The basic fneg cases are already autogen'd

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24592 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 368a8cf0f6bb2c8bfbb17f21c472a32a7859e74d..92593663020525e7c7fd70b1d9aa3953999fb070 100644 (file)
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -1062,10 +1062,8 @@ SDOperand PPCDAGToDAGISel::Select(SDOperand Op) {
                                       Val.getOperand(1), Val.getOperand(2));
       }
     }
-    if (Ty == MVT::f32)
-      return CurDAG->SelectNodeTo(N, PPC::FNEGS, MVT::f32, Val);
-    else
-      return CurDAG->SelectNodeTo(N, PPC::FNEGD, MVT::f64, Val);
+    // Other cases are autogenerated.
+    break;
   }
   case ISD::LOAD:
   case ISD::EXTLOAD: