bool FoundDef = false; // Not counting 2address def.
bool FoundUse = false;
bool FoundKill = false;
+ const TargetInstrDesc &TID = MII->getDesc();
for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MII->getOperand(i);
if (!MO.isReg())
if (Reg == 0)
continue;
if (Reg == OldReg) {
+ const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TID, i);
+ if (RC && !RC->contains(NewReg))
+ return false;
+
if (MO.isUse()) {
FoundUse = true;
if (MO.isKill())
while (++MII != MBB->end()) {
bool FoundUse = false;
bool FoundKill = false;
+ const TargetInstrDesc &TID = MII->getDesc();
for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MII->getOperand(i);
if (!MO.isReg())
if (Reg == OldReg) {
if (MO.isDef())
return false;
+
+ const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TID, i);
+ if (RC && !RC->contains(NewReg))
+ return false;
FoundUse = true;
if (MO.isKill())
FoundKill = true;
MachineBasicBlock *MBB = MI->getParent();
if (unsigned DstReg = TII->isLoadFromStackSlot(MI, OldFI)) {
if (PropagateForward(MI, MBB, DstReg, Reg)) {
+ DOUT << "Eliminated load: ";
+ DEBUG(MI->dump());
++NumLoadElim;
} else {
TII->copyRegToReg(*MBB, MI, DstReg, Reg, RC, RC);
}
} else if (unsigned SrcReg = TII->isStoreToStackSlot(MI, OldFI)) {
if (MI->killsRegister(SrcReg) && PropagateBackward(MI, MBB, SrcReg, Reg)) {
+ DOUT << "Eliminated store: ";
+ DEBUG(MI->dump());
++NumStoreElim;
} else {
TII->copyRegToReg(*MBB, MI, Reg, SrcReg, RC, RC);