pinctrl-names = "default", "idle", "udbg";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
pinctrl-1 = <&sdmmc0_gpio>;
- pinctrl-2 = <&uart2_xfer>;
+ pinctrl-2 = <&uart2_xfer &sdmmc0_dectn>;
cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
clock-names = "clk_mmc", "hclk_mmc";
pinctrl-names = "default", "idle", "udbg";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
pinctrl-1 = <&sdmmc0_gpio>;
- pinctrl-2 = <&uart2_xfer>;
+ pinctrl-2 = <&uart2_xfer &sdmmc0_dectn>;
clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
clock-names = "clk_mmc", "hclk_mmc";
dmas = <&pdma 10>;
CONFIG_USB_IPHETH=y
CONFIG_USB_SIERRA_NET=y
CONFIG_RTL8188EU=y
-CONFIG_RTL8189ES=m
-CONFIG_RTL8192DU=m
-CONFIG_RTL8723AU=m
-CONFIG_RTL8723BU=m
-CONFIG_RTL8723BS=m
-CONFIG_RTL8723BS_VQ0=m
-CONFIG_RTL8812AU=m
CONFIG_ESP8089=y
CONFIG_RKWIFI=y
CONFIG_AP6335=y
1) use of_find_node_by_name to get vpu node instead of of_find_compatible_node
*v0.0x1c.0:
1) support rk3368.
+*v0.0x1d.0:
+ 1) enable aclk_rga for rk3368, otherwise, isp reset will cause system halted.
*/
-#define CAMSYS_DRIVER_VERSION KERNEL_VERSION(0,0x1c,0)
+#define CAMSYS_DRIVER_VERSION KERNEL_VERSION(0,0x1d,0)
#define CAMSYS_PLATFORM_DRV_NAME "RockChip-CamSys"
if(CHIP_TYPE == 3368){
clk_prepare_enable(clk->cif_clk_out);
clk_prepare_enable(clk->pclk_dphyrx);
+ clk_prepare_enable(clk->aclk_rga);
}else{
clk_prepare_enable(clk->pd_isp);
clk_prepare_enable(clk->clk_mipi_24m);
clk_disable_unprepare(clk->hclk_isp);
clk_disable_unprepare(clk->isp);
clk_disable_unprepare(clk->isp_jpe);
- clk_disable_unprepare(clk->pclkin_isp);
+ clk_disable_unprepare(clk->pclkin_isp);
if(CHIP_TYPE == 3368){
clk_disable_unprepare(clk->cif_clk_out);
clk_disable_unprepare(clk->pclk_dphyrx);
+ clk_disable_unprepare(clk->aclk_rga);
}else{
clk_disable_unprepare(clk->clk_mipi_24m);
clk_disable_unprepare(clk->pd_isp);
mrv_clk->cif_clk_out = devm_clk_get(&pdev->dev, "clk_cif_out");
mrv_clk->cif_clk_pll = devm_clk_get(&pdev->dev, "clk_cif_pll");
mrv_clk->pclk_dphyrx = devm_clk_get(&pdev->dev, "pclk_dphyrx");
-
+ mrv_clk->aclk_rga = devm_clk_get(&pdev->dev, "aclk_rga");
if (IS_ERR_OR_NULL(mrv_clk->aclk_isp) || IS_ERR_OR_NULL(mrv_clk->hclk_isp) ||
IS_ERR_OR_NULL(mrv_clk->isp) || IS_ERR_OR_NULL(mrv_clk->isp_jpe) || IS_ERR_OR_NULL(mrv_clk->pclkin_isp) ||
- IS_ERR_OR_NULL(mrv_clk->cif_clk_out) || IS_ERR_OR_NULL(mrv_clk->pclk_dphyrx)) {
+ IS_ERR_OR_NULL(mrv_clk->cif_clk_out) || IS_ERR_OR_NULL(mrv_clk->pclk_dphyrx)||IS_ERR_OR_NULL(mrv_clk->aclk_rga)) {
camsys_err("Get %s clock resouce failed!\n",miscdev_name);
err = -EINVAL;
goto clk_failed;
if (!IS_ERR_OR_NULL(mrv_clk->pclk_dphyrx)) {
clk_put(mrv_clk->pclk_dphyrx);
}
+ if (!IS_ERR_OR_NULL(mrv_clk->aclk_rga)) {
+ clk_put(mrv_clk->aclk_rga);
+ }
}
kfree(mrv_clk);
struct clk *cif_clk_out;
struct clk *cif_clk_pll;
struct clk *pclk_dphyrx;
+ struct clk *aclk_rga;
unsigned int out_on;
#include <linux/rfkill-wlan.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
+#include <linux/log2.h>
#include "rk_sdmmc.h"
#include "rk_sdmmc_dbg.h"
#include <linux/regulator/rockchip_io_vol_domain.h>
u32 sg_elems = host->data->sg_len;
u32 fifoth_val, mburst;
u32 burst_limit = 0;
+ u32 idx, rx_wmark, tx_wmark;
int ret = 0;
/* Set external dma config: burst size, burst width*/
if (mburst > burst_limit) {
mburst = burst_limit;
- fifoth_val = SDMMC_SET_FIFOTH(mszs[3], mszs[3] - 1, (host->fifo_depth) / 2);
+ idx = (ilog2(mburst) > 0) ? (ilog2(mburst) - 1) : 0;
+
+ if (soc_is_rk3126b()) {
+ idx = 0;
+ rx_wmark = (host->fifo_depth) / 2 - 1;
+ } else {
+ rx_wmark = mszs[idx] - 1;
+ }
+
+ tx_wmark = (host->fifo_depth) / 2;
+ fifoth_val = SDMMC_SET_FIFOTH(idx, rx_wmark, tx_wmark);
+
mci_writel(host, FIFOTH, fifoth_val);
}
if (last_id != id) {
pr_info("[otg id chg] last id %d current id %d\n", last_id, id);
+
+ if (pldata->phy_status == USB_PHY_SUSPEND) {
+ pldata->clock_enable(pldata, 1);
+ pldata->phy_suspend(pldata, USB_PHY_ENABLED);
+ }
+
if (!id) { /* Force Host */
- if (pldata->phy_status == USB_PHY_SUSPEND) {
- pldata->clock_enable(pldata, 1);
- pldata->phy_suspend(pldata, USB_PHY_ENABLED);
- }
id_status_change(otg_dev->core_if, id);
} else { /* Force Device */
id_status_change(otg_dev->core_if, id);
1) add dev_name in struct camsys_devio_name_s;
*v0.a.0:
1) support external flash IC
+*v0.b.0:
+ 1) add CamSys_SensorBit0_CifBit4 in enum camsys_cifio_e.
*/
-#define CAMSYS_HEAD_VERSION KERNEL_VERSION(0,0xa,0)
+#define CAMSYS_HEAD_VERSION KERNEL_VERSION(0,0xb,0)
#define CAMSYS_MARVIN_DEVNAME "camsys_marvin"
#define CAMSYS_CIF0_DEVNAME "camsys_cif0"
typedef enum camsys_cifio_e {
CamSys_SensorBit0_CifBit0 = 0x00,
CamSys_SensorBit0_CifBit2 = 0x01,
+ CamSys_SensorBit0_CifBit4 = 0x02,
} camsys_cifio_t;
typedef struct camsys_cifphy_s {