goto bad_enable;
}
} else { /*single transfer*/
+ if ((!dma_t->addr) || (dma_t->count == 0)) {
+ printk(KERN_ERR "dma_enable: channel %d does not have leagal address or count\n", dma_ch);
+ goto bad_enable;
+ }
dma_t->buf.dma_address = (dma_addr_t)dma_t->addr;
dma_t->buf.length = dma_t->count;
}
rk28dma->dma_t.irqHandle = NULL;
rk28dma->dma_t.data = NULL;
- rk28dma->dma_t.sg = NULL;
+ rk28dma->dma_t.sg = NULL;
+ rk28dma->dma_t.addr = NULL;
+ rk28dma->dma_t.count = 0;
rk28dma->dma_llp_vir = NULL;
rk28dma->dma_llp_phy = NULL;
rk28dma->residue = 0;
int i, raw_status;
struct rk2818_dma *rk28dma;
- raw_status = read_dma_reg(DWDMA_RawBlock);
+ raw_status = read_dma_reg(DWDMA_RawTfr);
for (i = 0; i < MAX_DMA_CHANNELS; i++) {
if (raw_status & (1 << i)) {
rk2818_dma[i].dma_t.irqHandle = NULL;
rk2818_dma[i].dma_t.data = NULL;
rk2818_dma[i].dma_t.sg = NULL;
+ rk2818_dma[i].dma_t.addr = NULL;
+ rk2818_dma[i].dma_t.count = 0;
rk2818_dma[i].dma_t.d_ops = &rk2818_dma_ops;
dma_add(i, &rk2818_dma[i].dma_t);
typedef struct rk28_dma_llp llp_t;
struct rk28_dma_llp {
- u32 sar;
- u32 dar;
+ unsigned int sar;
+ unsigned int dar;
llp_t *llp;
- u32 ctll;
- u32 size;
+ unsigned int ctll;
+ unsigned int size;
};
struct rk28_dma_dev {
- u32 hd_if_r; /* hardware interface for reading */
- u32 hd_if_w; /* hardware interface for writing */
- u32 dev_addr_r; /* device basic addresss for reading */
- u32 dev_addr_w; /* device basic addresss for reading */
- u32 fifo_width; /* fifo width of device */
+ unsigned int hd_if_r; /* hardware interface for reading */
+ unsigned int hd_if_w; /* hardware interface for writing */
+ unsigned int dev_addr_r; /* device basic addresss for reading */
+ unsigned int dev_addr_w; /* device basic addresss for reading */
+ unsigned int fifo_width; /* fifo width of device */
};
struct rk2818_dma {
dma_t dma_t;
struct rk28_dma_dev *dev_info;/* basic address of sg in memory */
struct rk28_dma_llp *dma_llp_vir; /* virtual cpu addrress of linked list */
- u32 dma_llp_phy; /* physical bus address of linked list */
- u32 length; /* current transfer block */
- u32 residue; /* residue block of current dma transfer */
+ unsigned int dma_llp_phy; /* physical bus address of linked list */
+ unsigned int length; /* current transfer block */
+ unsigned int residue; /* residue block of current dma transfer */
spinlock_t lock;
};