Add a subtarget feature for the stfiwx instruction. I know the G5 has it,

but I don't know what other PPC impls do.  If someone could update the proc
table, I would appreciate it :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26421 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td
index 8b9e3a7ac140176e1a00f11fec728085d1b1b0bb..272f6d6a16a8068c123bffaadcab82c8d647030f 100644 (file)
--- a/lib/Target/PowerPC/PPC.td
+++ b/lib/Target/PowerPC/PPC.td
@@ -29,6 +29,8 @@ def FeatureGPUL      : SubtargetFeature<"gpul","IsGigaProcessor", "true",
                                         "Enable GPUL instructions">;
 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
                                         "Enable the fsqrt instruction">; 
+def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
+                                        "Enable the stfiwx instruction">; 
 
 //===----------------------------------------------------------------------===//
 // Register File Description
@@ -58,10 +60,10 @@ def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>;
 def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
 def : Processor<"750", G3Itineraries, []>;
 def : Processor<"970", G5Itineraries,
-                  [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
+                  [FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
                    Feature64Bit /*, Feature64BitRegs */]>;
 def : Processor<"g5", G5Itineraries,
-                  [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
+                  [FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
                    Feature64Bit /*, Feature64BitRegs */]>;
 
 

diff --git a/lib/Target/PowerPC/PPCSubtarget.h b/lib/Target/PowerPC/PPCSubtarget.h
index 3f1454ce527cbc957be698537176e33026f7932c..4f838741ad09905d9afdbf46639eda9388e6797c 100644 (file)
--- a/lib/Target/PowerPC/PPCSubtarget.h
+++ b/lib/Target/PowerPC/PPCSubtarget.h
@@ -37,6 +37,7 @@ protected:
   bool Has64BitRegs;
   bool HasAltivec;
   bool HasFSQRT;
+  bool HasSTFIWX;
   bool IsAIX;
   bool IsDarwin;
 public:
@@ -60,6 +61,7 @@ public:
   
 
   bool hasFSQRT() const { return HasFSQRT; }
+  bool hasSTFIWX() const { return HasSTFIWX; }
   bool has64BitRegs() const { return Has64BitRegs; }
   bool hasAltivec() const { return HasAltivec; }