#include <core/engine.h>
struct nvkm_gr {
- struct nvkm_engine base;
+ struct nvkm_engine engine;
/* Returns chipset-specific counts of units packed into an u64.
*/
#define nvkm_gr_create(p,e,c,y,d) \
nvkm_engine_create((p), (e), (c), (y), "PGRAPH", "graphics", (d))
#define nvkm_gr_destroy(d) \
- nvkm_engine_destroy(&(d)->base)
+ nvkm_engine_destroy(&(d)->engine)
#define nvkm_gr_init(d) \
- nvkm_engine_init(&(d)->base)
+ nvkm_engine_init(&(d)->engine)
#define nvkm_gr_fini(d,s) \
- nvkm_engine_fini(&(d)->base, (s))
+ nvkm_engine_fini(&(d)->engine, (s))
#define _nvkm_gr_dtor _nvkm_engine_dtor
#define _nvkm_gr_init _nvkm_engine_init
-nvkm-y += nvkm/engine/gr/ctxnv40.o
-nvkm-y += nvkm/engine/gr/ctxnv50.o
-nvkm-y += nvkm/engine/gr/ctxgf100.o
-nvkm-y += nvkm/engine/gr/ctxgf108.o
-nvkm-y += nvkm/engine/gr/ctxgf104.o
-nvkm-y += nvkm/engine/gr/ctxgf110.o
-nvkm-y += nvkm/engine/gr/ctxgf117.o
-nvkm-y += nvkm/engine/gr/ctxgf119.o
-nvkm-y += nvkm/engine/gr/ctxgk104.o
-nvkm-y += nvkm/engine/gr/ctxgk20a.o
-nvkm-y += nvkm/engine/gr/ctxgk110.o
-nvkm-y += nvkm/engine/gr/ctxgk110b.o
-nvkm-y += nvkm/engine/gr/ctxgk208.o
-nvkm-y += nvkm/engine/gr/ctxgm107.o
-nvkm-y += nvkm/engine/gr/ctxgm204.o
-nvkm-y += nvkm/engine/gr/ctxgm206.o
-nvkm-y += nvkm/engine/gr/ctxgm20b.o
nvkm-y += nvkm/engine/gr/nv04.o
nvkm-y += nvkm/engine/gr/nv10.o
nvkm-y += nvkm/engine/gr/nv20.o
nvkm-y += nvkm/engine/gr/gm204.o
nvkm-y += nvkm/engine/gr/gm206.o
nvkm-y += nvkm/engine/gr/gm20b.o
+
+nvkm-y += nvkm/engine/gr/ctxnv40.o
+nvkm-y += nvkm/engine/gr/ctxnv50.o
+nvkm-y += nvkm/engine/gr/ctxgf100.o
+nvkm-y += nvkm/engine/gr/ctxgf108.o
+nvkm-y += nvkm/engine/gr/ctxgf104.o
+nvkm-y += nvkm/engine/gr/ctxgf110.o
+nvkm-y += nvkm/engine/gr/ctxgf117.o
+nvkm-y += nvkm/engine/gr/ctxgf119.o
+nvkm-y += nvkm/engine/gr/ctxgk104.o
+nvkm-y += nvkm/engine/gr/ctxgk20a.o
+nvkm-y += nvkm/engine/gr/ctxgk110.o
+nvkm-y += nvkm/engine/gr/ctxgk110b.o
+nvkm-y += nvkm/engine/gr/ctxgk208.o
+nvkm-y += nvkm/engine/gr/ctxgm107.o
+nvkm-y += nvkm/engine/gr/ctxgm204.o
+nvkm-y += nvkm/engine/gr/ctxgm206.o
+nvkm-y += nvkm/engine/gr/ctxgm20b.o
return;
}
- nv_wr32(info->priv, addr, data);
+ nv_wr32(info->gr, addr, data);
}
void
gf100_grctx_generate_bundle(struct gf100_grctx *info)
{
- const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->bundle_size, (1 << s), access);
void
gf100_grctx_generate_pagepool(struct gf100_grctx *info)
{
- const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
void
gf100_grctx_generate_attrib(struct gf100_grctx *info)
{
- struct gf100_gr_priv *priv = info->priv;
- const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv);
+ struct gf100_gr *gr = info->gr;
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(gr);
const u32 attrib = impl->attrib_nr;
const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
const u32 access = NV_MEM_ACCESS_RW;
const int s = 12;
- const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access);
+ const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access);
int gpc, tpc;
u32 bo = 0;
mmio_refn(info, 0x419848, 0x10000000, s, b);
mmio_wr32(info, 0x405830, (attrib << 16));
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
const u32 o = TPC_UNIT(gpc, tpc, 0x0520);
mmio_skip(info, o, (attrib << 16) | ++bo);
mmio_wr32(info, o, (attrib << 16) | --bo);
}
void
-gf100_grctx_generate_unkn(struct gf100_gr_priv *priv)
+gf100_grctx_generate_unkn(struct gf100_gr *gr)
{
}
void
-gf100_grctx_generate_tpcid(struct gf100_gr_priv *priv)
+gf100_grctx_generate_tpcid(struct gf100_gr *gr)
{
int gpc, tpc, id;
for (tpc = 0, id = 0; tpc < 4; tpc++) {
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- if (tpc < priv->tpc_nr[gpc]) {
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x4e8), id);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id);
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ if (tpc < gr->tpc_nr[gpc]) {
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x698), id);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x4e8), id);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x088), id);
id++;
}
- nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]);
}
}
}
void
-gf100_grctx_generate_r406028(struct gf100_gr_priv *priv)
+gf100_grctx_generate_r406028(struct gf100_gr *gr)
{
u32 tmp[GPC_MAX / 8] = {}, i = 0;
- for (i = 0; i < priv->gpc_nr; i++)
- tmp[i / 8] |= priv->tpc_nr[i] << ((i % 8) * 4);
+ for (i = 0; i < gr->gpc_nr; i++)
+ tmp[i / 8] |= gr->tpc_nr[i] << ((i % 8) * 4);
for (i = 0; i < 4; i++) {
- nv_wr32(priv, 0x406028 + (i * 4), tmp[i]);
- nv_wr32(priv, 0x405870 + (i * 4), tmp[i]);
+ nv_wr32(gr, 0x406028 + (i * 4), tmp[i]);
+ nv_wr32(gr, 0x405870 + (i * 4), tmp[i]);
}
}
void
-gf100_grctx_generate_r4060a8(struct gf100_gr_priv *priv)
+gf100_grctx_generate_r4060a8(struct gf100_gr *gr)
{
u8 tpcnr[GPC_MAX], data[TPC_MAX];
int gpc, tpc, i;
- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
+ memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
memset(data, 0x1f, sizeof(data));
gpc = -1;
- for (tpc = 0; tpc < priv->tpc_total; tpc++) {
+ for (tpc = 0; tpc < gr->tpc_total; tpc++) {
do {
- gpc = (gpc + 1) % priv->gpc_nr;
+ gpc = (gpc + 1) % gr->gpc_nr;
} while (!tpcnr[gpc]);
tpcnr[gpc]--;
data[tpc] = gpc;
}
for (i = 0; i < 4; i++)
- nv_wr32(priv, 0x4060a8 + (i * 4), ((u32 *)data)[i]);
+ nv_wr32(gr, 0x4060a8 + (i * 4), ((u32 *)data)[i]);
}
void
-gf100_grctx_generate_r418bb8(struct gf100_gr_priv *priv)
+gf100_grctx_generate_r418bb8(struct gf100_gr *gr)
{
u32 data[6] = {}, data2[2] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc, i;
/* calculate first set of magics */
- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
+ memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
gpc = -1;
- for (tpc = 0; tpc < priv->tpc_total; tpc++) {
+ for (tpc = 0; tpc < gr->tpc_total; tpc++) {
do {
- gpc = (gpc + 1) % priv->gpc_nr;
+ gpc = (gpc + 1) % gr->gpc_nr;
} while (!tpcnr[gpc]);
tpcnr[gpc]--;
/* and the second... */
shift = 0;
- ntpcv = priv->tpc_total;
+ ntpcv = gr->tpc_total;
while (!(ntpcv & (1 << 4))) {
ntpcv <<= 1;
shift++;
data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
/* GPC_BROADCAST */
- nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) |
- priv->magic_not_rop_nr);
+ nv_wr32(gr, 0x418bb8, (gr->tpc_total << 8) |
+ gr->magic_not_rop_nr);
for (i = 0; i < 6; i++)
- nv_wr32(priv, 0x418b08 + (i * 4), data[i]);
+ nv_wr32(gr, 0x418b08 + (i * 4), data[i]);
/* GPC_BROADCAST.TP_BROADCAST */
- nv_wr32(priv, 0x419bd0, (priv->tpc_total << 8) |
- priv->magic_not_rop_nr | data2[0]);
- nv_wr32(priv, 0x419be4, data2[1]);
+ nv_wr32(gr, 0x419bd0, (gr->tpc_total << 8) |
+ gr->magic_not_rop_nr | data2[0]);
+ nv_wr32(gr, 0x419be4, data2[1]);
for (i = 0; i < 6; i++)
- nv_wr32(priv, 0x419b00 + (i * 4), data[i]);
+ nv_wr32(gr, 0x419b00 + (i * 4), data[i]);
/* UNK78xx */
- nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) |
- priv->magic_not_rop_nr);
+ nv_wr32(gr, 0x4078bc, (gr->tpc_total << 8) |
+ gr->magic_not_rop_nr);
for (i = 0; i < 6; i++)
- nv_wr32(priv, 0x40780c + (i * 4), data[i]);
+ nv_wr32(gr, 0x40780c + (i * 4), data[i]);
}
void
-gf100_grctx_generate_r406800(struct gf100_gr_priv *priv)
+gf100_grctx_generate_r406800(struct gf100_gr *gr)
{
u64 tpc_mask = 0, tpc_set = 0;
u8 tpcnr[GPC_MAX];
int gpc, tpc;
int i, a, b;
- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
- for (gpc = 0; gpc < priv->gpc_nr; gpc++)
- tpc_mask |= ((1ULL << priv->tpc_nr[gpc]) - 1) << (gpc * 8);
+ memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++)
+ tpc_mask |= ((1ULL << gr->tpc_nr[gpc]) - 1) << (gpc * 8);
for (i = 0, gpc = -1, b = -1; i < 32; i++) {
- a = (i * (priv->tpc_total - 1)) / 32;
+ a = (i * (gr->tpc_total - 1)) / 32;
if (a != b) {
b = a;
do {
- gpc = (gpc + 1) % priv->gpc_nr;
+ gpc = (gpc + 1) % gr->gpc_nr;
} while (!tpcnr[gpc]);
- tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
+ tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
tpc_set |= 1ULL << ((gpc * 8) + tpc);
}
- nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));
- nv_wr32(priv, 0x406c00 + (i * 0x20), lower_32_bits(tpc_set ^ tpc_mask));
- if (priv->gpc_nr > 4) {
- nv_wr32(priv, 0x406804 + (i * 0x20), upper_32_bits(tpc_set));
- nv_wr32(priv, 0x406c04 + (i * 0x20), upper_32_bits(tpc_set ^ tpc_mask));
+ nv_wr32(gr, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));
+ nv_wr32(gr, 0x406c00 + (i * 0x20), lower_32_bits(tpc_set ^ tpc_mask));
+ if (gr->gpc_nr > 4) {
+ nv_wr32(gr, 0x406804 + (i * 0x20), upper_32_bits(tpc_set));
+ nv_wr32(gr, 0x406c04 + (i * 0x20), upper_32_bits(tpc_set ^ tpc_mask));
}
}
}
void
-gf100_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
+gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
- struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 0);
- gf100_gr_mmio(priv, oclass->hub);
- gf100_gr_mmio(priv, oclass->gpc);
- gf100_gr_mmio(priv, oclass->zcull);
- gf100_gr_mmio(priv, oclass->tpc);
- gf100_gr_mmio(priv, oclass->ppc);
+ gf100_gr_mmio(gr, oclass->hub);
+ gf100_gr_mmio(gr, oclass->gpc);
+ gf100_gr_mmio(gr, oclass->zcull);
+ gf100_gr_mmio(gr, oclass->tpc);
+ gf100_gr_mmio(gr, oclass->ppc);
- nv_wr32(priv, 0x404154, 0x00000000);
+ nv_wr32(gr, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->pagepool(info);
oclass->attrib(info);
- oclass->unkn(priv);
-
- gf100_grctx_generate_tpcid(priv);
- gf100_grctx_generate_r406028(priv);
- gf100_grctx_generate_r4060a8(priv);
- gf100_grctx_generate_r418bb8(priv);
- gf100_grctx_generate_r406800(priv);
-
- gf100_gr_icmd(priv, oclass->icmd);
- nv_wr32(priv, 0x404154, 0x00000400);
- gf100_gr_mthd(priv, oclass->mthd);
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
+ oclass->unkn(gr);
+
+ gf100_grctx_generate_tpcid(gr);
+ gf100_grctx_generate_r406028(gr);
+ gf100_grctx_generate_r4060a8(gr);
+ gf100_grctx_generate_r418bb8(gr);
+ gf100_grctx_generate_r406800(gr);
+
+ gf100_gr_icmd(gr, oclass->icmd);
+ nv_wr32(gr, 0x404154, 0x00000400);
+ gf100_gr_mthd(gr, oclass->mthd);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
}
int
-gf100_grctx_generate(struct gf100_gr_priv *priv)
+gf100_grctx_generate(struct gf100_gr *gr)
{
- struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
- struct nvkm_bar *bar = nvkm_bar(priv);
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
+ struct nvkm_bar *bar = nvkm_bar(gr);
struct nvkm_gpuobj *chan;
struct gf100_grctx info;
int ret, i;
/* allocate memory to for a "channel", which we'll use to generate
* the default context values
*/
- ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x80000 + priv->size,
+ ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x80000 + gr->size,
0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan);
if (ret) {
- nv_error(priv, "failed to allocate channel memory, %d\n", ret);
+ nv_error(gr, "failed to allocate channel memory, %d\n", ret);
return ret;
}
bar->flush(bar);
- nv_wr32(priv, 0x100cb8, (chan->addr + 0x1000) >> 8);
- nv_wr32(priv, 0x100cbc, 0x80000001);
- nv_wait(priv, 0x100c80, 0x00008000, 0x00008000);
+ nv_wr32(gr, 0x100cb8, (chan->addr + 0x1000) >> 8);
+ nv_wr32(gr, 0x100cbc, 0x80000001);
+ nv_wait(gr, 0x100c80, 0x00008000, 0x00008000);
/* setup default state for mmio list construction */
- info.priv = priv;
- info.data = priv->mmio_data;
- info.mmio = priv->mmio_list;
+ info.gr = gr;
+ info.data = gr->mmio_data;
+ info.mmio = gr->mmio_list;
info.addr = 0x2000 + (i * 8);
info.buffer_nr = 0;
/* make channel current */
- if (priv->firmware) {
- nv_wr32(priv, 0x409840, 0x00000030);
- nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12);
- nv_wr32(priv, 0x409504, 0x00000003);
- if (!nv_wait(priv, 0x409800, 0x00000010, 0x00000010))
- nv_error(priv, "load_ctx timeout\n");
+ if (gr->firmware) {
+ nv_wr32(gr, 0x409840, 0x00000030);
+ nv_wr32(gr, 0x409500, 0x80000000 | chan->addr >> 12);
+ nv_wr32(gr, 0x409504, 0x00000003);
+ if (!nv_wait(gr, 0x409800, 0x00000010, 0x00000010))
+ nv_error(gr, "load_ctx timeout\n");
nv_wo32(chan, 0x8001c, 1);
nv_wo32(chan, 0x80020, 0);
nv_wo32(chan, 0x8002c, 0);
bar->flush(bar);
} else {
- nv_wr32(priv, 0x409840, 0x80000000);
- nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12);
- nv_wr32(priv, 0x409504, 0x00000001);
- if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000))
- nv_error(priv, "HUB_SET_CHAN timeout\n");
+ nv_wr32(gr, 0x409840, 0x80000000);
+ nv_wr32(gr, 0x409500, 0x80000000 | chan->addr >> 12);
+ nv_wr32(gr, 0x409504, 0x00000001);
+ if (!nv_wait(gr, 0x409800, 0x80000000, 0x80000000))
+ nv_error(gr, "HUB_SET_CHAN timeout\n");
}
- oclass->main(priv, &info);
+ oclass->main(gr, &info);
/* trigger a context unload by unsetting the "next channel valid" bit
* and faking a context switch interrupt
*/
- nv_mask(priv, 0x409b04, 0x80000000, 0x00000000);
- nv_wr32(priv, 0x409000, 0x00000100);
- if (!nv_wait(priv, 0x409b00, 0x80000000, 0x00000000)) {
- nv_error(priv, "grctx template channel unload timeout\n");
+ nv_mask(gr, 0x409b04, 0x80000000, 0x00000000);
+ nv_wr32(gr, 0x409000, 0x00000100);
+ if (!nv_wait(gr, 0x409b00, 0x80000000, 0x00000000)) {
+ nv_error(gr, "grctx template channel unload timeout\n");
ret = -EBUSY;
goto done;
}
- priv->data = kmalloc(priv->size, GFP_KERNEL);
- if (priv->data) {
- for (i = 0; i < priv->size; i += 4)
- priv->data[i / 4] = nv_ro32(chan, 0x80000 + i);
+ gr->data = kmalloc(gr->size, GFP_KERNEL);
+ if (gr->data) {
+ for (i = 0; i < gr->size; i += 4)
+ gr->data[i / 4] = nv_ro32(chan, 0x80000 + i);
ret = 0;
} else {
ret = -ENOMEM;
#include "gf100.h"
struct gf100_grctx {
- struct gf100_gr_priv *priv;
+ struct gf100_gr *gr;
struct gf100_gr_data *data;
struct gf100_gr_mmio *mmio;
int buffer_nr;
struct gf100_grctx_oclass {
struct nvkm_oclass base;
/* main context generation function */
- void (*main)(struct gf100_gr_priv *, struct gf100_grctx *);
+ void (*main)(struct gf100_gr *, struct gf100_grctx *);
/* context-specific modify-on-first-load list generation function */
- void (*unkn)(struct gf100_gr_priv *);
+ void (*unkn)(struct gf100_gr *);
/* mmio context data */
const struct gf100_gr_pack *hub;
const struct gf100_gr_pack *gpc;
};
static inline const struct gf100_grctx_oclass *
-gf100_grctx_impl(struct gf100_gr_priv *priv)
+gf100_grctx_impl(struct gf100_gr *gr)
{
- return (void *)nv_engine(priv)->cclass;
+ return (void *)nv_engine(gr)->cclass;
}
extern struct nvkm_oclass *gf100_grctx_oclass;
-int gf100_grctx_generate(struct gf100_gr_priv *);
-void gf100_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *);
+int gf100_grctx_generate(struct gf100_gr *);
+void gf100_grctx_generate_main(struct gf100_gr *, struct gf100_grctx *);
void gf100_grctx_generate_bundle(struct gf100_grctx *);
void gf100_grctx_generate_pagepool(struct gf100_grctx *);
void gf100_grctx_generate_attrib(struct gf100_grctx *);
-void gf100_grctx_generate_unkn(struct gf100_gr_priv *);
-void gf100_grctx_generate_tpcid(struct gf100_gr_priv *);
-void gf100_grctx_generate_r406028(struct gf100_gr_priv *);
-void gf100_grctx_generate_r4060a8(struct gf100_gr_priv *);
-void gf100_grctx_generate_r418bb8(struct gf100_gr_priv *);
-void gf100_grctx_generate_r406800(struct gf100_gr_priv *);
+void gf100_grctx_generate_unkn(struct gf100_gr *);
+void gf100_grctx_generate_tpcid(struct gf100_gr *);
+void gf100_grctx_generate_r406028(struct gf100_gr *);
+void gf100_grctx_generate_r4060a8(struct gf100_gr *);
+void gf100_grctx_generate_r418bb8(struct gf100_gr *);
+void gf100_grctx_generate_r406800(struct gf100_gr *);
extern struct nvkm_oclass *gf108_grctx_oclass;
void gf108_grctx_generate_attrib(struct gf100_grctx *);
-void gf108_grctx_generate_unkn(struct gf100_gr_priv *);
+void gf108_grctx_generate_unkn(struct gf100_gr *);
extern struct nvkm_oclass *gf104_grctx_oclass;
extern struct nvkm_oclass *gf110_grctx_oclass;
extern struct nvkm_oclass *gk104_grctx_oclass;
extern struct nvkm_oclass *gk20a_grctx_oclass;
-void gk104_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *);
+void gk104_grctx_generate_main(struct gf100_gr *, struct gf100_grctx *);
void gk104_grctx_generate_bundle(struct gf100_grctx *);
void gk104_grctx_generate_pagepool(struct gf100_grctx *);
-void gk104_grctx_generate_unkn(struct gf100_gr_priv *);
-void gk104_grctx_generate_r418bb8(struct gf100_gr_priv *);
-void gk104_grctx_generate_rop_active_fbps(struct gf100_gr_priv *);
+void gk104_grctx_generate_unkn(struct gf100_gr *);
+void gk104_grctx_generate_r418bb8(struct gf100_gr *);
+void gk104_grctx_generate_rop_active_fbps(struct gf100_gr *);
void gm107_grctx_generate_bundle(struct gf100_grctx *);
void gm107_grctx_generate_attrib(struct gf100_grctx *);
extern struct nvkm_oclass *gm204_grctx_oclass;
-void gm204_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *);
-void gm204_grctx_generate_tpcid(struct gf100_gr_priv *);
-void gm204_grctx_generate_405b60(struct gf100_gr_priv *);
+void gm204_grctx_generate_main(struct gf100_gr *, struct gf100_grctx *);
+void gm204_grctx_generate_tpcid(struct gf100_gr *);
+void gm204_grctx_generate_405b60(struct gf100_gr *);
extern struct nvkm_oclass *gm206_grctx_oclass;
extern struct nvkm_oclass *gm20b_grctx_oclass;
void
gf108_grctx_generate_attrib(struct gf100_grctx *info)
{
- struct gf100_gr_priv *priv = info->priv;
- const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv);
+ struct gf100_gr *gr = info->gr;
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(gr);
const u32 alpha = impl->alpha_nr;
const u32 beta = impl->attrib_nr;
const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
const u32 access = NV_MEM_ACCESS_RW;
const int s = 12;
- const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access);
+ const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access);
const int timeslice_mode = 1;
const int max_batches = 0xffff;
u32 bo = 0;
- u32 ao = bo + impl->attrib_nr_max * priv->tpc_total;
+ u32 ao = bo + impl->attrib_nr_max * gr->tpc_total;
int gpc, tpc;
mmio_refn(info, 0x418810, 0x80000000, s, b);
mmio_wr32(info, 0x405830, (beta << 16) | alpha);
mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
const u32 a = alpha;
const u32 b = beta;
const u32 t = timeslice_mode;
}
void
-gf108_grctx_generate_unkn(struct gf100_gr_priv *priv)
+gf108_grctx_generate_unkn(struct gf100_gr *gr)
{
- nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
- nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
- nv_mask(priv, 0x419814, 0x00000004, 0x00000004);
- nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000);
- nv_mask(priv, 0x405800, 0x08000000, 0x08000000);
- nv_mask(priv, 0x419c00, 0x00000008, 0x00000008);
+ nv_mask(gr, 0x418c6c, 0x00000001, 0x00000001);
+ nv_mask(gr, 0x41980c, 0x00000010, 0x00000010);
+ nv_mask(gr, 0x419814, 0x00000004, 0x00000004);
+ nv_mask(gr, 0x4064c0, 0x80000000, 0x80000000);
+ nv_mask(gr, 0x405800, 0x08000000, 0x08000000);
+ nv_mask(gr, 0x419c00, 0x00000008, 0x00000008);
}
struct nvkm_oclass *
void
gf117_grctx_generate_attrib(struct gf100_grctx *info)
{
- struct gf100_gr_priv *priv = info->priv;
- const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv);
+ struct gf100_gr *gr = info->gr;
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(gr);
const u32 alpha = impl->alpha_nr;
const u32 beta = impl->attrib_nr;
const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
const u32 access = NV_MEM_ACCESS_RW;
const int s = 12;
- const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access);
+ const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access);
const int timeslice_mode = 1;
const int max_batches = 0xffff;
u32 bo = 0;
- u32 ao = bo + impl->attrib_nr_max * priv->tpc_total;
+ u32 ao = bo + impl->attrib_nr_max * gr->tpc_total;
int gpc, ppc;
mmio_refn(info, 0x418810, 0x80000000, s, b);
mmio_wr32(info, 0x405830, (beta << 16) | alpha);
mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++) {
- const u32 a = alpha * priv->ppc_tpc_nr[gpc][ppc];
- const u32 b = beta * priv->ppc_tpc_nr[gpc][ppc];
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) {
+ const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc];
+ const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc];
const u32 t = timeslice_mode;
const u32 o = PPC_UNIT(gpc, ppc, 0);
mmio_skip(info, o + 0xc0, (t << 28) | (b << 16) | ++bo);
mmio_wr32(info, o + 0xc0, (t << 28) | (b << 16) | --bo);
- bo += impl->attrib_nr_max * priv->ppc_tpc_nr[gpc][ppc];
+ bo += impl->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc];
mmio_wr32(info, o + 0xe4, (a << 16) | ao);
- ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc];
+ ao += impl->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
}
}
}
void
-gf117_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
+gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
- struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
int i;
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 0);
- gf100_gr_mmio(priv, oclass->hub);
- gf100_gr_mmio(priv, oclass->gpc);
- gf100_gr_mmio(priv, oclass->zcull);
- gf100_gr_mmio(priv, oclass->tpc);
- gf100_gr_mmio(priv, oclass->ppc);
+ gf100_gr_mmio(gr, oclass->hub);
+ gf100_gr_mmio(gr, oclass->gpc);
+ gf100_gr_mmio(gr, oclass->zcull);
+ gf100_gr_mmio(gr, oclass->tpc);
+ gf100_gr_mmio(gr, oclass->ppc);
- nv_wr32(priv, 0x404154, 0x00000000);
+ nv_wr32(gr, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->pagepool(info);
oclass->attrib(info);
- oclass->unkn(priv);
+ oclass->unkn(gr);
- gf100_grctx_generate_tpcid(priv);
- gf100_grctx_generate_r406028(priv);
- gf100_grctx_generate_r4060a8(priv);
- gk104_grctx_generate_r418bb8(priv);
- gf100_grctx_generate_r406800(priv);
+ gf100_grctx_generate_tpcid(gr);
+ gf100_grctx_generate_r406028(gr);
+ gf100_grctx_generate_r4060a8(gr);
+ gk104_grctx_generate_r418bb8(gr);
+ gf100_grctx_generate_r406800(gr);
for (i = 0; i < 8; i++)
- nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
+ nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000);
- gf100_gr_icmd(priv, oclass->icmd);
- nv_wr32(priv, 0x404154, 0x00000400);
- gf100_gr_mthd(priv, oclass->mthd);
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
+ gf100_gr_icmd(gr, oclass->icmd);
+ nv_wr32(gr, 0x404154, 0x00000400);
+ gf100_gr_mthd(gr, oclass->mthd);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
}
struct nvkm_oclass *
void
gk104_grctx_generate_bundle(struct gf100_grctx *info)
{
- const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr);
const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth,
impl->bundle_size / 0x20);
const u32 token_limit = impl->bundle_token_limit;
void
gk104_grctx_generate_pagepool(struct gf100_grctx *info)
{
- const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
}
void
-gk104_grctx_generate_unkn(struct gf100_gr_priv *priv)
+gk104_grctx_generate_unkn(struct gf100_gr *gr)
{
- nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
- nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
- nv_mask(priv, 0x41be08, 0x00000004, 0x00000004);
- nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000);
- nv_mask(priv, 0x405800, 0x08000000, 0x08000000);
- nv_mask(priv, 0x419c00, 0x00000008, 0x00000008);
+ nv_mask(gr, 0x418c6c, 0x00000001, 0x00000001);
+ nv_mask(gr, 0x41980c, 0x00000010, 0x00000010);
+ nv_mask(gr, 0x41be08, 0x00000004, 0x00000004);
+ nv_mask(gr, 0x4064c0, 0x80000000, 0x80000000);
+ nv_mask(gr, 0x405800, 0x08000000, 0x08000000);
+ nv_mask(gr, 0x419c00, 0x00000008, 0x00000008);
}
void
-gk104_grctx_generate_r418bb8(struct gf100_gr_priv *priv)
+gk104_grctx_generate_r418bb8(struct gf100_gr *gr)
{
u32 data[6] = {}, data2[2] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc, i;
/* calculate first set of magics */
- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
+ memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
gpc = -1;
- for (tpc = 0; tpc < priv->tpc_total; tpc++) {
+ for (tpc = 0; tpc < gr->tpc_total; tpc++) {
do {
- gpc = (gpc + 1) % priv->gpc_nr;
+ gpc = (gpc + 1) % gr->gpc_nr;
} while (!tpcnr[gpc]);
tpcnr[gpc]--;
/* and the second... */
shift = 0;
- ntpcv = priv->tpc_total;
+ ntpcv = gr->tpc_total;
while (!(ntpcv & (1 << 4))) {
ntpcv <<= 1;
shift++;
data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
/* GPC_BROADCAST */
- nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) |
- priv->magic_not_rop_nr);
+ nv_wr32(gr, 0x418bb8, (gr->tpc_total << 8) |
+ gr->magic_not_rop_nr);
for (i = 0; i < 6; i++)
- nv_wr32(priv, 0x418b08 + (i * 4), data[i]);
+ nv_wr32(gr, 0x418b08 + (i * 4), data[i]);
/* GPC_BROADCAST.TP_BROADCAST */
- nv_wr32(priv, 0x41bfd0, (priv->tpc_total << 8) |
- priv->magic_not_rop_nr | data2[0]);
- nv_wr32(priv, 0x41bfe4, data2[1]);
+ nv_wr32(gr, 0x41bfd0, (gr->tpc_total << 8) |
+ gr->magic_not_rop_nr | data2[0]);
+ nv_wr32(gr, 0x41bfe4, data2[1]);
for (i = 0; i < 6; i++)
- nv_wr32(priv, 0x41bf00 + (i * 4), data[i]);
+ nv_wr32(gr, 0x41bf00 + (i * 4), data[i]);
/* UNK78xx */
- nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) |
- priv->magic_not_rop_nr);
+ nv_wr32(gr, 0x4078bc, (gr->tpc_total << 8) |
+ gr->magic_not_rop_nr);
for (i = 0; i < 6; i++)
- nv_wr32(priv, 0x40780c + (i * 4), data[i]);
+ nv_wr32(gr, 0x40780c + (i * 4), data[i]);
}
void
-gk104_grctx_generate_rop_active_fbps(struct gf100_gr_priv *priv)
+gk104_grctx_generate_rop_active_fbps(struct gf100_gr *gr)
{
- const u32 fbp_count = nv_rd32(priv, 0x120074);
- nv_mask(priv, 0x408850, 0x0000000f, fbp_count); /* zrop */
- nv_mask(priv, 0x408958, 0x0000000f, fbp_count); /* crop */
+ const u32 fbp_count = nv_rd32(gr, 0x120074);
+ nv_mask(gr, 0x408850, 0x0000000f, fbp_count); /* zrop */
+ nv_mask(gr, 0x408958, 0x0000000f, fbp_count); /* crop */
}
void
-gk104_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
+gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
- struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
int i;
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 0);
- gf100_gr_mmio(priv, oclass->hub);
- gf100_gr_mmio(priv, oclass->gpc);
- gf100_gr_mmio(priv, oclass->zcull);
- gf100_gr_mmio(priv, oclass->tpc);
- gf100_gr_mmio(priv, oclass->ppc);
+ gf100_gr_mmio(gr, oclass->hub);
+ gf100_gr_mmio(gr, oclass->gpc);
+ gf100_gr_mmio(gr, oclass->zcull);
+ gf100_gr_mmio(gr, oclass->tpc);
+ gf100_gr_mmio(gr, oclass->ppc);
- nv_wr32(priv, 0x404154, 0x00000000);
+ nv_wr32(gr, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->pagepool(info);
oclass->attrib(info);
- oclass->unkn(priv);
+ oclass->unkn(gr);
- gf100_grctx_generate_tpcid(priv);
- gf100_grctx_generate_r406028(priv);
- gk104_grctx_generate_r418bb8(priv);
- gf100_grctx_generate_r406800(priv);
+ gf100_grctx_generate_tpcid(gr);
+ gf100_grctx_generate_r406028(gr);
+ gk104_grctx_generate_r418bb8(gr);
+ gf100_grctx_generate_r406800(gr);
for (i = 0; i < 8; i++)
- nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
+ nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000);
- nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
- gk104_grctx_generate_rop_active_fbps(priv);
- nv_mask(priv, 0x419f78, 0x00000001, 0x00000000);
+ nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
+ gk104_grctx_generate_rop_active_fbps(gr);
+ nv_mask(gr, 0x419f78, 0x00000001, 0x00000000);
- gf100_gr_icmd(priv, oclass->icmd);
- nv_wr32(priv, 0x404154, 0x00000400);
- gf100_gr_mthd(priv, oclass->mthd);
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
+ gf100_gr_icmd(gr, oclass->icmd);
+ nv_wr32(gr, 0x404154, 0x00000400);
+ gf100_gr_mthd(gr, oclass->mthd);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
- nv_mask(priv, 0x418800, 0x00200000, 0x00200000);
- nv_mask(priv, 0x41be10, 0x00800000, 0x00800000);
+ nv_mask(gr, 0x418800, 0x00200000, 0x00200000);
+ nv_mask(gr, 0x41be10, 0x00800000, 0x00800000);
}
struct nvkm_oclass *
#include <subdev/mc.h>
static void
-gk20a_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
+gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
- struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
int idle_timeout_save;
int i;
- gf100_gr_mmio(priv, priv->fuc_sw_ctx);
+ gf100_gr_mmio(gr, gr->fuc_sw_ctx);
- gf100_gr_wait_idle(priv);
+ gf100_gr_wait_idle(gr);
- idle_timeout_save = nv_rd32(priv, 0x404154);
- nv_wr32(priv, 0x404154, 0x00000000);
+ idle_timeout_save = nv_rd32(gr, 0x404154);
+ nv_wr32(gr, 0x404154, 0x00000000);
oclass->attrib(info);
- oclass->unkn(priv);
+ oclass->unkn(gr);
- gf100_grctx_generate_tpcid(priv);
- gf100_grctx_generate_r406028(priv);
- gk104_grctx_generate_r418bb8(priv);
- gf100_grctx_generate_r406800(priv);
+ gf100_grctx_generate_tpcid(gr);
+ gf100_grctx_generate_r406028(gr);
+ gk104_grctx_generate_r418bb8(gr);
+ gf100_grctx_generate_r406800(gr);
for (i = 0; i < 8; i++)
- nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
+ nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000);
- nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
+ nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
- gk104_grctx_generate_rop_active_fbps(priv);
+ gk104_grctx_generate_rop_active_fbps(gr);
- nv_mask(priv, 0x5044b0, 0x8000000, 0x8000000);
+ nv_mask(gr, 0x5044b0, 0x8000000, 0x8000000);
- gf100_gr_wait_idle(priv);
+ gf100_gr_wait_idle(gr);
- nv_wr32(priv, 0x404154, idle_timeout_save);
- gf100_gr_wait_idle(priv);
+ nv_wr32(gr, 0x404154, idle_timeout_save);
+ gf100_gr_wait_idle(gr);
- gf100_gr_mthd(priv, priv->fuc_method);
- gf100_gr_wait_idle(priv);
+ gf100_gr_mthd(gr, gr->fuc_method);
+ gf100_gr_wait_idle(gr);
- gf100_gr_icmd(priv, priv->fuc_bundle);
+ gf100_gr_icmd(gr, gr->fuc_bundle);
oclass->pagepool(info);
oclass->bundle(info);
}
void
gm107_grctx_generate_bundle(struct gf100_grctx *info)
{
- const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr);
const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth,
impl->bundle_size / 0x20);
const u32 token_limit = impl->bundle_token_limit;
void
gm107_grctx_generate_pagepool(struct gf100_grctx *info)
{
- const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
void
gm107_grctx_generate_attrib(struct gf100_grctx *info)
{
- struct gf100_gr_priv *priv = info->priv;
- const struct gf100_grctx_oclass *impl = (void *)gf100_grctx_impl(priv);
+ struct gf100_gr *gr = info->gr;
+ const struct gf100_grctx_oclass *impl = (void *)gf100_grctx_impl(gr);
const u32 alpha = impl->alpha_nr;
const u32 attrib = impl->attrib_nr;
const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
const u32 access = NV_MEM_ACCESS_RW;
const int s = 12;
- const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access);
+ const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access);
const int max_batches = 0xffff;
u32 bo = 0;
- u32 ao = bo + impl->attrib_nr_max * priv->tpc_total;
+ u32 ao = bo + impl->attrib_nr_max * gr->tpc_total;
int gpc, ppc, n = 0;
mmio_refn(info, 0x418810, 0x80000000, s, b);
mmio_wr32(info, 0x405830, (attrib << 16) | alpha);
mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++, n++) {
- const u32 as = alpha * priv->ppc_tpc_nr[gpc][ppc];
- const u32 bs = attrib * priv->ppc_tpc_nr[gpc][ppc];
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) {
+ const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc];
+ const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc];
const u32 u = 0x418ea0 + (n * 0x04);
const u32 o = PPC_UNIT(gpc, ppc, 0);
mmio_wr32(info, o + 0xc0, bs);
mmio_wr32(info, o + 0xf4, bo);
- bo += impl->attrib_nr_max * priv->ppc_tpc_nr[gpc][ppc];
+ bo += impl->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc];
mmio_wr32(info, o + 0xe4, as);
mmio_wr32(info, o + 0xf8, ao);
- ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc];
+ ao += impl->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
mmio_wr32(info, u, ((bs / 3 /*XXX*/) << 16) | bs);
}
}
}
void
-gm107_grctx_generate_tpcid(struct gf100_gr_priv *priv)
+gm107_grctx_generate_tpcid(struct gf100_gr *gr)
{
int gpc, tpc, id;
for (tpc = 0, id = 0; tpc < 4; tpc++) {
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- if (tpc < priv->tpc_nr[gpc]) {
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id);
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ if (tpc < gr->tpc_nr[gpc]) {
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x698), id);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x088), id);
id++;
}
- nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]);
}
}
}
static void
-gm107_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
+gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
- struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
int i;
- gf100_gr_mmio(priv, oclass->hub);
- gf100_gr_mmio(priv, oclass->gpc);
- gf100_gr_mmio(priv, oclass->zcull);
- gf100_gr_mmio(priv, oclass->tpc);
- gf100_gr_mmio(priv, oclass->ppc);
+ gf100_gr_mmio(gr, oclass->hub);
+ gf100_gr_mmio(gr, oclass->gpc);
+ gf100_gr_mmio(gr, oclass->zcull);
+ gf100_gr_mmio(gr, oclass->tpc);
+ gf100_gr_mmio(gr, oclass->ppc);
- nv_wr32(priv, 0x404154, 0x00000000);
+ nv_wr32(gr, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->pagepool(info);
oclass->attrib(info);
- oclass->unkn(priv);
+ oclass->unkn(gr);
- gm107_grctx_generate_tpcid(priv);
- gf100_grctx_generate_r406028(priv);
- gk104_grctx_generate_r418bb8(priv);
- gf100_grctx_generate_r406800(priv);
+ gm107_grctx_generate_tpcid(gr);
+ gf100_grctx_generate_r406028(gr);
+ gk104_grctx_generate_r418bb8(gr);
+ gf100_grctx_generate_r406800(gr);
- nv_wr32(priv, 0x4064d0, 0x00000001);
+ nv_wr32(gr, 0x4064d0, 0x00000001);
for (i = 1; i < 8; i++)
- nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
- nv_wr32(priv, 0x406500, 0x00000001);
+ nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000);
+ nv_wr32(gr, 0x406500, 0x00000001);
- nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
+ nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
- gk104_grctx_generate_rop_active_fbps(priv);
+ gk104_grctx_generate_rop_active_fbps(gr);
- gf100_gr_icmd(priv, oclass->icmd);
- nv_wr32(priv, 0x404154, 0x00000400);
- gf100_gr_mthd(priv, oclass->mthd);
+ gf100_gr_icmd(gr, oclass->icmd);
+ nv_wr32(gr, 0x404154, 0x00000400);
+ gf100_gr_mthd(gr, oclass->mthd);
- nv_mask(priv, 0x419e00, 0x00808080, 0x00808080);
- nv_mask(priv, 0x419ccc, 0x80000000, 0x80000000);
- nv_mask(priv, 0x419f80, 0x80000000, 0x80000000);
- nv_mask(priv, 0x419f88, 0x80000000, 0x80000000);
+ nv_mask(gr, 0x419e00, 0x00808080, 0x00808080);
+ nv_mask(gr, 0x419ccc, 0x80000000, 0x80000000);
+ nv_mask(gr, 0x419f80, 0x80000000, 0x80000000);
+ nv_mask(gr, 0x419f88, 0x80000000, 0x80000000);
}
struct nvkm_oclass *
******************************************************************************/
void
-gm204_grctx_generate_tpcid(struct gf100_gr_priv *priv)
+gm204_grctx_generate_tpcid(struct gf100_gr *gr)
{
int gpc, tpc, id;
for (tpc = 0, id = 0; tpc < 4; tpc++) {
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- if (tpc < priv->tpc_nr[gpc]) {
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id);
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ if (tpc < gr->tpc_nr[gpc]) {
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x698), id);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x088), id);
id++;
}
}
}
static void
-gm204_grctx_generate_rop_active_fbps(struct gf100_gr_priv *priv)
+gm204_grctx_generate_rop_active_fbps(struct gf100_gr *gr)
{
- const u32 fbp_count = nv_rd32(priv, 0x12006c);
- nv_mask(priv, 0x408850, 0x0000000f, fbp_count); /* zrop */
- nv_mask(priv, 0x408958, 0x0000000f, fbp_count); /* crop */
+ const u32 fbp_count = nv_rd32(gr, 0x12006c);
+ nv_mask(gr, 0x408850, 0x0000000f, fbp_count); /* zrop */
+ nv_mask(gr, 0x408958, 0x0000000f, fbp_count); /* crop */
}
void
-gm204_grctx_generate_405b60(struct gf100_gr_priv *priv)
+gm204_grctx_generate_405b60(struct gf100_gr *gr)
{
- const u32 dist_nr = DIV_ROUND_UP(priv->tpc_total, 4);
- u32 dist[TPC_MAX] = {};
+ const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4);
+ u32 dist[TPC_MAX / 4] = {};
u32 gpcs[GPC_MAX] = {};
u8 tpcnr[GPC_MAX];
int tpc, gpc, i;
- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
+ memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
/* won't result in the same distribution as the binary driver where
* some of the gpcs have more tpcs than others, but this shall do
* for the moment. the code for earlier gpus has this issue too.
*/
- for (gpc = -1, i = 0; i < priv->tpc_total; i++) {
+ for (gpc = -1, i = 0; i < gr->tpc_total; i++) {
do {
- gpc = (gpc + 1) % priv->gpc_nr;
+ gpc = (gpc + 1) % gr->gpc_nr;
} while(!tpcnr[gpc]);
- tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
+ tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
dist[i / 4] |= ((gpc << 4) | tpc) << ((i % 4) * 8);
gpcs[gpc] |= i << (tpc * 8);
}
for (i = 0; i < dist_nr; i++)
- nv_wr32(priv, 0x405b60 + (i * 4), dist[i]);
- for (i = 0; i < priv->gpc_nr; i++)
- nv_wr32(priv, 0x405ba0 + (i * 4), gpcs[i]);
+ nv_wr32(gr, 0x405b60 + (i * 4), dist[i]);
+ for (i = 0; i < gr->gpc_nr; i++)
+ nv_wr32(gr, 0x405ba0 + (i * 4), gpcs[i]);
}
void
-gm204_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
+gm204_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
- struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
u32 tmp;
int i;
- gf100_gr_mmio(priv, oclass->hub);
- gf100_gr_mmio(priv, oclass->gpc);
- gf100_gr_mmio(priv, oclass->zcull);
- gf100_gr_mmio(priv, oclass->tpc);
- gf100_gr_mmio(priv, oclass->ppc);
+ gf100_gr_mmio(gr, oclass->hub);
+ gf100_gr_mmio(gr, oclass->gpc);
+ gf100_gr_mmio(gr, oclass->zcull);
+ gf100_gr_mmio(gr, oclass->tpc);
+ gf100_gr_mmio(gr, oclass->ppc);
- nv_wr32(priv, 0x404154, 0x00000000);
+ nv_wr32(gr, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->pagepool(info);
oclass->attrib(info);
- oclass->unkn(priv);
+ oclass->unkn(gr);
- gm204_grctx_generate_tpcid(priv);
- gf100_grctx_generate_r406028(priv);
- gk104_grctx_generate_r418bb8(priv);
+ gm204_grctx_generate_tpcid(gr);
+ gf100_grctx_generate_r406028(gr);
+ gk104_grctx_generate_r418bb8(gr);
for (i = 0; i < 8; i++)
- nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
- nv_wr32(priv, 0x406500, 0x00000000);
+ nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000);
+ nv_wr32(gr, 0x406500, 0x00000000);
- nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
+ nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
- gm204_grctx_generate_rop_active_fbps(priv);
+ gm204_grctx_generate_rop_active_fbps(gr);
- for (tmp = 0, i = 0; i < priv->gpc_nr; i++)
- tmp |= ((1 << priv->tpc_nr[i]) - 1) << (i * 4);
- nv_wr32(priv, 0x4041c4, tmp);
+ for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
+ tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4);
+ nv_wr32(gr, 0x4041c4, tmp);
- gm204_grctx_generate_405b60(priv);
+ gm204_grctx_generate_405b60(gr);
- gf100_gr_icmd(priv, oclass->icmd);
- nv_wr32(priv, 0x404154, 0x00000800);
- gf100_gr_mthd(priv, oclass->mthd);
+ gf100_gr_icmd(gr, oclass->icmd);
+ nv_wr32(gr, 0x404154, 0x00000800);
+ gf100_gr_mthd(gr, oclass->mthd);
- nv_mask(priv, 0x418e94, 0xffffffff, 0xc4230000);
- nv_mask(priv, 0x418e4c, 0xffffffff, 0x70000000);
+ nv_mask(gr, 0x418e94, 0xffffffff, 0xc4230000);
+ nv_mask(gr, 0x418e4c, 0xffffffff, 0x70000000);
}
struct nvkm_oclass *
#include "ctxgf100.h"
static void
-gm20b_grctx_generate_r406028(struct gf100_gr_priv *priv)
+gm20b_grctx_generate_r406028(struct gf100_gr *gr)
{
u32 tpc_per_gpc = 0;
int i;
- for (i = 0; i < priv->gpc_nr; i++)
- tpc_per_gpc |= priv->tpc_nr[i] << (4 * i);
+ for (i = 0; i < gr->gpc_nr; i++)
+ tpc_per_gpc |= gr->tpc_nr[i] << (4 * i);
- nv_wr32(priv, 0x406028, tpc_per_gpc);
- nv_wr32(priv, 0x405870, tpc_per_gpc);
+ nv_wr32(gr, 0x406028, tpc_per_gpc);
+ nv_wr32(gr, 0x405870, tpc_per_gpc);
}
static void
-gm20b_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
+gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
- struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
int idle_timeout_save;
int i, tmp;
- gf100_gr_mmio(priv, priv->fuc_sw_ctx);
+ gf100_gr_mmio(gr, gr->fuc_sw_ctx);
- gf100_gr_wait_idle(priv);
+ gf100_gr_wait_idle(gr);
- idle_timeout_save = nv_rd32(priv, 0x404154);
- nv_wr32(priv, 0x404154, 0x00000000);
+ idle_timeout_save = nv_rd32(gr, 0x404154);
+ nv_wr32(gr, 0x404154, 0x00000000);
oclass->attrib(info);
- oclass->unkn(priv);
+ oclass->unkn(gr);
- gm204_grctx_generate_tpcid(priv);
- gm20b_grctx_generate_r406028(priv);
- gk104_grctx_generate_r418bb8(priv);
+ gm204_grctx_generate_tpcid(gr);
+ gm20b_grctx_generate_r406028(gr);
+ gk104_grctx_generate_r418bb8(gr);
for (i = 0; i < 8; i++)
- nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
+ nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000);
- nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
+ nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
- gk104_grctx_generate_rop_active_fbps(priv);
- nv_wr32(priv, 0x408908, nv_rd32(priv, 0x410108) | 0x80000000);
+ gk104_grctx_generate_rop_active_fbps(gr);
+ nv_wr32(gr, 0x408908, nv_rd32(gr, 0x410108) | 0x80000000);
- for (tmp = 0, i = 0; i < priv->gpc_nr; i++)
- tmp |= ((1 << priv->tpc_nr[i]) - 1) << (i * 4);
- nv_wr32(priv, 0x4041c4, tmp);
+ for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
+ tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4);
+ nv_wr32(gr, 0x4041c4, tmp);
- gm204_grctx_generate_405b60(priv);
+ gm204_grctx_generate_405b60(gr);
- gf100_gr_wait_idle(priv);
+ gf100_gr_wait_idle(gr);
- nv_wr32(priv, 0x404154, idle_timeout_save);
- gf100_gr_wait_idle(priv);
+ nv_wr32(gr, 0x404154, idle_timeout_save);
+ gf100_gr_wait_idle(gr);
- gf100_gr_mthd(priv, priv->fuc_method);
- gf100_gr_wait_idle(priv);
+ gf100_gr_mthd(gr, gr->fuc_method);
+ gf100_gr_wait_idle(gr);
- gf100_gr_icmd(priv, priv->fuc_bundle);
+ gf100_gr_icmd(gr, gr->fuc_bundle);
oclass->pagepool(info);
oclass->bundle(info);
}
.attrib_nr = 0x400,
.alpha_nr_max = 0xc00,
.alpha_nr = 0x800,
-}.base;
\ No newline at end of file
+}.base;
******************************************************************************/
static void
-gf100_gr_zbc_clear_color(struct gf100_gr_priv *priv, int zbc)
+gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc)
{
- if (priv->zbc_color[zbc].format) {
- nv_wr32(priv, 0x405804, priv->zbc_color[zbc].ds[0]);
- nv_wr32(priv, 0x405808, priv->zbc_color[zbc].ds[1]);
- nv_wr32(priv, 0x40580c, priv->zbc_color[zbc].ds[2]);
- nv_wr32(priv, 0x405810, priv->zbc_color[zbc].ds[3]);
- }
- nv_wr32(priv, 0x405814, priv->zbc_color[zbc].format);
- nv_wr32(priv, 0x405820, zbc);
- nv_wr32(priv, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */
+ if (gr->zbc_color[zbc].format) {
+ nv_wr32(gr, 0x405804, gr->zbc_color[zbc].ds[0]);
+ nv_wr32(gr, 0x405808, gr->zbc_color[zbc].ds[1]);
+ nv_wr32(gr, 0x40580c, gr->zbc_color[zbc].ds[2]);
+ nv_wr32(gr, 0x405810, gr->zbc_color[zbc].ds[3]);
+ }
+ nv_wr32(gr, 0x405814, gr->zbc_color[zbc].format);
+ nv_wr32(gr, 0x405820, zbc);
+ nv_wr32(gr, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */
}
static int
-gf100_gr_zbc_color_get(struct gf100_gr_priv *priv, int format,
+gf100_gr_zbc_color_get(struct gf100_gr *gr, int format,
const u32 ds[4], const u32 l2[4])
{
- struct nvkm_ltc *ltc = nvkm_ltc(priv);
+ struct nvkm_ltc *ltc = nvkm_ltc(gr);
int zbc = -ENOSPC, i;
for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
- if (priv->zbc_color[i].format) {
- if (priv->zbc_color[i].format != format)
+ if (gr->zbc_color[i].format) {
+ if (gr->zbc_color[i].format != format)
continue;
- if (memcmp(priv->zbc_color[i].ds, ds, sizeof(
- priv->zbc_color[i].ds)))
+ if (memcmp(gr->zbc_color[i].ds, ds, sizeof(
+ gr->zbc_color[i].ds)))
continue;
- if (memcmp(priv->zbc_color[i].l2, l2, sizeof(
- priv->zbc_color[i].l2))) {
+ if (memcmp(gr->zbc_color[i].l2, l2, sizeof(
+ gr->zbc_color[i].l2))) {
WARN_ON(1);
return -EINVAL;
}
if (zbc < 0)
return zbc;
- memcpy(priv->zbc_color[zbc].ds, ds, sizeof(priv->zbc_color[zbc].ds));
- memcpy(priv->zbc_color[zbc].l2, l2, sizeof(priv->zbc_color[zbc].l2));
- priv->zbc_color[zbc].format = format;
+ memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds));
+ memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2));
+ gr->zbc_color[zbc].format = format;
ltc->zbc_color_get(ltc, zbc, l2);
- gf100_gr_zbc_clear_color(priv, zbc);
+ gf100_gr_zbc_clear_color(gr, zbc);
return zbc;
}
static void
-gf100_gr_zbc_clear_depth(struct gf100_gr_priv *priv, int zbc)
+gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc)
{
- if (priv->zbc_depth[zbc].format)
- nv_wr32(priv, 0x405818, priv->zbc_depth[zbc].ds);
- nv_wr32(priv, 0x40581c, priv->zbc_depth[zbc].format);
- nv_wr32(priv, 0x405820, zbc);
- nv_wr32(priv, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */
+ if (gr->zbc_depth[zbc].format)
+ nv_wr32(gr, 0x405818, gr->zbc_depth[zbc].ds);
+ nv_wr32(gr, 0x40581c, gr->zbc_depth[zbc].format);
+ nv_wr32(gr, 0x405820, zbc);
+ nv_wr32(gr, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */
}
static int
-gf100_gr_zbc_depth_get(struct gf100_gr_priv *priv, int format,
+gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format,
const u32 ds, const u32 l2)
{
- struct nvkm_ltc *ltc = nvkm_ltc(priv);
+ struct nvkm_ltc *ltc = nvkm_ltc(gr);
int zbc = -ENOSPC, i;
for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
- if (priv->zbc_depth[i].format) {
- if (priv->zbc_depth[i].format != format)
+ if (gr->zbc_depth[i].format) {
+ if (gr->zbc_depth[i].format != format)
continue;
- if (priv->zbc_depth[i].ds != ds)
+ if (gr->zbc_depth[i].ds != ds)
continue;
- if (priv->zbc_depth[i].l2 != l2) {
+ if (gr->zbc_depth[i].l2 != l2) {
WARN_ON(1);
return -EINVAL;
}
if (zbc < 0)
return zbc;
- priv->zbc_depth[zbc].format = format;
- priv->zbc_depth[zbc].ds = ds;
- priv->zbc_depth[zbc].l2 = l2;
+ gr->zbc_depth[zbc].format = format;
+ gr->zbc_depth[zbc].ds = ds;
+ gr->zbc_depth[zbc].l2 = l2;
ltc->zbc_depth_get(ltc, zbc, l2);
- gf100_gr_zbc_clear_depth(priv, zbc);
+ gf100_gr_zbc_clear_depth(gr, zbc);
return zbc;
}
static int
gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size)
{
- struct gf100_gr_priv *priv = (void *)object->engine;
+ struct gf100_gr *gr = (void *)object->engine;
union {
struct fermi_a_zbc_color_v0 v0;
} *args = data;
case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8:
case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10:
case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11:
- ret = gf100_gr_zbc_color_get(priv, args->v0.format,
+ ret = gf100_gr_zbc_color_get(gr, args->v0.format,
args->v0.ds,
args->v0.l2);
if (ret >= 0) {
static int
gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size)
{
- struct gf100_gr_priv *priv = (void *)object->engine;
+ struct gf100_gr *gr = (void *)object->engine;
union {
struct fermi_a_zbc_depth_v0 v0;
} *args = data;
if (nvif_unpack(args->v0, 0, 0, false)) {
switch (args->v0.format) {
case FERMI_A_ZBC_DEPTH_V0_FMT_FP32:
- ret = gf100_gr_zbc_depth_get(priv, args->v0.format,
+ ret = gf100_gr_zbc_depth_get(gr, args->v0.format,
args->v0.ds,
args->v0.l2);
return (ret >= 0) ? 0 : -ENOSPC;
gf100_gr_set_shader_exceptions(struct nvkm_object *object, u32 mthd,
void *pdata, u32 size)
{
- struct gf100_gr_priv *priv = (void *)object->engine;
+ struct gf100_gr *gr = (void *)object->engine;
if (size >= sizeof(u32)) {
u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000;
- nv_wr32(priv, 0x419e44, data);
- nv_wr32(priv, 0x419e4c, data);
+ nv_wr32(gr, 0x419e44, data);
+ nv_wr32(gr, 0x419e4c, data);
return 0;
}
return -EINVAL;
struct nvkm_object **pobject)
{
struct nvkm_vm *vm = nvkm_client(parent)->vm;
- struct gf100_gr_priv *priv = (void *)engine;
- struct gf100_gr_data *data = priv->mmio_data;
- struct gf100_gr_mmio *mmio = priv->mmio_list;
+ struct gf100_gr *gr = (void *)engine;
+ struct gf100_gr_data *data = gr->mmio_data;
+ struct gf100_gr_mmio *mmio = gr->mmio_list;
struct gf100_gr_chan *chan;
int ret, i;
/* allocate memory for context, and fill with default values */
ret = nvkm_gr_context_create(parent, engine, oclass, NULL,
- priv->size, 0x100,
+ gr->size, 0x100,
NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
/* allocate buffers referenced by mmio list */
- for (i = 0; data->size && i < ARRAY_SIZE(priv->mmio_data); i++) {
+ for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) {
ret = nvkm_gpuobj_new(nv_object(chan), NULL, data->size,
data->align, 0, &chan->data[i].mem);
if (ret)
}
/* finally, fill in the mmio list and point the context at it */
- for (i = 0; mmio->addr && i < ARRAY_SIZE(priv->mmio_list); i++) {
+ for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) {
u32 addr = mmio->addr;
u32 data = mmio->data;
mmio++;
}
- for (i = 0; i < priv->size; i += 4)
- nv_wo32(chan, i, priv->data[i / 4]);
+ for (i = 0; i < gr->size; i += 4)
+ nv_wo32(chan, i, gr->data[i / 4]);
- if (!priv->firmware) {
+ if (!gr->firmware) {
nv_wo32(chan, 0x00, chan->mmio_nr / 2);
nv_wo32(chan, 0x04, chan->mmio_vma.offset >> 8);
} else {
******************************************************************************/
void
-gf100_gr_zbc_init(struct gf100_gr_priv *priv)
+gf100_gr_zbc_init(struct gf100_gr *gr)
{
const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000 };
0x00000000, 0x00000000, 0x00000000, 0x00000000 };
const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 };
- struct nvkm_ltc *ltc = nvkm_ltc(priv);
+ struct nvkm_ltc *ltc = nvkm_ltc(gr);
int index;
- if (!priv->zbc_color[0].format) {
- gf100_gr_zbc_color_get(priv, 1, & zero[0], &zero[4]);
- gf100_gr_zbc_color_get(priv, 2, & one[0], &one[4]);
- gf100_gr_zbc_color_get(priv, 4, &f32_0[0], &f32_0[4]);
- gf100_gr_zbc_color_get(priv, 4, &f32_1[0], &f32_1[4]);
- gf100_gr_zbc_depth_get(priv, 1, 0x00000000, 0x00000000);
- gf100_gr_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000);
+ if (!gr->zbc_color[0].format) {
+ gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]);
+ gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]);
+ gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]);
+ gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]);
+ gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000);
+ gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000);
}
for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
- gf100_gr_zbc_clear_color(priv, index);
+ gf100_gr_zbc_clear_color(gr, index);
for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
- gf100_gr_zbc_clear_depth(priv, index);
+ gf100_gr_zbc_clear_depth(gr, index);
}
/**
* progress.
*/
int
-gf100_gr_wait_idle(struct gf100_gr_priv *priv)
+gf100_gr_wait_idle(struct gf100_gr *gr)
{
unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000);
bool gr_enabled, ctxsw_active, gr_busy;
* required to make sure FIFO_ENGINE_STATUS (0x2640) is
* up-to-date
*/
- nv_rd32(priv, 0x400700);
+ nv_rd32(gr, 0x400700);
- gr_enabled = nv_rd32(priv, 0x200) & 0x1000;
- ctxsw_active = nv_rd32(priv, 0x2640) & 0x8000;
- gr_busy = nv_rd32(priv, 0x40060c) & 0x1;
+ gr_enabled = nv_rd32(gr, 0x200) & 0x1000;
+ ctxsw_active = nv_rd32(gr, 0x2640) & 0x8000;
+ gr_busy = nv_rd32(gr, 0x40060c) & 0x1;
if (!gr_enabled || (!gr_busy && !ctxsw_active))
return 0;
} while (time_before(jiffies, end_jiffies));
- nv_error(priv, "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n",
+ nv_error(gr, "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n",
gr_enabled, ctxsw_active, gr_busy);
return -EAGAIN;
}
void
-gf100_gr_mmio(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
+gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p)
{
const struct gf100_gr_pack *pack;
const struct gf100_gr_init *init;
u32 next = init->addr + init->count * init->pitch;
u32 addr = init->addr;
while (addr < next) {
- nv_wr32(priv, addr, init->data);
+ nv_wr32(gr, addr, init->data);
addr += init->pitch;
}
}
}
void
-gf100_gr_icmd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
+gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
{
const struct gf100_gr_pack *pack;
const struct gf100_gr_init *init;
u32 data = 0;
- nv_wr32(priv, 0x400208, 0x80000000);
+ nv_wr32(gr, 0x400208, 0x80000000);
pack_for_each_init(init, pack, p) {
u32 next = init->addr + init->count * init->pitch;
u32 addr = init->addr;
if ((pack == p && init == p->init) || data != init->data) {
- nv_wr32(priv, 0x400204, init->data);
+ nv_wr32(gr, 0x400204, init->data);
data = init->data;
}
while (addr < next) {
- nv_wr32(priv, 0x400200, addr);
+ nv_wr32(gr, 0x400200, addr);
/**
* Wait for GR to go idle after submitting a
* GO_IDLE bundle
*/
if ((addr & 0xffff) == 0xe100)
- gf100_gr_wait_idle(priv);
- nv_wait(priv, 0x400700, 0x00000004, 0x00000000);
+ gf100_gr_wait_idle(gr);
+ nv_wait(gr, 0x400700, 0x00000004, 0x00000000);
addr += init->pitch;
}
}
- nv_wr32(priv, 0x400208, 0x00000000);
+ nv_wr32(gr, 0x400208, 0x00000000);
}
void
-gf100_gr_mthd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
+gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
{
const struct gf100_gr_pack *pack;
const struct gf100_gr_init *init;
u32 addr = init->addr;
if ((pack == p && init == p->init) || data != init->data) {
- nv_wr32(priv, 0x40448c, init->data);
+ nv_wr32(gr, 0x40448c, init->data);
data = init->data;
}
while (addr < next) {
- nv_wr32(priv, 0x404488, ctrl | (addr << 14));
+ nv_wr32(gr, 0x404488, ctrl | (addr << 14));
addr += init->pitch;
}
}
}
u64
-gf100_gr_units(struct nvkm_gr *gr)
+gf100_gr_units(struct nvkm_gr *obj)
{
- struct gf100_gr_priv *priv = (void *)gr;
+ struct gf100_gr *gr = container_of(obj, typeof(*gr), base);
u64 cfg;
- cfg = (u32)priv->gpc_nr;
- cfg |= (u32)priv->tpc_total << 8;
- cfg |= (u64)priv->rop_nr << 32;
+ cfg = (u32)gr->gpc_nr;
+ cfg |= (u32)gr->tpc_total << 8;
+ cfg |= (u64)gr->rop_nr << 32;
return cfg;
}
};
static void
-gf100_gr_trap_gpc_rop(struct gf100_gr_priv *priv, int gpc)
+gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc)
{
u32 trap[4];
int i;
- trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420));
- trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434));
- trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438));
- trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c));
+ trap[0] = nv_rd32(gr, GPC_UNIT(gpc, 0x0420));
+ trap[1] = nv_rd32(gr, GPC_UNIT(gpc, 0x0434));
+ trap[2] = nv_rd32(gr, GPC_UNIT(gpc, 0x0438));
+ trap[3] = nv_rd32(gr, GPC_UNIT(gpc, 0x043c));
- nv_error(priv, "GPC%d/PROP trap:", gpc);
+ nv_error(gr, "GPC%d/PROP trap:", gpc);
for (i = 0; i <= 29; ++i) {
if (!(trap[0] & (1 << i)))
continue;
}
pr_cont("\n");
- nv_error(priv, "x = %u, y = %u, format = %x, storage type = %x\n",
+ nv_error(gr, "x = %u, y = %u, format = %x, storage type = %x\n",
trap[1] & 0xffff, trap[1] >> 16, (trap[2] >> 8) & 0x3f,
trap[3] & 0xff);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000);
}
static const struct nvkm_enum gf100_mp_warp_error[] = {
};
static void
-gf100_gr_trap_mp(struct gf100_gr_priv *priv, int gpc, int tpc)
+gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
{
- u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648));
- u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650));
+ u32 werr = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x648));
+ u32 gerr = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x650));
- nv_error(priv, "GPC%i/TPC%i/MP trap:", gpc, tpc);
+ nv_error(gr, "GPC%i/TPC%i/MP trap:", gpc, tpc);
nvkm_bitfield_print(gf100_mp_global_error, gerr);
if (werr) {
pr_cont(" ");
}
pr_cont("\n");
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x648), 0x00000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x650), gerr);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x648), 0x00000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x650), gerr);
}
static void
-gf100_gr_trap_tpc(struct gf100_gr_priv *priv, int gpc, int tpc)
+gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc)
{
- u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0508));
+ u32 stat = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x0508));
if (stat & 0x00000001) {
- u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0224));
- nv_error(priv, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);
+ u32 trap = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x0224));
+ nv_error(gr, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);
stat &= ~0x00000001;
}
if (stat & 0x00000002) {
- gf100_gr_trap_mp(priv, gpc, tpc);
+ gf100_gr_trap_mp(gr, gpc, tpc);
stat &= ~0x00000002;
}
if (stat & 0x00000004) {
- u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0084));
- nv_error(priv, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);
+ u32 trap = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x0084));
+ nv_error(gr, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);
stat &= ~0x00000004;
}
if (stat & 0x00000008) {
- u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x048c));
- nv_error(priv, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);
+ u32 trap = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x048c));
+ nv_error(gr, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);
stat &= ~0x00000008;
}
if (stat) {
- nv_error(priv, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat);
+ nv_error(gr, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat);
}
}
static void
-gf100_gr_trap_gpc(struct gf100_gr_priv *priv, int gpc)
+gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc)
{
- u32 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90));
+ u32 stat = nv_rd32(gr, GPC_UNIT(gpc, 0x2c90));
int tpc;
if (stat & 0x00000001) {
- gf100_gr_trap_gpc_rop(priv, gpc);
+ gf100_gr_trap_gpc_rop(gr, gpc);
stat &= ~0x00000001;
}
if (stat & 0x00000002) {
- u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900));
- nv_error(priv, "GPC%d/ZCULL: 0x%08x\n", gpc, trap);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
+ u32 trap = nv_rd32(gr, GPC_UNIT(gpc, 0x0900));
+ nv_error(gr, "GPC%d/ZCULL: 0x%08x\n", gpc, trap);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000);
stat &= ~0x00000002;
}
if (stat & 0x00000004) {
- u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028));
- nv_error(priv, "GPC%d/CCACHE: 0x%08x\n", gpc, trap);
- nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
+ u32 trap = nv_rd32(gr, GPC_UNIT(gpc, 0x1028));
+ nv_error(gr, "GPC%d/CCACHE: 0x%08x\n", gpc, trap);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000);
stat &= ~0x00000004;
}
if (stat & 0x00000008) {
- u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824));
- nv_error(priv, "GPC%d/ESETUP: 0x%08x\n", gpc, trap);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
+ u32 trap = nv_rd32(gr, GPC_UNIT(gpc, 0x0824));
+ nv_error(gr, "GPC%d/ESETUP: 0x%08x\n", gpc, trap);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000);
stat &= ~0x00000009;
}
- for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
+ for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
u32 mask = 0x00010000 << tpc;
if (stat & mask) {
- gf100_gr_trap_tpc(priv, gpc, tpc);
- nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), mask);
+ gf100_gr_trap_tpc(gr, gpc, tpc);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), mask);
stat &= ~mask;
}
}
if (stat) {
- nv_error(priv, "GPC%d/0x%08x: unknown\n", gpc, stat);
+ nv_error(gr, "GPC%d/0x%08x: unknown\n", gpc, stat);
}
}
static void
-gf100_gr_trap_intr(struct gf100_gr_priv *priv)
+gf100_gr_trap_intr(struct gf100_gr *gr)
{
- u32 trap = nv_rd32(priv, 0x400108);
+ u32 trap = nv_rd32(gr, 0x400108);
int rop, gpc, i;
if (trap & 0x00000001) {
- u32 stat = nv_rd32(priv, 0x404000);
- nv_error(priv, "DISPATCH 0x%08x\n", stat);
- nv_wr32(priv, 0x404000, 0xc0000000);
- nv_wr32(priv, 0x400108, 0x00000001);
+ u32 stat = nv_rd32(gr, 0x404000);
+ nv_error(gr, "DISPATCH 0x%08x\n", stat);
+ nv_wr32(gr, 0x404000, 0xc0000000);
+ nv_wr32(gr, 0x400108, 0x00000001);
trap &= ~0x00000001;
}
if (trap & 0x00000002) {
- u32 stat = nv_rd32(priv, 0x404600);
- nv_error(priv, "M2MF 0x%08x\n", stat);
- nv_wr32(priv, 0x404600, 0xc0000000);
- nv_wr32(priv, 0x400108, 0x00000002);
+ u32 stat = nv_rd32(gr, 0x404600);
+ nv_error(gr, "M2MF 0x%08x\n", stat);
+ nv_wr32(gr, 0x404600, 0xc0000000);
+ nv_wr32(gr, 0x400108, 0x00000002);
trap &= ~0x00000002;
}
if (trap & 0x00000008) {
- u32 stat = nv_rd32(priv, 0x408030);
- nv_error(priv, "CCACHE 0x%08x\n", stat);
- nv_wr32(priv, 0x408030, 0xc0000000);
- nv_wr32(priv, 0x400108, 0x00000008);
+ u32 stat = nv_rd32(gr, 0x408030);
+ nv_error(gr, "CCACHE 0x%08x\n", stat);
+ nv_wr32(gr, 0x408030, 0xc0000000);
+ nv_wr32(gr, 0x400108, 0x00000008);
trap &= ~0x00000008;
}
if (trap & 0x00000010) {
- u32 stat = nv_rd32(priv, 0x405840);
- nv_error(priv, "SHADER 0x%08x\n", stat);
- nv_wr32(priv, 0x405840, 0xc0000000);
- nv_wr32(priv, 0x400108, 0x00000010);
+ u32 stat = nv_rd32(gr, 0x405840);
+ nv_error(gr, "SHADER 0x%08x\n", stat);
+ nv_wr32(gr, 0x405840, 0xc0000000);
+ nv_wr32(gr, 0x400108, 0x00000010);
trap &= ~0x00000010;
}
if (trap & 0x00000040) {
- u32 stat = nv_rd32(priv, 0x40601c);
- nv_error(priv, "UNK6 0x%08x\n", stat);
- nv_wr32(priv, 0x40601c, 0xc0000000);
- nv_wr32(priv, 0x400108, 0x00000040);
+ u32 stat = nv_rd32(gr, 0x40601c);
+ nv_error(gr, "UNK6 0x%08x\n", stat);
+ nv_wr32(gr, 0x40601c, 0xc0000000);
+ nv_wr32(gr, 0x400108, 0x00000040);
trap &= ~0x00000040;
}
if (trap & 0x00000080) {
- u32 stat = nv_rd32(priv, 0x404490);
- nv_error(priv, "MACRO 0x%08x\n", stat);
- nv_wr32(priv, 0x404490, 0xc0000000);
- nv_wr32(priv, 0x400108, 0x00000080);
+ u32 stat = nv_rd32(gr, 0x404490);
+ nv_error(gr, "MACRO 0x%08x\n", stat);
+ nv_wr32(gr, 0x404490, 0xc0000000);
+ nv_wr32(gr, 0x400108, 0x00000080);
trap &= ~0x00000080;
}
if (trap & 0x00000100) {
- u32 stat = nv_rd32(priv, 0x407020);
+ u32 stat = nv_rd32(gr, 0x407020);
- nv_error(priv, "SKED:");
+ nv_error(gr, "SKED:");
for (i = 0; i <= 29; ++i) {
if (!(stat & (1 << i)))
continue;
pr_cont("\n");
if (stat & 0x3fffffff)
- nv_wr32(priv, 0x407020, 0x40000000);
- nv_wr32(priv, 0x400108, 0x00000100);
+ nv_wr32(gr, 0x407020, 0x40000000);
+ nv_wr32(gr, 0x400108, 0x00000100);
trap &= ~0x00000100;
}
if (trap & 0x01000000) {
- u32 stat = nv_rd32(priv, 0x400118);
- for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) {
+ u32 stat = nv_rd32(gr, 0x400118);
+ for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) {
u32 mask = 0x00000001 << gpc;
if (stat & mask) {
- gf100_gr_trap_gpc(priv, gpc);
- nv_wr32(priv, 0x400118, mask);
+ gf100_gr_trap_gpc(gr, gpc);
+ nv_wr32(gr, 0x400118, mask);
stat &= ~mask;
}
}
- nv_wr32(priv, 0x400108, 0x01000000);
+ nv_wr32(gr, 0x400108, 0x01000000);
trap &= ~0x01000000;
}
if (trap & 0x02000000) {
- for (rop = 0; rop < priv->rop_nr; rop++) {
- u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070));
- u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144));
- nv_error(priv, "ROP%d 0x%08x 0x%08x\n",
+ for (rop = 0; rop < gr->rop_nr; rop++) {
+ u32 statz = nv_rd32(gr, ROP_UNIT(rop, 0x070));
+ u32 statc = nv_rd32(gr, ROP_UNIT(rop, 0x144));
+ nv_error(gr, "ROP%d 0x%08x 0x%08x\n",
rop, statz, statc);
- nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
- nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
+ nv_wr32(gr, ROP_UNIT(rop, 0x070), 0xc0000000);
+ nv_wr32(gr, ROP_UNIT(rop, 0x144), 0xc0000000);
}
- nv_wr32(priv, 0x400108, 0x02000000);
+ nv_wr32(gr, 0x400108, 0x02000000);
trap &= ~0x02000000;
}
if (trap) {
- nv_error(priv, "TRAP UNHANDLED 0x%08x\n", trap);
- nv_wr32(priv, 0x400108, trap);
+ nv_error(gr, "TRAP UNHANDLED 0x%08x\n", trap);
+ nv_wr32(gr, 0x400108, trap);
}
}
static void
-gf100_gr_ctxctl_debug_unit(struct gf100_gr_priv *priv, u32 base)
+gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base)
{
- nv_error(priv, "%06x - done 0x%08x\n", base,
- nv_rd32(priv, base + 0x400));
- nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
- nv_rd32(priv, base + 0x800), nv_rd32(priv, base + 0x804),
- nv_rd32(priv, base + 0x808), nv_rd32(priv, base + 0x80c));
- nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
- nv_rd32(priv, base + 0x810), nv_rd32(priv, base + 0x814),
- nv_rd32(priv, base + 0x818), nv_rd32(priv, base + 0x81c));
+ nv_error(gr, "%06x - done 0x%08x\n", base,
+ nv_rd32(gr, base + 0x400));
+ nv_error(gr, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
+ nv_rd32(gr, base + 0x800), nv_rd32(gr, base + 0x804),
+ nv_rd32(gr, base + 0x808), nv_rd32(gr, base + 0x80c));
+ nv_error(gr, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
+ nv_rd32(gr, base + 0x810), nv_rd32(gr, base + 0x814),
+ nv_rd32(gr, base + 0x818), nv_rd32(gr, base + 0x81c));
}
void
-gf100_gr_ctxctl_debug(struct gf100_gr_priv *priv)
+gf100_gr_ctxctl_debug(struct gf100_gr *gr)
{
- u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff;
+ u32 gpcnr = nv_rd32(gr, 0x409604) & 0xffff;
u32 gpc;
- gf100_gr_ctxctl_debug_unit(priv, 0x409000);
+ gf100_gr_ctxctl_debug_unit(gr, 0x409000);
for (gpc = 0; gpc < gpcnr; gpc++)
- gf100_gr_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000));
+ gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000));
}
static void
-gf100_gr_ctxctl_isr(struct gf100_gr_priv *priv)
+gf100_gr_ctxctl_isr(struct gf100_gr *gr)
{
- u32 stat = nv_rd32(priv, 0x409c18);
+ u32 stat = nv_rd32(gr, 0x409c18);
if (stat & 0x00000001) {
- u32 code = nv_rd32(priv, 0x409814);
+ u32 code = nv_rd32(gr, 0x409814);
if (code == E_BAD_FWMTHD) {
- u32 class = nv_rd32(priv, 0x409808);
- u32 addr = nv_rd32(priv, 0x40980c);
+ u32 class = nv_rd32(gr, 0x409808);
+ u32 addr = nv_rd32(gr, 0x40980c);
u32 subc = (addr & 0x00070000) >> 16;
u32 mthd = (addr & 0x00003ffc);
- u32 data = nv_rd32(priv, 0x409810);
+ u32 data = nv_rd32(gr, 0x409810);
- nv_error(priv, "FECS MTHD subc %d class 0x%04x "
+ nv_error(gr, "FECS MTHD subc %d class 0x%04x "
"mthd 0x%04x data 0x%08x\n",
subc, class, mthd, data);
- nv_wr32(priv, 0x409c20, 0x00000001);
+ nv_wr32(gr, 0x409c20, 0x00000001);
stat &= ~0x00000001;
} else {
- nv_error(priv, "FECS ucode error %d\n", code);
+ nv_error(gr, "FECS ucode error %d\n", code);
}
}
if (stat & 0x00080000) {
- nv_error(priv, "FECS watchdog timeout\n");
- gf100_gr_ctxctl_debug(priv);
- nv_wr32(priv, 0x409c20, 0x00080000);
+ nv_error(gr, "FECS watchdog timeout\n");
+ gf100_gr_ctxctl_debug(gr);
+ nv_wr32(gr, 0x409c20, 0x00080000);
stat &= ~0x00080000;
}
if (stat) {
- nv_error(priv, "FECS 0x%08x\n", stat);
- gf100_gr_ctxctl_debug(priv);
- nv_wr32(priv, 0x409c20, stat);
+ nv_error(gr, "FECS 0x%08x\n", stat);
+ gf100_gr_ctxctl_debug(gr);
+ nv_wr32(gr, 0x409c20, stat);
}
}
struct nvkm_engine *engine = nv_engine(subdev);
struct nvkm_object *engctx;
struct nvkm_handle *handle;
- struct gf100_gr_priv *priv = (void *)subdev;
- u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff;
- u32 stat = nv_rd32(priv, 0x400100);
- u32 addr = nv_rd32(priv, 0x400704);
+ struct gf100_gr *gr = (void *)subdev;
+ u64 inst = nv_rd32(gr, 0x409b00) & 0x0fffffff;
+ u32 stat = nv_rd32(gr, 0x400100);
+ u32 addr = nv_rd32(gr, 0x400704);
u32 mthd = (addr & 0x00003ffc);
u32 subc = (addr & 0x00070000) >> 16;
- u32 data = nv_rd32(priv, 0x400708);
- u32 code = nv_rd32(priv, 0x400110);
+ u32 data = nv_rd32(gr, 0x400708);
+ u32 code = nv_rd32(gr, 0x400110);
u32 class;
int chid;
- if (nv_device(priv)->card_type < NV_E0 || subc < 4)
- class = nv_rd32(priv, 0x404200 + (subc * 4));
+ if (nv_device(gr)->card_type < NV_E0 || subc < 4)
+ class = nv_rd32(gr, 0x404200 + (subc * 4));
else
class = 0x0000;
* notifier interrupt, only needed for cyclestats
* can be safely ignored
*/
- nv_wr32(priv, 0x400100, 0x00000001);
+ nv_wr32(gr, 0x400100, 0x00000001);
stat &= ~0x00000001;
}
if (stat & 0x00000010) {
handle = nvkm_handle_get_class(engctx, class);
if (!handle || nv_call(handle->object, mthd, data)) {
- nv_error(priv,
+ nv_error(gr,
"ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, inst << 12, nvkm_client_name(engctx),
subc, class, mthd, data);
}
nvkm_handle_put(handle);
- nv_wr32(priv, 0x400100, 0x00000010);
+ nv_wr32(gr, 0x400100, 0x00000010);
stat &= ~0x00000010;
}
if (stat & 0x00000020) {
- nv_error(priv,
+ nv_error(gr,
"ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, inst << 12, nvkm_client_name(engctx), subc,
class, mthd, data);
- nv_wr32(priv, 0x400100, 0x00000020);
+ nv_wr32(gr, 0x400100, 0x00000020);
stat &= ~0x00000020;
}
if (stat & 0x00100000) {
- nv_error(priv, "DATA_ERROR [");
+ nv_error(gr, "DATA_ERROR [");
nvkm_enum_print(nv50_data_error_names, code);
pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, inst << 12, nvkm_client_name(engctx), subc,
class, mthd, data);
- nv_wr32(priv, 0x400100, 0x00100000);
+ nv_wr32(gr, 0x400100, 0x00100000);
stat &= ~0x00100000;
}
if (stat & 0x00200000) {
- nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12,
+ nv_error(gr, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12,
nvkm_client_name(engctx));
- gf100_gr_trap_intr(priv);
- nv_wr32(priv, 0x400100, 0x00200000);
+ gf100_gr_trap_intr(gr);
+ nv_wr32(gr, 0x400100, 0x00200000);
stat &= ~0x00200000;
}
if (stat & 0x00080000) {
- gf100_gr_ctxctl_isr(priv);
- nv_wr32(priv, 0x400100, 0x00080000);
+ gf100_gr_ctxctl_isr(gr);
+ nv_wr32(gr, 0x400100, 0x00080000);
stat &= ~0x00080000;
}
if (stat) {
- nv_error(priv, "unknown stat 0x%08x\n", stat);
- nv_wr32(priv, 0x400100, stat);
+ nv_error(gr, "unknown stat 0x%08x\n", stat);
+ nv_wr32(gr, 0x400100, stat);
}
- nv_wr32(priv, 0x400500, 0x00010001);
+ nv_wr32(gr, 0x400500, 0x00010001);
nvkm_engctx_put(engctx);
}
void
-gf100_gr_init_fw(struct gf100_gr_priv *priv, u32 fuc_base,
+gf100_gr_init_fw(struct gf100_gr *gr, u32 fuc_base,
struct gf100_gr_fuc *code, struct gf100_gr_fuc *data)
{
int i;
- nv_wr32(priv, fuc_base + 0x01c0, 0x01000000);
+ nv_wr32(gr, fuc_base + 0x01c0, 0x01000000);
for (i = 0; i < data->size / 4; i++)
- nv_wr32(priv, fuc_base + 0x01c4, data->data[i]);
+ nv_wr32(gr, fuc_base + 0x01c4, data->data[i]);
- nv_wr32(priv, fuc_base + 0x0180, 0x01000000);
+ nv_wr32(gr, fuc_base + 0x0180, 0x01000000);
for (i = 0; i < code->size / 4; i++) {
if ((i & 0x3f) == 0)
- nv_wr32(priv, fuc_base + 0x0188, i >> 6);
- nv_wr32(priv, fuc_base + 0x0184, code->data[i]);
+ nv_wr32(gr, fuc_base + 0x0188, i >> 6);
+ nv_wr32(gr, fuc_base + 0x0184, code->data[i]);
}
/* code must be padded to 0x40 words */
for (; i & 0x3f; i++)
- nv_wr32(priv, fuc_base + 0x0184, 0);
+ nv_wr32(gr, fuc_base + 0x0184, 0);
}
static void
-gf100_gr_init_csdata(struct gf100_gr_priv *priv,
+gf100_gr_init_csdata(struct gf100_gr *gr,
const struct gf100_gr_pack *pack,
u32 falcon, u32 starstar, u32 base)
{
u32 addr = ~0, prev = ~0, xfer = 0;
u32 star, temp;
- nv_wr32(priv, falcon + 0x01c0, 0x02000000 + starstar);
- star = nv_rd32(priv, falcon + 0x01c4);
- temp = nv_rd32(priv, falcon + 0x01c4);
+ nv_wr32(gr, falcon + 0x01c0, 0x02000000 + starstar);
+ star = nv_rd32(gr, falcon + 0x01c4);
+ temp = nv_rd32(gr, falcon + 0x01c4);
if (temp > star)
star = temp;
- nv_wr32(priv, falcon + 0x01c0, 0x01000000 + star);
+ nv_wr32(gr, falcon + 0x01c0, 0x01000000 + star);
pack_for_each_init(init, iter, pack) {
u32 head = init->addr - base;
if (head != prev + 4 || xfer >= 32) {
if (xfer) {
u32 data = ((--xfer << 26) | addr);
- nv_wr32(priv, falcon + 0x01c4, data);
+ nv_wr32(gr, falcon + 0x01c4, data);
star += 4;
}
addr = head;
}
}
- nv_wr32(priv, falcon + 0x01c4, (--xfer << 26) | addr);
- nv_wr32(priv, falcon + 0x01c0, 0x01000004 + starstar);
- nv_wr32(priv, falcon + 0x01c4, star + 4);
+ nv_wr32(gr, falcon + 0x01c4, (--xfer << 26) | addr);
+ nv_wr32(gr, falcon + 0x01c0, 0x01000004 + starstar);
+ nv_wr32(gr, falcon + 0x01c4, star + 4);
}
int
-gf100_gr_init_ctxctl(struct gf100_gr_priv *priv)
+gf100_gr_init_ctxctl(struct gf100_gr *gr)
{
- struct gf100_gr_oclass *oclass = (void *)nv_object(priv)->oclass;
- struct gf100_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_gr_oclass *oclass = (void *)nv_object(gr)->oclass;
+ struct gf100_grctx_oclass *cclass = (void *)nv_engine(gr)->cclass;
int i;
- if (priv->firmware) {
+ if (gr->firmware) {
/* load fuc microcode */
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
- gf100_gr_init_fw(priv, 0x409000, &priv->fuc409c,
- &priv->fuc409d);
- gf100_gr_init_fw(priv, 0x41a000, &priv->fuc41ac,
- &priv->fuc41ad);
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 0);
+ gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c,
+ &gr->fuc409d);
+ gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac,
+ &gr->fuc41ad);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
/* start both of them running */
- nv_wr32(priv, 0x409840, 0xffffffff);
- nv_wr32(priv, 0x41a10c, 0x00000000);
- nv_wr32(priv, 0x40910c, 0x00000000);
- nv_wr32(priv, 0x41a100, 0x00000002);
- nv_wr32(priv, 0x409100, 0x00000002);
- if (!nv_wait(priv, 0x409800, 0x00000001, 0x00000001))
- nv_warn(priv, "0x409800 wait failed\n");
-
- nv_wr32(priv, 0x409840, 0xffffffff);
- nv_wr32(priv, 0x409500, 0x7fffffff);
- nv_wr32(priv, 0x409504, 0x00000021);
-
- nv_wr32(priv, 0x409840, 0xffffffff);
- nv_wr32(priv, 0x409500, 0x00000000);
- nv_wr32(priv, 0x409504, 0x00000010);
- if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
- nv_error(priv, "fuc09 req 0x10 timeout\n");
+ nv_wr32(gr, 0x409840, 0xffffffff);
+ nv_wr32(gr, 0x41a10c, 0x00000000);
+ nv_wr32(gr, 0x40910c, 0x00000000);
+ nv_wr32(gr, 0x41a100, 0x00000002);
+ nv_wr32(gr, 0x409100, 0x00000002);
+ if (!nv_wait(gr, 0x409800, 0x00000001, 0x00000001))
+ nv_warn(gr, "0x409800 wait failed\n");
+
+ nv_wr32(gr, 0x409840, 0xffffffff);
+ nv_wr32(gr, 0x409500, 0x7fffffff);
+ nv_wr32(gr, 0x409504, 0x00000021);
+
+ nv_wr32(gr, 0x409840, 0xffffffff);
+ nv_wr32(gr, 0x409500, 0x00000000);
+ nv_wr32(gr, 0x409504, 0x00000010);
+ if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) {
+ nv_error(gr, "fuc09 req 0x10 timeout\n");
return -EBUSY;
}
- priv->size = nv_rd32(priv, 0x409800);
+ gr->size = nv_rd32(gr, 0x409800);
- nv_wr32(priv, 0x409840, 0xffffffff);
- nv_wr32(priv, 0x409500, 0x00000000);
- nv_wr32(priv, 0x409504, 0x00000016);
- if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
- nv_error(priv, "fuc09 req 0x16 timeout\n");
+ nv_wr32(gr, 0x409840, 0xffffffff);
+ nv_wr32(gr, 0x409500, 0x00000000);
+ nv_wr32(gr, 0x409504, 0x00000016);
+ if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) {
+ nv_error(gr, "fuc09 req 0x16 timeout\n");
return -EBUSY;
}
- nv_wr32(priv, 0x409840, 0xffffffff);
- nv_wr32(priv, 0x409500, 0x00000000);
- nv_wr32(priv, 0x409504, 0x00000025);
- if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
- nv_error(priv, "fuc09 req 0x25 timeout\n");
+ nv_wr32(gr, 0x409840, 0xffffffff);
+ nv_wr32(gr, 0x409500, 0x00000000);
+ nv_wr32(gr, 0x409504, 0x00000025);
+ if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) {
+ nv_error(gr, "fuc09 req 0x25 timeout\n");
return -EBUSY;
}
- if (nv_device(priv)->chipset >= 0xe0) {
- nv_wr32(priv, 0x409800, 0x00000000);
- nv_wr32(priv, 0x409500, 0x00000001);
- nv_wr32(priv, 0x409504, 0x00000030);
- if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
- nv_error(priv, "fuc09 req 0x30 timeout\n");
+ if (nv_device(gr)->chipset >= 0xe0) {
+ nv_wr32(gr, 0x409800, 0x00000000);
+ nv_wr32(gr, 0x409500, 0x00000001);
+ nv_wr32(gr, 0x409504, 0x00000030);
+ if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) {
+ nv_error(gr, "fuc09 req 0x30 timeout\n");
return -EBUSY;
}
- nv_wr32(priv, 0x409810, 0xb00095c8);
- nv_wr32(priv, 0x409800, 0x00000000);
- nv_wr32(priv, 0x409500, 0x00000001);
- nv_wr32(priv, 0x409504, 0x00000031);
- if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
- nv_error(priv, "fuc09 req 0x31 timeout\n");
+ nv_wr32(gr, 0x409810, 0xb00095c8);
+ nv_wr32(gr, 0x409800, 0x00000000);
+ nv_wr32(gr, 0x409500, 0x00000001);
+ nv_wr32(gr, 0x409504, 0x00000031);
+ if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) {
+ nv_error(gr, "fuc09 req 0x31 timeout\n");
return -EBUSY;
}
- nv_wr32(priv, 0x409810, 0x00080420);
- nv_wr32(priv, 0x409800, 0x00000000);
- nv_wr32(priv, 0x409500, 0x00000001);
- nv_wr32(priv, 0x409504, 0x00000032);
- if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
- nv_error(priv, "fuc09 req 0x32 timeout\n");
+ nv_wr32(gr, 0x409810, 0x00080420);
+ nv_wr32(gr, 0x409800, 0x00000000);
+ nv_wr32(gr, 0x409500, 0x00000001);
+ nv_wr32(gr, 0x409504, 0x00000032);
+ if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) {
+ nv_error(gr, "fuc09 req 0x32 timeout\n");
return -EBUSY;
}
- nv_wr32(priv, 0x409614, 0x00000070);
- nv_wr32(priv, 0x409614, 0x00000770);
- nv_wr32(priv, 0x40802c, 0x00000001);
+ nv_wr32(gr, 0x409614, 0x00000070);
+ nv_wr32(gr, 0x409614, 0x00000770);
+ nv_wr32(gr, 0x40802c, 0x00000001);
}
- if (priv->data == NULL) {
- int ret = gf100_grctx_generate(priv);
+ if (gr->data == NULL) {
+ int ret = gf100_grctx_generate(gr);
if (ret) {
- nv_error(priv, "failed to construct context\n");
+ nv_error(gr, "failed to construct context\n");
return ret;
}
}
}
/* load HUB microcode */
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
- nv_wr32(priv, 0x4091c0, 0x01000000);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 0);
+ nv_wr32(gr, 0x4091c0, 0x01000000);
for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++)
- nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]);
+ nv_wr32(gr, 0x4091c4, oclass->fecs.ucode->data.data[i]);
- nv_wr32(priv, 0x409180, 0x01000000);
+ nv_wr32(gr, 0x409180, 0x01000000);
for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) {
if ((i & 0x3f) == 0)
- nv_wr32(priv, 0x409188, i >> 6);
- nv_wr32(priv, 0x409184, oclass->fecs.ucode->code.data[i]);
+ nv_wr32(gr, 0x409188, i >> 6);
+ nv_wr32(gr, 0x409184, oclass->fecs.ucode->code.data[i]);
}
/* load GPC microcode */
- nv_wr32(priv, 0x41a1c0, 0x01000000);
+ nv_wr32(gr, 0x41a1c0, 0x01000000);
for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++)
- nv_wr32(priv, 0x41a1c4, oclass->gpccs.ucode->data.data[i]);
+ nv_wr32(gr, 0x41a1c4, oclass->gpccs.ucode->data.data[i]);
- nv_wr32(priv, 0x41a180, 0x01000000);
+ nv_wr32(gr, 0x41a180, 0x01000000);
for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) {
if ((i & 0x3f) == 0)
- nv_wr32(priv, 0x41a188, i >> 6);
- nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]);
+ nv_wr32(gr, 0x41a188, i >> 6);
+ nv_wr32(gr, 0x41a184, oclass->gpccs.ucode->code.data[i]);
}
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
/* load register lists */
- gf100_gr_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000);
- gf100_gr_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000);
- gf100_gr_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800);
- gf100_gr_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00);
+ gf100_gr_init_csdata(gr, cclass->hub, 0x409000, 0x000, 0x000000);
+ gf100_gr_init_csdata(gr, cclass->gpc, 0x41a000, 0x000, 0x418000);
+ gf100_gr_init_csdata(gr, cclass->tpc, 0x41a000, 0x004, 0x419800);
+ gf100_gr_init_csdata(gr, cclass->ppc, 0x41a000, 0x008, 0x41be00);
/* start HUB ucode running, it'll init the GPCs */
- nv_wr32(priv, 0x40910c, 0x00000000);
- nv_wr32(priv, 0x409100, 0x00000002);
- if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) {
- nv_error(priv, "HUB_INIT timed out\n");
- gf100_gr_ctxctl_debug(priv);
+ nv_wr32(gr, 0x40910c, 0x00000000);
+ nv_wr32(gr, 0x409100, 0x00000002);
+ if (!nv_wait(gr, 0x409800, 0x80000000, 0x80000000)) {
+ nv_error(gr, "HUB_INIT timed out\n");
+ gf100_gr_ctxctl_debug(gr);
return -EBUSY;
}
- priv->size = nv_rd32(priv, 0x409804);
- if (priv->data == NULL) {
- int ret = gf100_grctx_generate(priv);
+ gr->size = nv_rd32(gr, 0x409804);
+ if (gr->data == NULL) {
+ int ret = gf100_grctx_generate(gr);
if (ret) {
- nv_error(priv, "failed to construct context\n");
+ nv_error(gr, "failed to construct context\n");
return ret;
}
}
gf100_gr_init(struct nvkm_object *object)
{
struct gf100_gr_oclass *oclass = (void *)object->oclass;
- struct gf100_gr_priv *priv = (void *)object;
- const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
+ struct gf100_gr *gr = (void *)object;
+ const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc, rop;
int ret, i;
- ret = nvkm_gr_init(&priv->base);
+ ret = nvkm_gr_init(&gr->base);
if (ret)
return ret;
- nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
- nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
+ nv_wr32(gr, GPC_BCAST(0x0880), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x08a4), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x0888), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x088c), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x0890), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x0894), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8);
+ nv_wr32(gr, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8);
- gf100_gr_mmio(priv, oclass->mmio);
+ gf100_gr_mmio(gr, oclass->mmio);
- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
- for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
+ memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
+ for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
do {
- gpc = (gpc + 1) % priv->gpc_nr;
+ gpc = (gpc + 1) % gr->gpc_nr;
} while (!tpcnr[gpc]);
- tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
+ tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
data[i / 8] |= tpc << ((i % 8) * 4);
}
- nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
- nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
- nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
- nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
+ nv_wr32(gr, GPC_BCAST(0x0980), data[0]);
+ nv_wr32(gr, GPC_BCAST(0x0984), data[1]);
+ nv_wr32(gr, GPC_BCAST(0x0988), data[2]);
+ nv_wr32(gr, GPC_BCAST(0x098c), data[3]);
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- nv_wr32(priv, GPC_UNIT(gpc, 0x0914),
- priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 |
- priv->tpc_total);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0914),
+ gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 |
+ gr->tpc_total);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918);
}
- if (nv_device(priv)->chipset != 0xd7)
- nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918);
+ if (nv_device(gr)->chipset != 0xd7)
+ nv_wr32(gr, GPC_BCAST(0x1bd4), magicgpc918);
else
- nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
-
- nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
-
- nv_wr32(priv, 0x400500, 0x00010001);
-
- nv_wr32(priv, 0x400100, 0xffffffff);
- nv_wr32(priv, 0x40013c, 0xffffffff);
-
- nv_wr32(priv, 0x409c24, 0x000f0000);
- nv_wr32(priv, 0x404000, 0xc0000000);
- nv_wr32(priv, 0x404600, 0xc0000000);
- nv_wr32(priv, 0x408030, 0xc0000000);
- nv_wr32(priv, 0x40601c, 0xc0000000);
- nv_wr32(priv, 0x404490, 0xc0000000);
- nv_wr32(priv, 0x406018, 0xc0000000);
- nv_wr32(priv, 0x405840, 0xc0000000);
- nv_wr32(priv, 0x405844, 0x00ffffff);
- nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
- nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
-
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
- for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
+ nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918);
+
+ nv_wr32(gr, GPC_BCAST(0x08ac), nv_rd32(gr, 0x100800));
+
+ nv_wr32(gr, 0x400500, 0x00010001);
+
+ nv_wr32(gr, 0x400100, 0xffffffff);
+ nv_wr32(gr, 0x40013c, 0xffffffff);
+
+ nv_wr32(gr, 0x409c24, 0x000f0000);
+ nv_wr32(gr, 0x404000, 0xc0000000);
+ nv_wr32(gr, 0x404600, 0xc0000000);
+ nv_wr32(gr, 0x408030, 0xc0000000);
+ nv_wr32(gr, 0x40601c, 0xc0000000);
+ nv_wr32(gr, 0x404490, 0xc0000000);
+ nv_wr32(gr, 0x406018, 0xc0000000);
+ nv_wr32(gr, 0x405840, 0xc0000000);
+ nv_wr32(gr, 0x405844, 0x00ffffff);
+ nv_mask(gr, 0x419cc0, 0x00000008, 0x00000008);
+ nv_mask(gr, 0x419eb4, 0x00001000, 0x00001000);
+
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000);
+ for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
}
- nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
- nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
}
- for (rop = 0; rop < priv->rop_nr; rop++) {
- nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
- nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
- nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
- nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
+ for (rop = 0; rop < gr->rop_nr; rop++) {
+ nv_wr32(gr, ROP_UNIT(rop, 0x144), 0xc0000000);
+ nv_wr32(gr, ROP_UNIT(rop, 0x070), 0xc0000000);
+ nv_wr32(gr, ROP_UNIT(rop, 0x204), 0xffffffff);
+ nv_wr32(gr, ROP_UNIT(rop, 0x208), 0xffffffff);
}
- nv_wr32(priv, 0x400108, 0xffffffff);
- nv_wr32(priv, 0x400138, 0xffffffff);
- nv_wr32(priv, 0x400118, 0xffffffff);
- nv_wr32(priv, 0x400130, 0xffffffff);
- nv_wr32(priv, 0x40011c, 0xffffffff);
- nv_wr32(priv, 0x400134, 0xffffffff);
+ nv_wr32(gr, 0x400108, 0xffffffff);
+ nv_wr32(gr, 0x400138, 0xffffffff);
+ nv_wr32(gr, 0x400118, 0xffffffff);
+ nv_wr32(gr, 0x400130, 0xffffffff);
+ nv_wr32(gr, 0x40011c, 0xffffffff);
+ nv_wr32(gr, 0x400134, 0xffffffff);
- nv_wr32(priv, 0x400054, 0x34ce3464);
+ nv_wr32(gr, 0x400054, 0x34ce3464);
- gf100_gr_zbc_init(priv);
+ gf100_gr_zbc_init(gr);
- return gf100_gr_init_ctxctl(priv);
+ return gf100_gr_init_ctxctl(gr);
}
void
}
int
-gf100_gr_ctor_fw(struct gf100_gr_priv *priv, const char *fwname,
+gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname,
struct gf100_gr_fuc *fuc)
{
- struct nvkm_device *device = nv_device(priv);
+ struct nvkm_device *device = nv_device(gr);
const struct firmware *fw;
char f[64];
char cname[16];
snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname);
ret = request_firmware(&fw, f, nv_device_base(device));
if (ret) {
- nv_error(priv, "failed to load %s\n", fwname);
+ nv_error(gr, "failed to load %s\n", fwname);
return ret;
}
void
gf100_gr_dtor(struct nvkm_object *object)
{
- struct gf100_gr_priv *priv = (void *)object;
+ struct gf100_gr *gr = (void *)object;
- kfree(priv->data);
+ kfree(gr->data);
- gf100_gr_dtor_fw(&priv->fuc409c);
- gf100_gr_dtor_fw(&priv->fuc409d);
- gf100_gr_dtor_fw(&priv->fuc41ac);
- gf100_gr_dtor_fw(&priv->fuc41ad);
+ gf100_gr_dtor_fw(&gr->fuc409c);
+ gf100_gr_dtor_fw(&gr->fuc409d);
+ gf100_gr_dtor_fw(&gr->fuc41ac);
+ gf100_gr_dtor_fw(&gr->fuc41ad);
- nvkm_gpuobj_ref(NULL, &priv->unk4188b8);
- nvkm_gpuobj_ref(NULL, &priv->unk4188b4);
+ nvkm_gpuobj_ref(NULL, &gr->unk4188b8);
+ nvkm_gpuobj_ref(NULL, &gr->unk4188b4);
- nvkm_gr_destroy(&priv->base);
+ nvkm_gr_destroy(&gr->base);
}
int
{
struct gf100_gr_oclass *oclass = (void *)bclass;
struct nvkm_device *device = nv_device(parent);
- struct gf100_gr_priv *priv;
+ struct gf100_gr *gr;
bool use_ext_fw, enable;
int ret, i, j;
oclass->fecs.ucode == NULL);
enable = use_ext_fw || oclass->fecs.ucode != NULL;
- ret = nvkm_gr_create(parent, engine, bclass, enable, &priv);
- *pobject = nv_object(priv);
+ ret = nvkm_gr_create(parent, engine, bclass, enable, &gr);
+ *pobject = nv_object(gr);
if (ret)
return ret;
- nv_subdev(priv)->unit = 0x08001000;
- nv_subdev(priv)->intr = gf100_gr_intr;
+ nv_subdev(gr)->unit = 0x08001000;
+ nv_subdev(gr)->intr = gf100_gr_intr;
- priv->base.units = gf100_gr_units;
+ gr->base.units = gf100_gr_units;
if (use_ext_fw) {
- nv_info(priv, "using external firmware\n");
- if (gf100_gr_ctor_fw(priv, "fecs_inst", &priv->fuc409c) ||
- gf100_gr_ctor_fw(priv, "fecs_data", &priv->fuc409d) ||
- gf100_gr_ctor_fw(priv, "gpccs_inst", &priv->fuc41ac) ||
- gf100_gr_ctor_fw(priv, "gpccs_data", &priv->fuc41ad))
+ nv_info(gr, "using external firmware\n");
+ if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) ||
+ gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) ||
+ gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) ||
+ gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad))
return -ENODEV;
- priv->firmware = true;
+ gr->firmware = true;
}
- ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
- &priv->unk4188b4);
+ ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x1000, 256, 0,
+ &gr->unk4188b4);
if (ret)
return ret;
- ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
- &priv->unk4188b8);
+ ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x1000, 256, 0,
+ &gr->unk4188b8);
if (ret)
return ret;
for (i = 0; i < 0x1000; i += 4) {
- nv_wo32(priv->unk4188b4, i, 0x00000010);
- nv_wo32(priv->unk4188b8, i, 0x00000010);
- }
-
- priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16;
- priv->gpc_nr = nv_rd32(priv, 0x409604) & 0x0000001f;
- for (i = 0; i < priv->gpc_nr; i++) {
- priv->tpc_nr[i] = nv_rd32(priv, GPC_UNIT(i, 0x2608));
- priv->tpc_total += priv->tpc_nr[i];
- priv->ppc_nr[i] = oclass->ppc_nr;
- for (j = 0; j < priv->ppc_nr[i]; j++) {
- u8 mask = nv_rd32(priv, GPC_UNIT(i, 0x0c30 + (j * 4)));
- priv->ppc_tpc_nr[i][j] = hweight8(mask);
+ nv_wo32(gr->unk4188b4, i, 0x00000010);
+ nv_wo32(gr->unk4188b8, i, 0x00000010);
+ }
+
+ gr->rop_nr = (nv_rd32(gr, 0x409604) & 0x001f0000) >> 16;
+ gr->gpc_nr = nv_rd32(gr, 0x409604) & 0x0000001f;
+ for (i = 0; i < gr->gpc_nr; i++) {
+ gr->tpc_nr[i] = nv_rd32(gr, GPC_UNIT(i, 0x2608));
+ gr->tpc_total += gr->tpc_nr[i];
+ gr->ppc_nr[i] = oclass->ppc_nr;
+ for (j = 0; j < gr->ppc_nr[i]; j++) {
+ u8 mask = nv_rd32(gr, GPC_UNIT(i, 0x0c30 + (j * 4)));
+ gr->ppc_tpc_nr[i][j] = hweight8(mask);
}
}
/*XXX: these need figuring out... though it might not even matter */
- switch (nv_device(priv)->chipset) {
+ switch (nv_device(gr)->chipset) {
case 0xc0:
- if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */
- priv->magic_not_rop_nr = 0x07;
+ if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */
+ gr->magic_not_rop_nr = 0x07;
} else
- if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */
- priv->magic_not_rop_nr = 0x05;
+ if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */
+ gr->magic_not_rop_nr = 0x05;
} else
- if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */
- priv->magic_not_rop_nr = 0x06;
+ if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */
+ gr->magic_not_rop_nr = 0x06;
}
break;
case 0xc3: /* 450, 4/0/0/0, 2 */
- priv->magic_not_rop_nr = 0x03;
+ gr->magic_not_rop_nr = 0x03;
break;
case 0xc4: /* 460, 3/4/0/0, 4 */
- priv->magic_not_rop_nr = 0x01;
+ gr->magic_not_rop_nr = 0x01;
break;
case 0xc1: /* 2/0/0/0, 1 */
- priv->magic_not_rop_nr = 0x01;
+ gr->magic_not_rop_nr = 0x01;
break;
case 0xc8: /* 4/4/3/4, 5 */
- priv->magic_not_rop_nr = 0x06;
+ gr->magic_not_rop_nr = 0x06;
break;
case 0xce: /* 4/4/0/0, 4 */
- priv->magic_not_rop_nr = 0x03;
+ gr->magic_not_rop_nr = 0x03;
break;
case 0xcf: /* 4/0/0/0, 3 */
- priv->magic_not_rop_nr = 0x03;
+ gr->magic_not_rop_nr = 0x03;
break;
case 0xd7:
case 0xd9: /* 1/0/0/0, 1 */
case 0xea: /* gk20a */
case 0x12b: /* gm20b */
- priv->magic_not_rop_nr = 0x01;
+ gr->magic_not_rop_nr = 0x01;
break;
}
- nv_engine(priv)->cclass = *oclass->cclass;
- nv_engine(priv)->sclass = oclass->sclass;
+ nv_engine(gr)->cclass = *oclass->cclass;
+ nv_engine(gr)->sclass = oclass->sclass;
return 0;
}
u32 l2;
};
-struct gf100_gr_priv {
+struct gf100_gr {
struct nvkm_gr base;
struct gf100_gr_fuc fuc409c;
struct nvkm_object **);
void gf100_gr_context_dtor(struct nvkm_object *);
-void gf100_gr_ctxctl_debug(struct gf100_gr_priv *);
+void gf100_gr_ctxctl_debug(struct gf100_gr *);
void gf100_gr_dtor_fw(struct gf100_gr_fuc *);
-int gf100_gr_ctor_fw(struct gf100_gr_priv *, const char *,
+int gf100_gr_ctor_fw(struct gf100_gr *, const char *,
struct gf100_gr_fuc *);
u64 gf100_gr_units(struct nvkm_gr *);
int gf100_gr_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_object **);
void gf100_gr_dtor(struct nvkm_object *);
int gf100_gr_init(struct nvkm_object *);
-void gf100_gr_zbc_init(struct gf100_gr_priv *);
+void gf100_gr_zbc_init(struct gf100_gr *);
int gk104_gr_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *data, u32 size,
int ppc_nr;
};
-int gf100_gr_wait_idle(struct gf100_gr_priv *);
-void gf100_gr_mmio(struct gf100_gr_priv *, const struct gf100_gr_pack *);
-void gf100_gr_icmd(struct gf100_gr_priv *, const struct gf100_gr_pack *);
-void gf100_gr_mthd(struct gf100_gr_priv *, const struct gf100_gr_pack *);
-int gf100_gr_init_ctxctl(struct gf100_gr_priv *);
+int gf100_gr_wait_idle(struct gf100_gr *);
+void gf100_gr_mmio(struct gf100_gr *, const struct gf100_gr_pack *);
+void gf100_gr_icmd(struct gf100_gr *, const struct gf100_gr_pack *);
+void gf100_gr_mthd(struct gf100_gr *, const struct gf100_gr_pack *);
+int gf100_gr_init_ctxctl(struct gf100_gr *);
/* register init value lists */
extern const struct gf100_gr_init gm107_gr_init_l1c_0[];
extern const struct gf100_gr_init gm107_gr_init_wwdx_0[];
extern const struct gf100_gr_init gm107_gr_init_cbm_0[];
-void gm107_gr_init_bios(struct gf100_gr_priv *);
+void gm107_gr_init_bios(struct gf100_gr *);
extern const struct gf100_gr_pack gm204_gr_pack_mmio[];
#endif
gk104_gr_init(struct nvkm_object *object)
{
struct gf100_gr_oclass *oclass = (void *)object->oclass;
- struct gf100_gr_priv *priv = (void *)object;
- struct nvkm_pmu *pmu = nvkm_pmu(priv);
- const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
+ struct gf100_gr *gr = (void *)object;
+ struct nvkm_pmu *pmu = nvkm_pmu(gr);
+ const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc, rop;
if (pmu)
pmu->pgob(pmu, false);
- ret = nvkm_gr_init(&priv->base);
+ ret = nvkm_gr_init(&gr->base);
if (ret)
return ret;
- nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
- nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
+ nv_wr32(gr, GPC_BCAST(0x0880), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x08a4), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x0888), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x088c), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x0890), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x0894), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8);
+ nv_wr32(gr, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8);
- gf100_gr_mmio(priv, oclass->mmio);
+ gf100_gr_mmio(gr, oclass->mmio);
- nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001);
+ nv_wr32(gr, GPC_UNIT(0, 0x3018), 0x00000001);
memset(data, 0x00, sizeof(data));
- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
- for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
+ memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
+ for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
do {
- gpc = (gpc + 1) % priv->gpc_nr;
+ gpc = (gpc + 1) % gr->gpc_nr;
} while (!tpcnr[gpc]);
- tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
+ tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
data[i / 8] |= tpc << ((i % 8) * 4);
}
- nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
- nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
- nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
- nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
-
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- nv_wr32(priv, GPC_UNIT(gpc, 0x0914),
- priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 |
- priv->tpc_total);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
+ nv_wr32(gr, GPC_BCAST(0x0980), data[0]);
+ nv_wr32(gr, GPC_BCAST(0x0984), data[1]);
+ nv_wr32(gr, GPC_BCAST(0x0988), data[2]);
+ nv_wr32(gr, GPC_BCAST(0x098c), data[3]);
+
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0914),
+ gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 |
+ gr->tpc_total);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918);
}
- nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
- nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
-
- nv_wr32(priv, 0x400500, 0x00010001);
-
- nv_wr32(priv, 0x400100, 0xffffffff);
- nv_wr32(priv, 0x40013c, 0xffffffff);
-
- nv_wr32(priv, 0x409ffc, 0x00000000);
- nv_wr32(priv, 0x409c14, 0x00003e3e);
- nv_wr32(priv, 0x409c24, 0x000f0001);
- nv_wr32(priv, 0x404000, 0xc0000000);
- nv_wr32(priv, 0x404600, 0xc0000000);
- nv_wr32(priv, 0x408030, 0xc0000000);
- nv_wr32(priv, 0x404490, 0xc0000000);
- nv_wr32(priv, 0x406018, 0xc0000000);
- nv_wr32(priv, 0x407020, 0x40000000);
- nv_wr32(priv, 0x405840, 0xc0000000);
- nv_wr32(priv, 0x405844, 0x00ffffff);
- nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
- nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
-
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- nv_wr32(priv, GPC_UNIT(gpc, 0x3038), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
- for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
+ nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918);
+ nv_wr32(gr, GPC_BCAST(0x08ac), nv_rd32(gr, 0x100800));
+
+ nv_wr32(gr, 0x400500, 0x00010001);
+
+ nv_wr32(gr, 0x400100, 0xffffffff);
+ nv_wr32(gr, 0x40013c, 0xffffffff);
+
+ nv_wr32(gr, 0x409ffc, 0x00000000);
+ nv_wr32(gr, 0x409c14, 0x00003e3e);
+ nv_wr32(gr, 0x409c24, 0x000f0001);
+ nv_wr32(gr, 0x404000, 0xc0000000);
+ nv_wr32(gr, 0x404600, 0xc0000000);
+ nv_wr32(gr, 0x408030, 0xc0000000);
+ nv_wr32(gr, 0x404490, 0xc0000000);
+ nv_wr32(gr, 0x406018, 0xc0000000);
+ nv_wr32(gr, 0x407020, 0x40000000);
+ nv_wr32(gr, 0x405840, 0xc0000000);
+ nv_wr32(gr, 0x405844, 0x00ffffff);
+ nv_mask(gr, 0x419cc0, 0x00000008, 0x00000008);
+ nv_mask(gr, 0x419eb4, 0x00001000, 0x00001000);
+
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ nv_wr32(gr, GPC_UNIT(gpc, 0x3038), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000);
+ for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
}
- nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
- nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
}
- for (rop = 0; rop < priv->rop_nr; rop++) {
- nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
- nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
- nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
- nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
+ for (rop = 0; rop < gr->rop_nr; rop++) {
+ nv_wr32(gr, ROP_UNIT(rop, 0x144), 0xc0000000);
+ nv_wr32(gr, ROP_UNIT(rop, 0x070), 0xc0000000);
+ nv_wr32(gr, ROP_UNIT(rop, 0x204), 0xffffffff);
+ nv_wr32(gr, ROP_UNIT(rop, 0x208), 0xffffffff);
}
- nv_wr32(priv, 0x400108, 0xffffffff);
- nv_wr32(priv, 0x400138, 0xffffffff);
- nv_wr32(priv, 0x400118, 0xffffffff);
- nv_wr32(priv, 0x400130, 0xffffffff);
- nv_wr32(priv, 0x40011c, 0xffffffff);
- nv_wr32(priv, 0x400134, 0xffffffff);
+ nv_wr32(gr, 0x400108, 0xffffffff);
+ nv_wr32(gr, 0x400138, 0xffffffff);
+ nv_wr32(gr, 0x400118, 0xffffffff);
+ nv_wr32(gr, 0x400130, 0xffffffff);
+ nv_wr32(gr, 0x40011c, 0xffffffff);
+ nv_wr32(gr, 0x400134, 0xffffffff);
- nv_wr32(priv, 0x400054, 0x34ce3464);
+ nv_wr32(gr, 0x400054, 0x34ce3464);
- gf100_gr_zbc_init(priv);
+ gf100_gr_zbc_init(gr);
- return gf100_gr_init_ctxctl(priv);
+ return gf100_gr_init_ctxctl(gr);
}
int
struct nvkm_object **pobject)
{
int err;
- struct gf100_gr_priv *priv;
+ struct gf100_gr *gr;
struct gf100_gr_fuc fuc;
err = gf100_gr_ctor(parent, engine, oclass, data, size, pobject);
if (err)
return err;
- priv = (void *)*pobject;
+ gr = (void *)*pobject;
- err = gf100_gr_ctor_fw(priv, "sw_nonctx", &fuc);
+ err = gf100_gr_ctor_fw(gr, "sw_nonctx", &fuc);
if (err)
return err;
- priv->fuc_sw_nonctx = gk20a_gr_av_to_init(&fuc);
+ gr->fuc_sw_nonctx = gk20a_gr_av_to_init(&fuc);
gf100_gr_dtor_fw(&fuc);
- if (IS_ERR(priv->fuc_sw_nonctx))
- return PTR_ERR(priv->fuc_sw_nonctx);
+ if (IS_ERR(gr->fuc_sw_nonctx))
+ return PTR_ERR(gr->fuc_sw_nonctx);
- err = gf100_gr_ctor_fw(priv, "sw_ctx", &fuc);
+ err = gf100_gr_ctor_fw(gr, "sw_ctx", &fuc);
if (err)
return err;
- priv->fuc_sw_ctx = gk20a_gr_aiv_to_init(&fuc);
+ gr->fuc_sw_ctx = gk20a_gr_aiv_to_init(&fuc);
gf100_gr_dtor_fw(&fuc);
- if (IS_ERR(priv->fuc_sw_ctx))
- return PTR_ERR(priv->fuc_sw_ctx);
+ if (IS_ERR(gr->fuc_sw_ctx))
+ return PTR_ERR(gr->fuc_sw_ctx);
- err = gf100_gr_ctor_fw(priv, "sw_bundle_init", &fuc);
+ err = gf100_gr_ctor_fw(gr, "sw_bundle_init", &fuc);
if (err)
return err;
- priv->fuc_bundle = gk20a_gr_av_to_init(&fuc);
+ gr->fuc_bundle = gk20a_gr_av_to_init(&fuc);
gf100_gr_dtor_fw(&fuc);
- if (IS_ERR(priv->fuc_bundle))
- return PTR_ERR(priv->fuc_bundle);
+ if (IS_ERR(gr->fuc_bundle))
+ return PTR_ERR(gr->fuc_bundle);
- err = gf100_gr_ctor_fw(priv, "sw_method_init", &fuc);
+ err = gf100_gr_ctor_fw(gr, "sw_method_init", &fuc);
if (err)
return err;
- priv->fuc_method = gk20a_gr_av_to_method(&fuc);
+ gr->fuc_method = gk20a_gr_av_to_method(&fuc);
gf100_gr_dtor_fw(&fuc);
- if (IS_ERR(priv->fuc_method))
- return PTR_ERR(priv->fuc_method);
+ if (IS_ERR(gr->fuc_method))
+ return PTR_ERR(gr->fuc_method);
return 0;
}
void
gk20a_gr_dtor(struct nvkm_object *object)
{
- struct gf100_gr_priv *priv = (void *)object;
+ struct gf100_gr *gr = (void *)object;
- gk20a_gr_init_dtor(priv->fuc_method);
- gk20a_gr_init_dtor(priv->fuc_bundle);
- gk20a_gr_init_dtor(priv->fuc_sw_ctx);
- gk20a_gr_init_dtor(priv->fuc_sw_nonctx);
+ gk20a_gr_init_dtor(gr->fuc_method);
+ gk20a_gr_init_dtor(gr->fuc_bundle);
+ gk20a_gr_init_dtor(gr->fuc_sw_ctx);
+ gk20a_gr_init_dtor(gr->fuc_sw_nonctx);
gf100_gr_dtor(object);
}
static int
-gk20a_gr_wait_mem_scrubbing(struct gf100_gr_priv *priv)
+gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr)
{
- if (!nv_wait(priv, 0x40910c, 0x6, 0x0)) {
- nv_error(priv, "FECS mem scrubbing timeout\n");
+ if (!nv_wait(gr, 0x40910c, 0x6, 0x0)) {
+ nv_error(gr, "FECS mem scrubbing timeout\n");
return -ETIMEDOUT;
}
- if (!nv_wait(priv, 0x41a10c, 0x6, 0x0)) {
- nv_error(priv, "GPCCS mem scrubbing timeout\n");
+ if (!nv_wait(gr, 0x41a10c, 0x6, 0x0)) {
+ nv_error(gr, "GPCCS mem scrubbing timeout\n");
return -ETIMEDOUT;
}
}
static void
-gk20a_gr_set_hww_esr_report_mask(struct gf100_gr_priv *priv)
+gk20a_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
{
- nv_wr32(priv, 0x419e44, 0x1ffffe);
- nv_wr32(priv, 0x419e4c, 0x7f);
+ nv_wr32(gr, 0x419e44, 0x1ffffe);
+ nv_wr32(gr, 0x419e4c, 0x7f);
}
int
gk20a_gr_init(struct nvkm_object *object)
{
struct gk20a_gr_oclass *oclass = (void *)object->oclass;
- struct gf100_gr_priv *priv = (void *)object;
- const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
+ struct gf100_gr *gr = (void *)object;
+ const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc;
int ret, i;
- ret = nvkm_gr_init(&priv->base);
+ ret = nvkm_gr_init(&gr->base);
if (ret)
return ret;
/* Clear SCC RAM */
- nv_wr32(priv, 0x40802c, 0x1);
+ nv_wr32(gr, 0x40802c, 0x1);
- gf100_gr_mmio(priv, priv->fuc_sw_nonctx);
+ gf100_gr_mmio(gr, gr->fuc_sw_nonctx);
- ret = gk20a_gr_wait_mem_scrubbing(priv);
+ ret = gk20a_gr_wait_mem_scrubbing(gr);
if (ret)
return ret;
- ret = gf100_gr_wait_idle(priv);
+ ret = gf100_gr_wait_idle(gr);
if (ret)
return ret;
/* MMU debug buffer */
- nv_wr32(priv, 0x100cc8, priv->unk4188b4->addr >> 8);
- nv_wr32(priv, 0x100ccc, priv->unk4188b8->addr >> 8);
+ nv_wr32(gr, 0x100cc8, gr->unk4188b4->addr >> 8);
+ nv_wr32(gr, 0x100ccc, gr->unk4188b8->addr >> 8);
if (oclass->init_gpc_mmu)
- oclass->init_gpc_mmu(priv);
+ oclass->init_gpc_mmu(gr);
/* Set the PE as stream master */
- nv_mask(priv, 0x503018, 0x1, 0x1);
+ nv_mask(gr, 0x503018, 0x1, 0x1);
/* Zcull init */
memset(data, 0x00, sizeof(data));
- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
- for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
+ memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
+ for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
do {
- gpc = (gpc + 1) % priv->gpc_nr;
+ gpc = (gpc + 1) % gr->gpc_nr;
} while (!tpcnr[gpc]);
- tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
+ tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
data[i / 8] |= tpc << ((i % 8) * 4);
}
- nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
- nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
- nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
- nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
-
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- nv_wr32(priv, GPC_UNIT(gpc, 0x0914),
- priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 |
- priv->tpc_total);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
+ nv_wr32(gr, GPC_BCAST(0x0980), data[0]);
+ nv_wr32(gr, GPC_BCAST(0x0984), data[1]);
+ nv_wr32(gr, GPC_BCAST(0x0988), data[2]);
+ nv_wr32(gr, GPC_BCAST(0x098c), data[3]);
+
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0914),
+ gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 |
+ gr->tpc_total);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918);
}
- nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
+ nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918);
/* Enable FIFO access */
- nv_wr32(priv, 0x400500, 0x00010001);
+ nv_wr32(gr, 0x400500, 0x00010001);
/* Enable interrupts */
- nv_wr32(priv, 0x400100, 0xffffffff);
- nv_wr32(priv, 0x40013c, 0xffffffff);
+ nv_wr32(gr, 0x400100, 0xffffffff);
+ nv_wr32(gr, 0x40013c, 0xffffffff);
/* Enable FECS error interrupts */
- nv_wr32(priv, 0x409c24, 0x000f0000);
+ nv_wr32(gr, 0x409c24, 0x000f0000);
/* Enable hardware warning exceptions */
- nv_wr32(priv, 0x404000, 0xc0000000);
- nv_wr32(priv, 0x404600, 0xc0000000);
+ nv_wr32(gr, 0x404000, 0xc0000000);
+ nv_wr32(gr, 0x404600, 0xc0000000);
if (oclass->set_hww_esr_report_mask)
- oclass->set_hww_esr_report_mask(priv);
+ oclass->set_hww_esr_report_mask(gr);
/* Enable TPC exceptions per GPC */
- nv_wr32(priv, 0x419d0c, 0x2);
- nv_wr32(priv, 0x41ac94, (((1 << priv->tpc_total) - 1) & 0xff) << 16);
+ nv_wr32(gr, 0x419d0c, 0x2);
+ nv_wr32(gr, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16);
/* Reset and enable all exceptions */
- nv_wr32(priv, 0x400108, 0xffffffff);
- nv_wr32(priv, 0x400138, 0xffffffff);
- nv_wr32(priv, 0x400118, 0xffffffff);
- nv_wr32(priv, 0x400130, 0xffffffff);
- nv_wr32(priv, 0x40011c, 0xffffffff);
- nv_wr32(priv, 0x400134, 0xffffffff);
+ nv_wr32(gr, 0x400108, 0xffffffff);
+ nv_wr32(gr, 0x400138, 0xffffffff);
+ nv_wr32(gr, 0x400118, 0xffffffff);
+ nv_wr32(gr, 0x400130, 0xffffffff);
+ nv_wr32(gr, 0x40011c, 0xffffffff);
+ nv_wr32(gr, 0x400134, 0xffffffff);
- gf100_gr_zbc_init(priv);
+ gf100_gr_zbc_init(gr);
- return gf100_gr_init_ctxctl(priv);
+ return gf100_gr_init_ctxctl(gr);
}
struct nvkm_oclass *
struct gk20a_gr_oclass {
struct gf100_gr_oclass gf100;
- void (*init_gpc_mmu)(struct gf100_gr_priv *);
- void (*set_hww_esr_report_mask)(struct gf100_gr_priv *);
+ void (*init_gpc_mmu)(struct gf100_gr *);
+ void (*set_hww_esr_report_mask)(struct gf100_gr *);
};
#endif
******************************************************************************/
void
-gm107_gr_init_bios(struct gf100_gr_priv *priv)
+gm107_gr_init_bios(struct gf100_gr *gr)
{
static const struct {
u32 ctrl;
{ 0x419af0, 0x419af4 },
{ 0x419af8, 0x419afc },
};
- struct nvkm_bios *bios = nvkm_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(gr);
struct nvbios_P0260E infoE;
struct nvbios_P0260X infoX;
int E = -1, X;
while (nvbios_P0260Ep(bios, ++E, &ver, &hdr, &infoE)) {
if (X = -1, E < ARRAY_SIZE(regs)) {
- nv_wr32(priv, regs[E].ctrl, infoE.data);
+ nv_wr32(gr, regs[E].ctrl, infoE.data);
while (nvbios_P0260Xp(bios, ++X, &ver, &hdr, &infoX))
- nv_wr32(priv, regs[E].data, infoX.data);
+ nv_wr32(gr, regs[E].data, infoX.data);
}
}
}
gm107_gr_init(struct nvkm_object *object)
{
struct gf100_gr_oclass *oclass = (void *)object->oclass;
- struct gf100_gr_priv *priv = (void *)object;
- const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
+ struct gf100_gr *gr = (void *)object;
+ const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc, ppc, rop;
int ret, i;
- ret = nvkm_gr_init(&priv->base);
+ ret = nvkm_gr_init(&gr->base);
if (ret)
return ret;
- nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
- nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
+ nv_wr32(gr, GPC_BCAST(0x0880), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x0890), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x0894), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8);
+ nv_wr32(gr, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8);
- gf100_gr_mmio(priv, oclass->mmio);
+ gf100_gr_mmio(gr, oclass->mmio);
- gm107_gr_init_bios(priv);
+ gm107_gr_init_bios(gr);
- nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001);
+ nv_wr32(gr, GPC_UNIT(0, 0x3018), 0x00000001);
memset(data, 0x00, sizeof(data));
- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
- for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
+ memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
+ for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
do {
- gpc = (gpc + 1) % priv->gpc_nr;
+ gpc = (gpc + 1) % gr->gpc_nr;
} while (!tpcnr[gpc]);
- tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
+ tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
data[i / 8] |= tpc << ((i % 8) * 4);
}
- nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
- nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
- nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
- nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
-
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- nv_wr32(priv, GPC_UNIT(gpc, 0x0914),
- priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 |
- priv->tpc_total);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
+ nv_wr32(gr, GPC_BCAST(0x0980), data[0]);
+ nv_wr32(gr, GPC_BCAST(0x0984), data[1]);
+ nv_wr32(gr, GPC_BCAST(0x0988), data[2]);
+ nv_wr32(gr, GPC_BCAST(0x098c), data[3]);
+
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0914),
+ gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 |
+ gr->tpc_total);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918);
}
- nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
- nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
-
- nv_wr32(priv, 0x400500, 0x00010001);
-
- nv_wr32(priv, 0x400100, 0xffffffff);
- nv_wr32(priv, 0x40013c, 0xffffffff);
- nv_wr32(priv, 0x400124, 0x00000002);
- nv_wr32(priv, 0x409c24, 0x000e0000);
-
- nv_wr32(priv, 0x404000, 0xc0000000);
- nv_wr32(priv, 0x404600, 0xc0000000);
- nv_wr32(priv, 0x408030, 0xc0000000);
- nv_wr32(priv, 0x404490, 0xc0000000);
- nv_wr32(priv, 0x406018, 0xc0000000);
- nv_wr32(priv, 0x407020, 0x40000000);
- nv_wr32(priv, 0x405840, 0xc0000000);
- nv_wr32(priv, 0x405844, 0x00ffffff);
- nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
-
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- for (ppc = 0; ppc < 2 /* priv->ppc_nr[gpc] */; ppc++)
- nv_wr32(priv, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
- for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005);
+ nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918);
+ nv_wr32(gr, GPC_BCAST(0x08ac), nv_rd32(gr, 0x100800));
+
+ nv_wr32(gr, 0x400500, 0x00010001);
+
+ nv_wr32(gr, 0x400100, 0xffffffff);
+ nv_wr32(gr, 0x40013c, 0xffffffff);
+ nv_wr32(gr, 0x400124, 0x00000002);
+ nv_wr32(gr, 0x409c24, 0x000e0000);
+
+ nv_wr32(gr, 0x404000, 0xc0000000);
+ nv_wr32(gr, 0x404600, 0xc0000000);
+ nv_wr32(gr, 0x408030, 0xc0000000);
+ nv_wr32(gr, 0x404490, 0xc0000000);
+ nv_wr32(gr, 0x406018, 0xc0000000);
+ nv_wr32(gr, 0x407020, 0x40000000);
+ nv_wr32(gr, 0x405840, 0xc0000000);
+ nv_wr32(gr, 0x405844, 0x00ffffff);
+ nv_mask(gr, 0x419cc0, 0x00000008, 0x00000008);
+
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ for (ppc = 0; ppc < 2 /* gr->ppc_nr[gpc] */; ppc++)
+ nv_wr32(gr, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000);
+ for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005);
}
- nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
- nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
}
- for (rop = 0; rop < priv->rop_nr; rop++) {
- nv_wr32(priv, ROP_UNIT(rop, 0x144), 0x40000000);
- nv_wr32(priv, ROP_UNIT(rop, 0x070), 0x40000000);
- nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
- nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
+ for (rop = 0; rop < gr->rop_nr; rop++) {
+ nv_wr32(gr, ROP_UNIT(rop, 0x144), 0x40000000);
+ nv_wr32(gr, ROP_UNIT(rop, 0x070), 0x40000000);
+ nv_wr32(gr, ROP_UNIT(rop, 0x204), 0xffffffff);
+ nv_wr32(gr, ROP_UNIT(rop, 0x208), 0xffffffff);
}
- nv_wr32(priv, 0x400108, 0xffffffff);
- nv_wr32(priv, 0x400138, 0xffffffff);
- nv_wr32(priv, 0x400118, 0xffffffff);
- nv_wr32(priv, 0x400130, 0xffffffff);
- nv_wr32(priv, 0x40011c, 0xffffffff);
- nv_wr32(priv, 0x400134, 0xffffffff);
+ nv_wr32(gr, 0x400108, 0xffffffff);
+ nv_wr32(gr, 0x400138, 0xffffffff);
+ nv_wr32(gr, 0x400118, 0xffffffff);
+ nv_wr32(gr, 0x400130, 0xffffffff);
+ nv_wr32(gr, 0x40011c, 0xffffffff);
+ nv_wr32(gr, 0x400134, 0xffffffff);
- nv_wr32(priv, 0x400054, 0x2c350f63);
+ nv_wr32(gr, 0x400054, 0x2c350f63);
- gf100_gr_zbc_init(priv);
+ gf100_gr_zbc_init(gr);
- return gf100_gr_init_ctxctl(priv);
+ return gf100_gr_init_ctxctl(gr);
}
#include "fuc/hubgm107.fuc5.h"
******************************************************************************/
static int
-gm204_gr_init_ctxctl(struct gf100_gr_priv *priv)
+gm204_gr_init_ctxctl(struct gf100_gr *gr)
{
return 0;
}
gm204_gr_init(struct nvkm_object *object)
{
struct gf100_gr_oclass *oclass = (void *)object->oclass;
- struct gf100_gr_priv *priv = (void *)object;
- const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
+ struct gf100_gr *gr = (void *)object;
+ const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc, ppc, rop;
int ret, i;
u32 tmp;
- ret = nvkm_gr_init(&priv->base);
+ ret = nvkm_gr_init(&gr->base);
if (ret)
return ret;
- tmp = nv_rd32(priv, 0x100c80); /*XXX: mask? */
- nv_wr32(priv, 0x418880, 0x00001000 | (tmp & 0x00000fff));
- nv_wr32(priv, 0x418890, 0x00000000);
- nv_wr32(priv, 0x418894, 0x00000000);
- nv_wr32(priv, 0x4188b4, priv->unk4188b4->addr >> 8);
- nv_wr32(priv, 0x4188b8, priv->unk4188b8->addr >> 8);
- nv_mask(priv, 0x4188b0, 0x00040000, 0x00040000);
+ tmp = nv_rd32(gr, 0x100c80); /*XXX: mask? */
+ nv_wr32(gr, 0x418880, 0x00001000 | (tmp & 0x00000fff));
+ nv_wr32(gr, 0x418890, 0x00000000);
+ nv_wr32(gr, 0x418894, 0x00000000);
+ nv_wr32(gr, 0x4188b4, gr->unk4188b4->addr >> 8);
+ nv_wr32(gr, 0x4188b8, gr->unk4188b8->addr >> 8);
+ nv_mask(gr, 0x4188b0, 0x00040000, 0x00040000);
/*XXX: belongs in fb */
- nv_wr32(priv, 0x100cc8, priv->unk4188b4->addr >> 8);
- nv_wr32(priv, 0x100ccc, priv->unk4188b8->addr >> 8);
- nv_mask(priv, 0x100cc4, 0x00040000, 0x00040000);
+ nv_wr32(gr, 0x100cc8, gr->unk4188b4->addr >> 8);
+ nv_wr32(gr, 0x100ccc, gr->unk4188b8->addr >> 8);
+ nv_mask(gr, 0x100cc4, 0x00040000, 0x00040000);
- gf100_gr_mmio(priv, oclass->mmio);
+ gf100_gr_mmio(gr, oclass->mmio);
- gm107_gr_init_bios(priv);
+ gm107_gr_init_bios(gr);
- nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001);
+ nv_wr32(gr, GPC_UNIT(0, 0x3018), 0x00000001);
memset(data, 0x00, sizeof(data));
- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
- for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
+ memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
+ for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
do {
- gpc = (gpc + 1) % priv->gpc_nr;
+ gpc = (gpc + 1) % gr->gpc_nr;
} while (!tpcnr[gpc]);
- tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
+ tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
data[i / 8] |= tpc << ((i % 8) * 4);
}
- nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
- nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
- nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
- nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
-
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- nv_wr32(priv, GPC_UNIT(gpc, 0x0914),
- priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 |
- priv->tpc_total);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
+ nv_wr32(gr, GPC_BCAST(0x0980), data[0]);
+ nv_wr32(gr, GPC_BCAST(0x0984), data[1]);
+ nv_wr32(gr, GPC_BCAST(0x0988), data[2]);
+ nv_wr32(gr, GPC_BCAST(0x098c), data[3]);
+
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0914),
+ gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 |
+ gr->tpc_total);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918);
}
- nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
- nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
- nv_wr32(priv, GPC_BCAST(0x033c), nv_rd32(priv, 0x100804));
-
- nv_wr32(priv, 0x400500, 0x00010001);
- nv_wr32(priv, 0x400100, 0xffffffff);
- nv_wr32(priv, 0x40013c, 0xffffffff);
- nv_wr32(priv, 0x400124, 0x00000002);
- nv_wr32(priv, 0x409c24, 0x000e0000);
- nv_wr32(priv, 0x405848, 0xc0000000);
- nv_wr32(priv, 0x40584c, 0x00000001);
- nv_wr32(priv, 0x404000, 0xc0000000);
- nv_wr32(priv, 0x404600, 0xc0000000);
- nv_wr32(priv, 0x408030, 0xc0000000);
- nv_wr32(priv, 0x404490, 0xc0000000);
- nv_wr32(priv, 0x406018, 0xc0000000);
- nv_wr32(priv, 0x407020, 0x40000000);
- nv_wr32(priv, 0x405840, 0xc0000000);
- nv_wr32(priv, 0x405844, 0x00ffffff);
- nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
-
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++)
- nv_wr32(priv, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
- for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005);
+ nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918);
+ nv_wr32(gr, GPC_BCAST(0x08ac), nv_rd32(gr, 0x100800));
+ nv_wr32(gr, GPC_BCAST(0x033c), nv_rd32(gr, 0x100804));
+
+ nv_wr32(gr, 0x400500, 0x00010001);
+ nv_wr32(gr, 0x400100, 0xffffffff);
+ nv_wr32(gr, 0x40013c, 0xffffffff);
+ nv_wr32(gr, 0x400124, 0x00000002);
+ nv_wr32(gr, 0x409c24, 0x000e0000);
+ nv_wr32(gr, 0x405848, 0xc0000000);
+ nv_wr32(gr, 0x40584c, 0x00000001);
+ nv_wr32(gr, 0x404000, 0xc0000000);
+ nv_wr32(gr, 0x404600, 0xc0000000);
+ nv_wr32(gr, 0x408030, 0xc0000000);
+ nv_wr32(gr, 0x404490, 0xc0000000);
+ nv_wr32(gr, 0x406018, 0xc0000000);
+ nv_wr32(gr, 0x407020, 0x40000000);
+ nv_wr32(gr, 0x405840, 0xc0000000);
+ nv_wr32(gr, 0x405844, 0x00ffffff);
+ nv_mask(gr, 0x419cc0, 0x00000008, 0x00000008);
+
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++)
+ nv_wr32(gr, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000);
+ for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005);
}
- nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
- nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
}
- for (rop = 0; rop < priv->rop_nr; rop++) {
- nv_wr32(priv, ROP_UNIT(rop, 0x144), 0x40000000);
- nv_wr32(priv, ROP_UNIT(rop, 0x070), 0x40000000);
- nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
- nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
+ for (rop = 0; rop < gr->rop_nr; rop++) {
+ nv_wr32(gr, ROP_UNIT(rop, 0x144), 0x40000000);
+ nv_wr32(gr, ROP_UNIT(rop, 0x070), 0x40000000);
+ nv_wr32(gr, ROP_UNIT(rop, 0x204), 0xffffffff);
+ nv_wr32(gr, ROP_UNIT(rop, 0x208), 0xffffffff);
}
- nv_wr32(priv, 0x400108, 0xffffffff);
- nv_wr32(priv, 0x400138, 0xffffffff);
- nv_wr32(priv, 0x400118, 0xffffffff);
- nv_wr32(priv, 0x400130, 0xffffffff);
- nv_wr32(priv, 0x40011c, 0xffffffff);
- nv_wr32(priv, 0x400134, 0xffffffff);
+ nv_wr32(gr, 0x400108, 0xffffffff);
+ nv_wr32(gr, 0x400138, 0xffffffff);
+ nv_wr32(gr, 0x400118, 0xffffffff);
+ nv_wr32(gr, 0x400130, 0xffffffff);
+ nv_wr32(gr, 0x40011c, 0xffffffff);
+ nv_wr32(gr, 0x400134, 0xffffffff);
- nv_wr32(priv, 0x400054, 0x2c350f63);
+ nv_wr32(gr, 0x400054, 0x2c350f63);
- gf100_gr_zbc_init(priv);
+ gf100_gr_zbc_init(gr);
- return gm204_gr_init_ctxctl(priv);
+ return gm204_gr_init_ctxctl(gr);
}
struct nvkm_oclass *
};
static void
-gm20b_gr_init_gpc_mmu(struct gf100_gr_priv *priv)
+gm20b_gr_init_gpc_mmu(struct gf100_gr *gr)
{
u32 val;
/* TODO this needs to be removed once secure boot works */
if (1) {
- nv_wr32(priv, 0x100ce4, 0xffffffff);
+ nv_wr32(gr, 0x100ce4, 0xffffffff);
}
/* TODO update once secure boot works */
- val = nv_rd32(priv, 0x100c80);
+ val = nv_rd32(gr, 0x100c80);
val &= 0xf000087f;
- nv_wr32(priv, 0x418880, val);
- nv_wr32(priv, 0x418890, 0);
- nv_wr32(priv, 0x418894, 0);
+ nv_wr32(gr, 0x418880, val);
+ nv_wr32(gr, 0x418890, 0);
+ nv_wr32(gr, 0x418894, 0);
- nv_wr32(priv, 0x4188b0, nv_rd32(priv, 0x100cc4));
- nv_wr32(priv, 0x4188b4, nv_rd32(priv, 0x100cc8));
- nv_wr32(priv, 0x4188b8, nv_rd32(priv, 0x100ccc));
+ nv_wr32(gr, 0x4188b0, nv_rd32(gr, 0x100cc4));
+ nv_wr32(gr, 0x4188b4, nv_rd32(gr, 0x100cc8));
+ nv_wr32(gr, 0x4188b8, nv_rd32(gr, 0x100ccc));
- nv_wr32(priv, 0x4188ac, nv_rd32(priv, 0x100800));
+ nv_wr32(gr, 0x4188ac, nv_rd32(gr, 0x100800));
}
static void
-gm20b_gr_set_hww_esr_report_mask(struct gf100_gr_priv *priv)
+gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
{
- nv_wr32(priv, 0x419e44, 0xdffffe);
- nv_wr32(priv, 0x419e4c, 0x5);
+ nv_wr32(gr, 0x419e44, 0xdffffe);
+ nv_wr32(gr, 0x419e4c, 0x5);
}
struct nvkm_oclass *
NV04_PGRAPH_DEBUG_3
};
-struct nv04_gr_priv {
+struct nv04_gr {
struct nvkm_gr base;
struct nv04_gr_chan *chan[16];
spinlock_t lock;
};
-static inline struct nv04_gr_priv *
-nv04_gr_priv(struct nv04_gr_chan *chan)
+static inline struct nv04_gr *
+nv04_gr(struct nv04_gr_chan *chan)
{
return (void *)nv_object(chan)->engine;
}
static void
nv04_gr_set_ctx1(struct nvkm_object *object, u32 mask, u32 value)
{
- struct nv04_gr_priv *priv = (void *)object->engine;
- int subc = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7;
+ struct nv04_gr *gr = (void *)object->engine;
+ int subc = (nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7;
u32 tmp;
tmp = nv_ro32(object, 0x00);
tmp |= value;
nv_wo32(object, 0x00, tmp);
- nv_wr32(priv, NV04_PGRAPH_CTX_SWITCH1, tmp);
- nv_wr32(priv, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp);
+ nv_wr32(gr, NV04_PGRAPH_CTX_SWITCH1, tmp);
+ nv_wr32(gr, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp);
}
static void
nv04_gr_mthd_surf3d_clip_h(struct nvkm_object *object, u32 mthd,
void *args, u32 size)
{
- struct nv04_gr_priv *priv = (void *)object->engine;
+ struct nv04_gr *gr = (void *)object->engine;
u32 data = *(u32 *)args;
u32 min = data & 0xffff, max;
u32 w = data >> 16;
w |= 0xffff0000;
max = min + w;
max &= 0x3ffff;
- nv_wr32(priv, 0x40053c, min);
- nv_wr32(priv, 0x400544, max);
+ nv_wr32(gr, 0x40053c, min);
+ nv_wr32(gr, 0x400544, max);
return 0;
}
nv04_gr_mthd_surf3d_clip_v(struct nvkm_object *object, u32 mthd,
void *args, u32 size)
{
- struct nv04_gr_priv *priv = (void *)object->engine;
+ struct nv04_gr *gr = (void *)object->engine;
u32 data = *(u32 *)args;
u32 min = data & 0xffff, max;
u32 w = data >> 16;
w |= 0xffff0000;
max = min + w;
max &= 0x3ffff;
- nv_wr32(priv, 0x400540, min);
- nv_wr32(priv, 0x400548, max);
+ nv_wr32(gr, 0x400540, min);
+ nv_wr32(gr, 0x400548, max);
return 0;
}
******************************************************************************/
static struct nv04_gr_chan *
-nv04_gr_channel(struct nv04_gr_priv *priv)
+nv04_gr_channel(struct nv04_gr *gr)
{
struct nv04_gr_chan *chan = NULL;
- if (nv_rd32(priv, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) {
- int chid = nv_rd32(priv, NV04_PGRAPH_CTX_USER) >> 24;
- if (chid < ARRAY_SIZE(priv->chan))
- chan = priv->chan[chid];
+ if (nv_rd32(gr, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) {
+ int chid = nv_rd32(gr, NV04_PGRAPH_CTX_USER) >> 24;
+ if (chid < ARRAY_SIZE(gr->chan))
+ chan = gr->chan[chid];
}
return chan;
}
static int
nv04_gr_load_context(struct nv04_gr_chan *chan, int chid)
{
- struct nv04_gr_priv *priv = nv04_gr_priv(chan);
+ struct nv04_gr *gr = nv04_gr(chan);
int i;
for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++)
- nv_wr32(priv, nv04_gr_ctx_regs[i], chan->nv04[i]);
+ nv_wr32(gr, nv04_gr_ctx_regs[i], chan->nv04[i]);
- nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10010100);
- nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24);
- nv_mask(priv, NV04_PGRAPH_FFINTFC_ST2, 0xfff00000, 0x00000000);
+ nv_wr32(gr, NV04_PGRAPH_CTX_CONTROL, 0x10010100);
+ nv_mask(gr, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24);
+ nv_mask(gr, NV04_PGRAPH_FFINTFC_ST2, 0xfff00000, 0x00000000);
return 0;
}
static int
nv04_gr_unload_context(struct nv04_gr_chan *chan)
{
- struct nv04_gr_priv *priv = nv04_gr_priv(chan);
+ struct nv04_gr *gr = nv04_gr(chan);
int i;
for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++)
- chan->nv04[i] = nv_rd32(priv, nv04_gr_ctx_regs[i]);
+ chan->nv04[i] = nv_rd32(gr, nv04_gr_ctx_regs[i]);
- nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10000000);
- nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000);
+ nv_wr32(gr, NV04_PGRAPH_CTX_CONTROL, 0x10000000);
+ nv_mask(gr, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000);
return 0;
}
static void
-nv04_gr_context_switch(struct nv04_gr_priv *priv)
+nv04_gr_context_switch(struct nv04_gr *gr)
{
struct nv04_gr_chan *prev = NULL;
struct nv04_gr_chan *next = NULL;
unsigned long flags;
int chid;
- spin_lock_irqsave(&priv->lock, flags);
- nv04_gr_idle(priv);
+ spin_lock_irqsave(&gr->lock, flags);
+ nv04_gr_idle(gr);
/* If previous context is valid, we need to save it */
- prev = nv04_gr_channel(priv);
+ prev = nv04_gr_channel(gr);
if (prev)
nv04_gr_unload_context(prev);
/* load context for next channel */
- chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f;
- next = priv->chan[chid];
+ chid = (nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f;
+ next = gr->chan[chid];
if (next)
nv04_gr_load_context(next, chid);
- spin_unlock_irqrestore(&priv->lock, flags);
+ spin_unlock_irqrestore(&gr->lock, flags);
}
static u32 *ctx_reg(struct nv04_gr_chan *chan, u32 reg)
struct nvkm_object **pobject)
{
struct nvkm_fifo_chan *fifo = (void *)parent;
- struct nv04_gr_priv *priv = (void *)engine;
+ struct nv04_gr *gr = (void *)engine;
struct nv04_gr_chan *chan;
unsigned long flags;
int ret;
if (ret)
return ret;
- spin_lock_irqsave(&priv->lock, flags);
- if (priv->chan[fifo->chid]) {
- *pobject = nv_object(priv->chan[fifo->chid]);
+ spin_lock_irqsave(&gr->lock, flags);
+ if (gr->chan[fifo->chid]) {
+ *pobject = nv_object(gr->chan[fifo->chid]);
atomic_inc(&(*pobject)->refcount);
- spin_unlock_irqrestore(&priv->lock, flags);
+ spin_unlock_irqrestore(&gr->lock, flags);
nvkm_object_destroy(&chan->base);
return 1;
}
*ctx_reg(chan, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31;
- priv->chan[fifo->chid] = chan;
+ gr->chan[fifo->chid] = chan;
chan->chid = fifo->chid;
- spin_unlock_irqrestore(&priv->lock, flags);
+ spin_unlock_irqrestore(&gr->lock, flags);
return 0;
}
static void
nv04_gr_context_dtor(struct nvkm_object *object)
{
- struct nv04_gr_priv *priv = (void *)object->engine;
+ struct nv04_gr *gr = (void *)object->engine;
struct nv04_gr_chan *chan = (void *)object;
unsigned long flags;
- spin_lock_irqsave(&priv->lock, flags);
- priv->chan[chan->chid] = NULL;
- spin_unlock_irqrestore(&priv->lock, flags);
+ spin_lock_irqsave(&gr->lock, flags);
+ gr->chan[chan->chid] = NULL;
+ spin_unlock_irqrestore(&gr->lock, flags);
nvkm_object_destroy(&chan->base);
}
static int
nv04_gr_context_fini(struct nvkm_object *object, bool suspend)
{
- struct nv04_gr_priv *priv = (void *)object->engine;
+ struct nv04_gr *gr = (void *)object->engine;
struct nv04_gr_chan *chan = (void *)object;
unsigned long flags;
- spin_lock_irqsave(&priv->lock, flags);
- nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
- if (nv04_gr_channel(priv) == chan)
+ spin_lock_irqsave(&gr->lock, flags);
+ nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
+ if (nv04_gr_channel(gr) == chan)
nv04_gr_unload_context(chan);
- nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
- spin_unlock_irqrestore(&priv->lock, flags);
+ nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
+ spin_unlock_irqrestore(&gr->lock, flags);
return nvkm_object_fini(&chan->base, suspend);
}
static void
nv04_gr_intr(struct nvkm_subdev *subdev)
{
- struct nv04_gr_priv *priv = (void *)subdev;
+ struct nv04_gr *gr = (void *)subdev;
struct nv04_gr_chan *chan = NULL;
struct nvkm_namedb *namedb = NULL;
struct nvkm_handle *handle = NULL;
- u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
- u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
- u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
- u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
+ u32 stat = nv_rd32(gr, NV03_PGRAPH_INTR);
+ u32 nsource = nv_rd32(gr, NV03_PGRAPH_NSOURCE);
+ u32 nstatus = nv_rd32(gr, NV03_PGRAPH_NSTATUS);
+ u32 addr = nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR);
u32 chid = (addr & 0x0f000000) >> 24;
u32 subc = (addr & 0x0000e000) >> 13;
u32 mthd = (addr & 0x00001ffc);
- u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
- u32 class = nv_rd32(priv, 0x400180 + subc * 4) & 0xff;
- u32 inst = (nv_rd32(priv, 0x40016c) & 0xffff) << 4;
+ u32 data = nv_rd32(gr, NV04_PGRAPH_TRAPPED_DATA);
+ u32 class = nv_rd32(gr, 0x400180 + subc * 4) & 0xff;
+ u32 inst = (nv_rd32(gr, 0x40016c) & 0xffff) << 4;
u32 show = stat;
unsigned long flags;
- spin_lock_irqsave(&priv->lock, flags);
- chan = priv->chan[chid];
+ spin_lock_irqsave(&gr->lock, flags);
+ chan = gr->chan[chid];
if (chan)
namedb = (void *)nv_pclass(nv_object(chan), NV_NAMEDB_CLASS);
- spin_unlock_irqrestore(&priv->lock, flags);
+ spin_unlock_irqrestore(&gr->lock, flags);
if (stat & NV_PGRAPH_INTR_NOTIFY) {
if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) {
}
if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
- nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
+ nv_wr32(gr, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
- nv04_gr_context_switch(priv);
+ nv04_gr_context_switch(gr);
}
- nv_wr32(priv, NV03_PGRAPH_INTR, stat);
- nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
+ nv_wr32(gr, NV03_PGRAPH_INTR, stat);
+ nv_wr32(gr, NV04_PGRAPH_FIFO, 0x00000001);
if (show) {
- nv_error(priv, "%s", "");
+ nv_error(gr, "%s", "");
nvkm_bitfield_print(nv04_gr_intr_name, show);
pr_cont(" nsource:");
nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
nvkm_bitfield_print(nv04_gr_nstatus, nstatus);
pr_cont("\n");
- nv_error(priv,
+ nv_error(gr,
"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, nvkm_client_name(chan), subc, class, mthd,
data);
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
- struct nv04_gr_priv *priv;
+ struct nv04_gr *gr;
int ret;
- ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
- *pobject = nv_object(priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
+ *pobject = nv_object(gr);
if (ret)
return ret;
- nv_subdev(priv)->unit = 0x00001000;
- nv_subdev(priv)->intr = nv04_gr_intr;
- nv_engine(priv)->cclass = &nv04_gr_cclass;
- nv_engine(priv)->sclass = nv04_gr_sclass;
- spin_lock_init(&priv->lock);
+ nv_subdev(gr)->unit = 0x00001000;
+ nv_subdev(gr)->intr = nv04_gr_intr;
+ nv_engine(gr)->cclass = &nv04_gr_cclass;
+ nv_engine(gr)->sclass = nv04_gr_sclass;
+ spin_lock_init(&gr->lock);
return 0;
}
nv04_gr_init(struct nvkm_object *object)
{
struct nvkm_engine *engine = nv_engine(object);
- struct nv04_gr_priv *priv = (void *)engine;
+ struct nv04_gr *gr = (void *)engine;
int ret;
- ret = nvkm_gr_init(&priv->base);
+ ret = nvkm_gr_init(&gr->base);
if (ret)
return ret;
/* Enable PGRAPH interrupts */
- nv_wr32(priv, NV03_PGRAPH_INTR, 0xFFFFFFFF);
- nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
-
- nv_wr32(priv, NV04_PGRAPH_VALID1, 0);
- nv_wr32(priv, NV04_PGRAPH_VALID2, 0);
- /*nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x000001FF);
- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/
- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x1231c000);
+ nv_wr32(gr, NV03_PGRAPH_INTR, 0xFFFFFFFF);
+ nv_wr32(gr, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
+
+ nv_wr32(gr, NV04_PGRAPH_VALID1, 0);
+ nv_wr32(gr, NV04_PGRAPH_VALID2, 0);
+ /*nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x000001FF);
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x1231c000);
/*1231C000 blob, 001 haiku*/
/*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/
- nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x72111100);
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_1, 0x72111100);
/*0x72111100 blob , 01 haiku*/
- /*nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/
- nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x11d5f071);
+ /*nv_wr32(gr, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_2, 0x11d5f071);
/*haiku same*/
- /*nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/
- nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31);
+ /*nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31);
/*haiku and blob 10d4*/
- nv_wr32(priv, NV04_PGRAPH_STATE , 0xFFFFFFFF);
- nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL , 0x10000100);
- nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000);
+ nv_wr32(gr, NV04_PGRAPH_STATE , 0xFFFFFFFF);
+ nv_wr32(gr, NV04_PGRAPH_CTX_CONTROL , 0x10000100);
+ nv_mask(gr, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000);
/* These don't belong here, they're part of a per-channel context */
- nv_wr32(priv, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
- nv_wr32(priv, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF);
+ nv_wr32(gr, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
+ nv_wr32(gr, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF);
return 0;
}
0x00400a04,
};
-struct nv10_gr_priv {
+struct nv10_gr {
struct nvkm_gr base;
struct nv10_gr_chan *chan[32];
spinlock_t lock;
};
-static inline struct nv10_gr_priv *
-nv10_gr_priv(struct nv10_gr_chan *chan)
+static inline struct nv10_gr *
+nv10_gr(struct nv10_gr_chan *chan)
{
return (void *)nv_object(chan)->engine;
}
* Graphics object classes
******************************************************************************/
-#define PIPE_SAVE(priv, state, addr) \
+#define PIPE_SAVE(gr, state, addr) \
do { \
int __i; \
- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, addr); \
+ nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, addr); \
for (__i = 0; __i < ARRAY_SIZE(state); __i++) \
- state[__i] = nv_rd32(priv, NV10_PGRAPH_PIPE_DATA); \
+ state[__i] = nv_rd32(gr, NV10_PGRAPH_PIPE_DATA); \
} while (0)
-#define PIPE_RESTORE(priv, state, addr) \
+#define PIPE_RESTORE(gr, state, addr) \
do { \
int __i; \
- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, addr); \
+ nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, addr); \
for (__i = 0; __i < ARRAY_SIZE(state); __i++) \
- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, state[__i]); \
+ nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, state[__i]); \
} while (0)
static struct nvkm_oclass
void *args, u32 size)
{
struct nv10_gr_chan *chan = (void *)object->parent;
- struct nv10_gr_priv *priv = nv10_gr_priv(chan);
+ struct nv10_gr *gr = nv10_gr(chan);
struct pipe_state *pipe = &chan->pipe_state;
u32 pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3];
u32 xfmode0, xfmode1;
if (mthd != 0x1644)
return 0;
- nv04_gr_idle(priv);
+ nv04_gr_idle(gr);
- PIPE_SAVE(priv, pipe_0x0040, 0x0040);
- PIPE_SAVE(priv, pipe->pipe_0x0200, 0x0200);
+ PIPE_SAVE(gr, pipe_0x0040, 0x0040);
+ PIPE_SAVE(gr, pipe->pipe_0x0200, 0x0200);
- PIPE_RESTORE(priv, chan->lma_window, 0x6790);
+ PIPE_RESTORE(gr, chan->lma_window, 0x6790);
- nv04_gr_idle(priv);
+ nv04_gr_idle(gr);
- xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0);
- xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1);
+ xfmode0 = nv_rd32(gr, NV10_PGRAPH_XFMODE0);
+ xfmode1 = nv_rd32(gr, NV10_PGRAPH_XFMODE1);
- PIPE_SAVE(priv, pipe->pipe_0x4400, 0x4400);
- PIPE_SAVE(priv, pipe_0x64c0, 0x64c0);
- PIPE_SAVE(priv, pipe_0x6ab0, 0x6ab0);
- PIPE_SAVE(priv, pipe_0x6a80, 0x6a80);
+ PIPE_SAVE(gr, pipe->pipe_0x4400, 0x4400);
+ PIPE_SAVE(gr, pipe_0x64c0, 0x64c0);
+ PIPE_SAVE(gr, pipe_0x6ab0, 0x6ab0);
+ PIPE_SAVE(gr, pipe_0x6a80, 0x6a80);
- nv04_gr_idle(priv);
+ nv04_gr_idle(gr);
- nv_wr32(priv, NV10_PGRAPH_XFMODE0, 0x10000000);
- nv_wr32(priv, NV10_PGRAPH_XFMODE1, 0x00000000);
- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
+ nv_wr32(gr, NV10_PGRAPH_XFMODE0, 0x10000000);
+ nv_wr32(gr, NV10_PGRAPH_XFMODE1, 0x00000000);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
for (i = 0; i < 4; i++)
- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
for (i = 0; i < 4; i++)
- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000000);
- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
for (i = 0; i < 3; i++)
- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
for (i = 0; i < 3; i++)
- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000000);
- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000008);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000008);
- PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200);
+ PIPE_RESTORE(gr, pipe->pipe_0x0200, 0x0200);
- nv04_gr_idle(priv);
+ nv04_gr_idle(gr);
- PIPE_RESTORE(priv, pipe_0x0040, 0x0040);
+ PIPE_RESTORE(gr, pipe_0x0040, 0x0040);
- nv_wr32(priv, NV10_PGRAPH_XFMODE0, xfmode0);
- nv_wr32(priv, NV10_PGRAPH_XFMODE1, xfmode1);
+ nv_wr32(gr, NV10_PGRAPH_XFMODE0, xfmode0);
+ nv_wr32(gr, NV10_PGRAPH_XFMODE1, xfmode1);
- PIPE_RESTORE(priv, pipe_0x64c0, 0x64c0);
- PIPE_RESTORE(priv, pipe_0x6ab0, 0x6ab0);
- PIPE_RESTORE(priv, pipe_0x6a80, 0x6a80);
- PIPE_RESTORE(priv, pipe->pipe_0x4400, 0x4400);
+ PIPE_RESTORE(gr, pipe_0x64c0, 0x64c0);
+ PIPE_RESTORE(gr, pipe_0x6ab0, 0x6ab0);
+ PIPE_RESTORE(gr, pipe_0x6a80, 0x6a80);
+ PIPE_RESTORE(gr, pipe->pipe_0x4400, 0x4400);
- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0);
- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000000);
- nv04_gr_idle(priv);
+ nv04_gr_idle(gr);
return 0;
}
void *args, u32 size)
{
struct nv10_gr_chan *chan = (void *)object->parent;
- struct nv10_gr_priv *priv = nv10_gr_priv(chan);
+ struct nv10_gr *gr = nv10_gr(chan);
- nv04_gr_idle(priv);
+ nv04_gr_idle(gr);
- nv_mask(priv, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100);
- nv_mask(priv, 0x4006b0, 0x08000000, 0x08000000);
+ nv_mask(gr, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100);
+ nv_mask(gr, 0x4006b0, 0x08000000, 0x08000000);
return 0;
}
******************************************************************************/
static struct nv10_gr_chan *
-nv10_gr_channel(struct nv10_gr_priv *priv)
+nv10_gr_channel(struct nv10_gr *gr)
{
struct nv10_gr_chan *chan = NULL;
- if (nv_rd32(priv, 0x400144) & 0x00010000) {
- int chid = nv_rd32(priv, 0x400148) >> 24;
- if (chid < ARRAY_SIZE(priv->chan))
- chan = priv->chan[chid];
+ if (nv_rd32(gr, 0x400144) & 0x00010000) {
+ int chid = nv_rd32(gr, 0x400148) >> 24;
+ if (chid < ARRAY_SIZE(gr->chan))
+ chan = gr->chan[chid];
}
return chan;
}
static void
nv10_gr_save_pipe(struct nv10_gr_chan *chan)
{
- struct nv10_gr_priv *priv = nv10_gr_priv(chan);
+ struct nv10_gr *gr = nv10_gr(chan);
struct pipe_state *pipe = &chan->pipe_state;
- PIPE_SAVE(priv, pipe->pipe_0x4400, 0x4400);
- PIPE_SAVE(priv, pipe->pipe_0x0200, 0x0200);
- PIPE_SAVE(priv, pipe->pipe_0x6400, 0x6400);
- PIPE_SAVE(priv, pipe->pipe_0x6800, 0x6800);
- PIPE_SAVE(priv, pipe->pipe_0x6c00, 0x6c00);
- PIPE_SAVE(priv, pipe->pipe_0x7000, 0x7000);
- PIPE_SAVE(priv, pipe->pipe_0x7400, 0x7400);
- PIPE_SAVE(priv, pipe->pipe_0x7800, 0x7800);
- PIPE_SAVE(priv, pipe->pipe_0x0040, 0x0040);
- PIPE_SAVE(priv, pipe->pipe_0x0000, 0x0000);
+ PIPE_SAVE(gr, pipe->pipe_0x4400, 0x4400);
+ PIPE_SAVE(gr, pipe->pipe_0x0200, 0x0200);
+ PIPE_SAVE(gr, pipe->pipe_0x6400, 0x6400);
+ PIPE_SAVE(gr, pipe->pipe_0x6800, 0x6800);
+ PIPE_SAVE(gr, pipe->pipe_0x6c00, 0x6c00);
+ PIPE_SAVE(gr, pipe->pipe_0x7000, 0x7000);
+ PIPE_SAVE(gr, pipe->pipe_0x7400, 0x7400);
+ PIPE_SAVE(gr, pipe->pipe_0x7800, 0x7800);
+ PIPE_SAVE(gr, pipe->pipe_0x0040, 0x0040);
+ PIPE_SAVE(gr, pipe->pipe_0x0000, 0x0000);
}
static void
nv10_gr_load_pipe(struct nv10_gr_chan *chan)
{
- struct nv10_gr_priv *priv = nv10_gr_priv(chan);
+ struct nv10_gr *gr = nv10_gr(chan);
struct pipe_state *pipe = &chan->pipe_state;
u32 xfmode0, xfmode1;
int i;
- nv04_gr_idle(priv);
+ nv04_gr_idle(gr);
/* XXX check haiku comments */
- xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0);
- xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1);
- nv_wr32(priv, NV10_PGRAPH_XFMODE0, 0x10000000);
- nv_wr32(priv, NV10_PGRAPH_XFMODE1, 0x00000000);
- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
+ xfmode0 = nv_rd32(gr, NV10_PGRAPH_XFMODE0);
+ xfmode1 = nv_rd32(gr, NV10_PGRAPH_XFMODE1);
+ nv_wr32(gr, NV10_PGRAPH_XFMODE0, 0x10000000);
+ nv_wr32(gr, NV10_PGRAPH_XFMODE1, 0x00000000);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
for (i = 0; i < 4; i++)
- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
for (i = 0; i < 4; i++)
- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000000);
- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
for (i = 0; i < 3; i++)
- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
for (i = 0; i < 3; i++)
- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000000);
- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000008);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
+ nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000008);
- PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200);
- nv04_gr_idle(priv);
+ PIPE_RESTORE(gr, pipe->pipe_0x0200, 0x0200);
+ nv04_gr_idle(gr);
/* restore XFMODE */
- nv_wr32(priv, NV10_PGRAPH_XFMODE0, xfmode0);
- nv_wr32(priv, NV10_PGRAPH_XFMODE1, xfmode1);
- PIPE_RESTORE(priv, pipe->pipe_0x6400, 0x6400);
- PIPE_RESTORE(priv, pipe->pipe_0x6800, 0x6800);
- PIPE_RESTORE(priv, pipe->pipe_0x6c00, 0x6c00);
- PIPE_RESTORE(priv, pipe->pipe_0x7000, 0x7000);
- PIPE_RESTORE(priv, pipe->pipe_0x7400, 0x7400);
- PIPE_RESTORE(priv, pipe->pipe_0x7800, 0x7800);
- PIPE_RESTORE(priv, pipe->pipe_0x4400, 0x4400);
- PIPE_RESTORE(priv, pipe->pipe_0x0000, 0x0000);
- PIPE_RESTORE(priv, pipe->pipe_0x0040, 0x0040);
- nv04_gr_idle(priv);
+ nv_wr32(gr, NV10_PGRAPH_XFMODE0, xfmode0);
+ nv_wr32(gr, NV10_PGRAPH_XFMODE1, xfmode1);
+ PIPE_RESTORE(gr, pipe->pipe_0x6400, 0x6400);
+ PIPE_RESTORE(gr, pipe->pipe_0x6800, 0x6800);
+ PIPE_RESTORE(gr, pipe->pipe_0x6c00, 0x6c00);
+ PIPE_RESTORE(gr, pipe->pipe_0x7000, 0x7000);
+ PIPE_RESTORE(gr, pipe->pipe_0x7400, 0x7400);
+ PIPE_RESTORE(gr, pipe->pipe_0x7800, 0x7800);
+ PIPE_RESTORE(gr, pipe->pipe_0x4400, 0x4400);
+ PIPE_RESTORE(gr, pipe->pipe_0x0000, 0x0000);
+ PIPE_RESTORE(gr, pipe->pipe_0x0040, 0x0040);
+ nv04_gr_idle(gr);
}
static void
nv10_gr_create_pipe(struct nv10_gr_chan *chan)
{
- struct nv10_gr_priv *priv = nv10_gr_priv(chan);
+ struct nv10_gr *gr = nv10_gr(chan);
struct pipe_state *pipe_state = &chan->pipe_state;
u32 *pipe_state_addr;
int i;
u32 *__end_addr = pipe_state->pipe_##addr + \
ARRAY_SIZE(pipe_state->pipe_##addr); \
if (pipe_state_addr != __end_addr) \
- nv_error(priv, "incomplete pipe init for 0x%x : %p/%p\n", \
+ nv_error(gr, "incomplete pipe init for 0x%x : %p/%p\n", \
addr, pipe_state_addr, __end_addr); \
} while (0)
#define NV_WRITE_PIPE_INIT(value) *(pipe_state_addr++) = value
}
static int
-nv10_gr_ctx_regs_find_offset(struct nv10_gr_priv *priv, int reg)
+nv10_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) {
if (nv10_gr_ctx_regs[i] == reg)
return i;
}
- nv_error(priv, "unknow offset nv10_ctx_regs %d\n", reg);
+ nv_error(gr, "unknow offset nv10_ctx_regs %d\n", reg);
return -1;
}
static int
-nv17_gr_ctx_regs_find_offset(struct nv10_gr_priv *priv, int reg)
+nv17_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) {
if (nv17_gr_ctx_regs[i] == reg)
return i;
}
- nv_error(priv, "unknow offset nv17_ctx_regs %d\n", reg);
+ nv_error(gr, "unknow offset nv17_ctx_regs %d\n", reg);
return -1;
}
static void
nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst)
{
- struct nv10_gr_priv *priv = nv10_gr_priv(chan);
+ struct nv10_gr *gr = nv10_gr(chan);
u32 st2, st2_dl, st2_dh, fifo_ptr, fifo[0x60/4];
u32 ctx_user, ctx_switch[5];
int i, subchan = -1;
/* Look for a celsius object */
for (i = 0; i < 8; i++) {
- int class = nv_rd32(priv, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff;
+ int class = nv_rd32(gr, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff;
if (class == 0x56 || class == 0x96 || class == 0x99) {
subchan = i;
return;
/* Save the current ctx object */
- ctx_user = nv_rd32(priv, NV10_PGRAPH_CTX_USER);
+ ctx_user = nv_rd32(gr, NV10_PGRAPH_CTX_USER);
for (i = 0; i < 5; i++)
- ctx_switch[i] = nv_rd32(priv, NV10_PGRAPH_CTX_SWITCH(i));
+ ctx_switch[i] = nv_rd32(gr, NV10_PGRAPH_CTX_SWITCH(i));
/* Save the FIFO state */
- st2 = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2);
- st2_dl = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2_DL);
- st2_dh = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2_DH);
- fifo_ptr = nv_rd32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR);
+ st2 = nv_rd32(gr, NV10_PGRAPH_FFINTFC_ST2);
+ st2_dl = nv_rd32(gr, NV10_PGRAPH_FFINTFC_ST2_DL);
+ st2_dh = nv_rd32(gr, NV10_PGRAPH_FFINTFC_ST2_DH);
+ fifo_ptr = nv_rd32(gr, NV10_PGRAPH_FFINTFC_FIFO_PTR);
for (i = 0; i < ARRAY_SIZE(fifo); i++)
- fifo[i] = nv_rd32(priv, 0x4007a0 + 4 * i);
+ fifo[i] = nv_rd32(gr, 0x4007a0 + 4 * i);
/* Switch to the celsius subchannel */
for (i = 0; i < 5; i++)
- nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(i),
- nv_rd32(priv, NV10_PGRAPH_CTX_CACHE(subchan, i)));
- nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xe000, subchan << 13);
+ nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(i),
+ nv_rd32(gr, NV10_PGRAPH_CTX_CACHE(subchan, i)));
+ nv_mask(gr, NV10_PGRAPH_CTX_USER, 0xe000, subchan << 13);
/* Inject NV10TCL_DMA_VTXBUF */
- nv_wr32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR, 0);
- nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2,
+ nv_wr32(gr, NV10_PGRAPH_FFINTFC_FIFO_PTR, 0);
+ nv_wr32(gr, NV10_PGRAPH_FFINTFC_ST2,
0x2c000000 | chid << 20 | subchan << 16 | 0x18c);
- nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DL, inst);
- nv_mask(priv, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000);
- nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
- nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
+ nv_wr32(gr, NV10_PGRAPH_FFINTFC_ST2_DL, inst);
+ nv_mask(gr, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000);
+ nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
+ nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
/* Restore the FIFO state */
for (i = 0; i < ARRAY_SIZE(fifo); i++)
- nv_wr32(priv, 0x4007a0 + 4 * i, fifo[i]);
+ nv_wr32(gr, 0x4007a0 + 4 * i, fifo[i]);
- nv_wr32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR, fifo_ptr);
- nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2, st2);
- nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DL, st2_dl);
- nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DH, st2_dh);
+ nv_wr32(gr, NV10_PGRAPH_FFINTFC_FIFO_PTR, fifo_ptr);
+ nv_wr32(gr, NV10_PGRAPH_FFINTFC_ST2, st2);
+ nv_wr32(gr, NV10_PGRAPH_FFINTFC_ST2_DL, st2_dl);
+ nv_wr32(gr, NV10_PGRAPH_FFINTFC_ST2_DH, st2_dh);
/* Restore the current ctx object */
for (i = 0; i < 5; i++)
- nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(i), ctx_switch[i]);
- nv_wr32(priv, NV10_PGRAPH_CTX_USER, ctx_user);
+ nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(i), ctx_switch[i]);
+ nv_wr32(gr, NV10_PGRAPH_CTX_USER, ctx_user);
}
static int
nv10_gr_load_context(struct nv10_gr_chan *chan, int chid)
{
- struct nv10_gr_priv *priv = nv10_gr_priv(chan);
+ struct nv10_gr *gr = nv10_gr(chan);
u32 inst;
int i;
for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++)
- nv_wr32(priv, nv10_gr_ctx_regs[i], chan->nv10[i]);
+ nv_wr32(gr, nv10_gr_ctx_regs[i], chan->nv10[i]);
- if (nv_device(priv)->card_type >= NV_11 &&
- nv_device(priv)->chipset >= 0x17) {
+ if (nv_device(gr)->card_type >= NV_11 &&
+ nv_device(gr)->chipset >= 0x17) {
for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++)
- nv_wr32(priv, nv17_gr_ctx_regs[i], chan->nv17[i]);
+ nv_wr32(gr, nv17_gr_ctx_regs[i], chan->nv17[i]);
}
nv10_gr_load_pipe(chan);
- inst = nv_rd32(priv, NV10_PGRAPH_GLOBALSTATE1) & 0xffff;
+ inst = nv_rd32(gr, NV10_PGRAPH_GLOBALSTATE1) & 0xffff;
nv10_gr_load_dma_vtxbuf(chan, chid, inst);
- nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
- nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24);
- nv_mask(priv, NV10_PGRAPH_FFINTFC_ST2, 0x30000000, 0x00000000);
+ nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
+ nv_mask(gr, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24);
+ nv_mask(gr, NV10_PGRAPH_FFINTFC_ST2, 0x30000000, 0x00000000);
return 0;
}
static int
nv10_gr_unload_context(struct nv10_gr_chan *chan)
{
- struct nv10_gr_priv *priv = nv10_gr_priv(chan);
+ struct nv10_gr *gr = nv10_gr(chan);
int i;
for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++)
- chan->nv10[i] = nv_rd32(priv, nv10_gr_ctx_regs[i]);
+ chan->nv10[i] = nv_rd32(gr, nv10_gr_ctx_regs[i]);
- if (nv_device(priv)->card_type >= NV_11 &&
- nv_device(priv)->chipset >= 0x17) {
+ if (nv_device(gr)->card_type >= NV_11 &&
+ nv_device(gr)->chipset >= 0x17) {
for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++)
- chan->nv17[i] = nv_rd32(priv, nv17_gr_ctx_regs[i]);
+ chan->nv17[i] = nv_rd32(gr, nv17_gr_ctx_regs[i]);
}
nv10_gr_save_pipe(chan);
- nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000000);
- nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000);
+ nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10000000);
+ nv_mask(gr, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000);
return 0;
}
static void
-nv10_gr_context_switch(struct nv10_gr_priv *priv)
+nv10_gr_context_switch(struct nv10_gr *gr)
{
struct nv10_gr_chan *prev = NULL;
struct nv10_gr_chan *next = NULL;
unsigned long flags;
int chid;
- spin_lock_irqsave(&priv->lock, flags);
- nv04_gr_idle(priv);
+ spin_lock_irqsave(&gr->lock, flags);
+ nv04_gr_idle(gr);
/* If previous context is valid, we need to save it */
- prev = nv10_gr_channel(priv);
+ prev = nv10_gr_channel(gr);
if (prev)
nv10_gr_unload_context(prev);
/* load context for next channel */
- chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
- next = priv->chan[chid];
+ chid = (nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
+ next = gr->chan[chid];
if (next)
nv10_gr_load_context(next, chid);
- spin_unlock_irqrestore(&priv->lock, flags);
+ spin_unlock_irqrestore(&gr->lock, flags);
}
#define NV_WRITE_CTX(reg, val) do { \
- int offset = nv10_gr_ctx_regs_find_offset(priv, reg); \
+ int offset = nv10_gr_ctx_regs_find_offset(gr, reg); \
if (offset > 0) \
chan->nv10[offset] = val; \
} while (0)
#define NV17_WRITE_CTX(reg, val) do { \
- int offset = nv17_gr_ctx_regs_find_offset(priv, reg); \
+ int offset = nv17_gr_ctx_regs_find_offset(gr, reg); \
if (offset > 0) \
chan->nv17[offset] = val; \
} while (0)
struct nvkm_object **pobject)
{
struct nvkm_fifo_chan *fifo = (void *)parent;
- struct nv10_gr_priv *priv = (void *)engine;
+ struct nv10_gr *gr = (void *)engine;
struct nv10_gr_chan *chan;
unsigned long flags;
int ret;
if (ret)
return ret;
- spin_lock_irqsave(&priv->lock, flags);
- if (priv->chan[fifo->chid]) {
- *pobject = nv_object(priv->chan[fifo->chid]);
+ spin_lock_irqsave(&gr->lock, flags);
+ if (gr->chan[fifo->chid]) {
+ *pobject = nv_object(gr->chan[fifo->chid]);
atomic_inc(&(*pobject)->refcount);
- spin_unlock_irqrestore(&priv->lock, flags);
+ spin_unlock_irqrestore(&gr->lock, flags);
nvkm_object_destroy(&chan->base);
return 1;
}
NV_WRITE_CTX(0x00400e14, 0x00001000);
NV_WRITE_CTX(0x00400e30, 0x00080008);
NV_WRITE_CTX(0x00400e34, 0x00080008);
- if (nv_device(priv)->card_type >= NV_11 &&
- nv_device(priv)->chipset >= 0x17) {
+ if (nv_device(gr)->card_type >= NV_11 &&
+ nv_device(gr)->chipset >= 0x17) {
/* is it really needed ??? */
NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4,
- nv_rd32(priv, NV10_PGRAPH_DEBUG_4));
- NV17_WRITE_CTX(0x004006b0, nv_rd32(priv, 0x004006b0));
+ nv_rd32(gr, NV10_PGRAPH_DEBUG_4));
+ NV17_WRITE_CTX(0x004006b0, nv_rd32(gr, 0x004006b0));
NV17_WRITE_CTX(0x00400eac, 0x0fff0000);
NV17_WRITE_CTX(0x00400eb0, 0x0fff0000);
NV17_WRITE_CTX(0x00400ec0, 0x00000080);
nv10_gr_create_pipe(chan);
- priv->chan[fifo->chid] = chan;
+ gr->chan[fifo->chid] = chan;
chan->chid = fifo->chid;
- spin_unlock_irqrestore(&priv->lock, flags);
+ spin_unlock_irqrestore(&gr->lock, flags);
return 0;
}
static void
nv10_gr_context_dtor(struct nvkm_object *object)
{
- struct nv10_gr_priv *priv = (void *)object->engine;
+ struct nv10_gr *gr = (void *)object->engine;
struct nv10_gr_chan *chan = (void *)object;
unsigned long flags;
- spin_lock_irqsave(&priv->lock, flags);
- priv->chan[chan->chid] = NULL;
- spin_unlock_irqrestore(&priv->lock, flags);
+ spin_lock_irqsave(&gr->lock, flags);
+ gr->chan[chan->chid] = NULL;
+ spin_unlock_irqrestore(&gr->lock, flags);
nvkm_object_destroy(&chan->base);
}
static int
nv10_gr_context_fini(struct nvkm_object *object, bool suspend)
{
- struct nv10_gr_priv *priv = (void *)object->engine;
+ struct nv10_gr *gr = (void *)object->engine;
struct nv10_gr_chan *chan = (void *)object;
unsigned long flags;
- spin_lock_irqsave(&priv->lock, flags);
- nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
- if (nv10_gr_channel(priv) == chan)
+ spin_lock_irqsave(&gr->lock, flags);
+ nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
+ if (nv10_gr_channel(gr) == chan)
nv10_gr_unload_context(chan);
- nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
- spin_unlock_irqrestore(&priv->lock, flags);
+ nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
+ spin_unlock_irqrestore(&gr->lock, flags);
return nvkm_object_fini(&chan->base, suspend);
}
{
struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i];
struct nvkm_fifo *fifo = nvkm_fifo(engine);
- struct nv10_gr_priv *priv = (void *)engine;
+ struct nv10_gr *gr = (void *)engine;
unsigned long flags;
fifo->pause(fifo, &flags);
- nv04_gr_idle(priv);
+ nv04_gr_idle(gr);
- nv_wr32(priv, NV10_PGRAPH_TLIMIT(i), tile->limit);
- nv_wr32(priv, NV10_PGRAPH_TSIZE(i), tile->pitch);
- nv_wr32(priv, NV10_PGRAPH_TILE(i), tile->addr);
+ nv_wr32(gr, NV10_PGRAPH_TLIMIT(i), tile->limit);
+ nv_wr32(gr, NV10_PGRAPH_TSIZE(i), tile->pitch);
+ nv_wr32(gr, NV10_PGRAPH_TILE(i), tile->addr);
fifo->start(fifo, &flags);
}
static void
nv10_gr_intr(struct nvkm_subdev *subdev)
{
- struct nv10_gr_priv *priv = (void *)subdev;
+ struct nv10_gr *gr = (void *)subdev;
struct nv10_gr_chan *chan = NULL;
struct nvkm_namedb *namedb = NULL;
struct nvkm_handle *handle = NULL;
- u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
- u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
- u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
- u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
+ u32 stat = nv_rd32(gr, NV03_PGRAPH_INTR);
+ u32 nsource = nv_rd32(gr, NV03_PGRAPH_NSOURCE);
+ u32 nstatus = nv_rd32(gr, NV03_PGRAPH_NSTATUS);
+ u32 addr = nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR);
u32 chid = (addr & 0x01f00000) >> 20;
u32 subc = (addr & 0x00070000) >> 16;
u32 mthd = (addr & 0x00001ffc);
- u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
- u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff;
+ u32 data = nv_rd32(gr, NV04_PGRAPH_TRAPPED_DATA);
+ u32 class = nv_rd32(gr, 0x400160 + subc * 4) & 0xfff;
u32 show = stat;
unsigned long flags;
- spin_lock_irqsave(&priv->lock, flags);
- chan = priv->chan[chid];
+ spin_lock_irqsave(&gr->lock, flags);
+ chan = gr->chan[chid];
if (chan)
namedb = (void *)nv_pclass(nv_object(chan), NV_NAMEDB_CLASS);
- spin_unlock_irqrestore(&priv->lock, flags);
+ spin_unlock_irqrestore(&gr->lock, flags);
if (stat & NV_PGRAPH_INTR_ERROR) {
if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) {
}
if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
- nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
+ nv_wr32(gr, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
- nv10_gr_context_switch(priv);
+ nv10_gr_context_switch(gr);
}
- nv_wr32(priv, NV03_PGRAPH_INTR, stat);
- nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
+ nv_wr32(gr, NV03_PGRAPH_INTR, stat);
+ nv_wr32(gr, NV04_PGRAPH_FIFO, 0x00000001);
if (show) {
- nv_error(priv, "%s", "");
+ nv_error(gr, "%s", "");
nvkm_bitfield_print(nv10_gr_intr_name, show);
pr_cont(" nsource:");
nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
pr_cont("\n");
- nv_error(priv,
+ nv_error(gr,
"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, nvkm_client_name(chan), subc, class, mthd,
data);
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
- struct nv10_gr_priv *priv;
+ struct nv10_gr *gr;
int ret;
- ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
- *pobject = nv_object(priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
+ *pobject = nv_object(gr);
if (ret)
return ret;
- nv_subdev(priv)->unit = 0x00001000;
- nv_subdev(priv)->intr = nv10_gr_intr;
- nv_engine(priv)->cclass = &nv10_gr_cclass;
+ nv_subdev(gr)->unit = 0x00001000;
+ nv_subdev(gr)->intr = nv10_gr_intr;
+ nv_engine(gr)->cclass = &nv10_gr_cclass;
- if (nv_device(priv)->chipset <= 0x10)
- nv_engine(priv)->sclass = nv10_gr_sclass;
+ if (nv_device(gr)->chipset <= 0x10)
+ nv_engine(gr)->sclass = nv10_gr_sclass;
else
- if (nv_device(priv)->chipset < 0x17 ||
- nv_device(priv)->card_type < NV_11)
- nv_engine(priv)->sclass = nv15_gr_sclass;
+ if (nv_device(gr)->chipset < 0x17 ||
+ nv_device(gr)->card_type < NV_11)
+ nv_engine(gr)->sclass = nv15_gr_sclass;
else
- nv_engine(priv)->sclass = nv17_gr_sclass;
+ nv_engine(gr)->sclass = nv17_gr_sclass;
- nv_engine(priv)->tile_prog = nv10_gr_tile_prog;
- spin_lock_init(&priv->lock);
+ nv_engine(gr)->tile_prog = nv10_gr_tile_prog;
+ spin_lock_init(&gr->lock);
return 0;
}
static void
nv10_gr_dtor(struct nvkm_object *object)
{
- struct nv10_gr_priv *priv = (void *)object;
- nvkm_gr_destroy(&priv->base);
+ struct nv10_gr *gr = (void *)object;
+ nvkm_gr_destroy(&gr->base);
}
static int
{
struct nvkm_engine *engine = nv_engine(object);
struct nvkm_fb *fb = nvkm_fb(object);
- struct nv10_gr_priv *priv = (void *)engine;
+ struct nv10_gr *gr = (void *)engine;
int ret, i;
- ret = nvkm_gr_init(&priv->base);
+ ret = nvkm_gr_init(&gr->base);
if (ret)
return ret;
- nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF);
- nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
-
- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
- nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700);
- /* nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x24E00810); */ /* 0x25f92ad9 */
- nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x25f92ad9);
- nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1 << 29) | (1 << 31));
-
- if (nv_device(priv)->card_type >= NV_11 &&
- nv_device(priv)->chipset >= 0x17) {
- nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x1f000000);
- nv_wr32(priv, 0x400a10, 0x03ff3fb6);
- nv_wr32(priv, 0x400838, 0x002f8684);
- nv_wr32(priv, 0x40083c, 0x00115f3f);
- nv_wr32(priv, 0x4006b0, 0x40000020);
+ nv_wr32(gr, NV03_PGRAPH_INTR , 0xFFFFFFFF);
+ nv_wr32(gr, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
+
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x00000000);
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_1, 0x00118700);
+ /* nv_wr32(gr, NV04_PGRAPH_DEBUG_2, 0x24E00810); */ /* 0x25f92ad9 */
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_2, 0x25f92ad9);
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1 << 29) | (1 << 31));
+
+ if (nv_device(gr)->card_type >= NV_11 &&
+ nv_device(gr)->chipset >= 0x17) {
+ nv_wr32(gr, NV10_PGRAPH_DEBUG_4, 0x1f000000);
+ nv_wr32(gr, 0x400a10, 0x03ff3fb6);
+ nv_wr32(gr, 0x400838, 0x002f8684);
+ nv_wr32(gr, 0x40083c, 0x00115f3f);
+ nv_wr32(gr, 0x4006b0, 0x40000020);
} else {
- nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000);
+ nv_wr32(gr, NV10_PGRAPH_DEBUG_4, 0x00000000);
}
/* Turn all the tiling regions off. */
for (i = 0; i < fb->tile.regions; i++)
engine->tile_prog(engine, i);
- nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000);
- nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000);
- nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000);
- nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(3), 0x00000000);
- nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(4), 0x00000000);
- nv_wr32(priv, NV10_PGRAPH_STATE, 0xFFFFFFFF);
+ nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000);
+ nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000);
+ nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000);
+ nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(3), 0x00000000);
+ nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(4), 0x00000000);
+ nv_wr32(gr, NV10_PGRAPH_STATE, 0xFFFFFFFF);
- nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000);
- nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
- nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2, 0x08000000);
+ nv_mask(gr, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000);
+ nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
+ nv_wr32(gr, NV10_PGRAPH_FFINTFC_ST2, 0x08000000);
return 0;
}
static int
nv10_gr_fini(struct nvkm_object *object, bool suspend)
{
- struct nv10_gr_priv *priv = (void *)object;
- return nvkm_gr_fini(&priv->base, suspend);
+ struct nv10_gr *gr = (void *)object;
+ return nvkm_gr_fini(&gr->base, suspend);
}
struct nvkm_oclass
int
nv20_gr_context_init(struct nvkm_object *object)
{
- struct nv20_gr_priv *priv = (void *)object->engine;
+ struct nv20_gr *gr = (void *)object->engine;
struct nv20_gr_chan *chan = (void *)object;
int ret;
if (ret)
return ret;
- nv_wo32(priv->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4);
+ nv_wo32(gr->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4);
return 0;
}
int
nv20_gr_context_fini(struct nvkm_object *object, bool suspend)
{
- struct nv20_gr_priv *priv = (void *)object->engine;
+ struct nv20_gr *gr = (void *)object->engine;
struct nv20_gr_chan *chan = (void *)object;
int chid = -1;
- nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
- if (nv_rd32(priv, 0x400144) & 0x00010000)
- chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24;
+ nv_mask(gr, 0x400720, 0x00000001, 0x00000000);
+ if (nv_rd32(gr, 0x400144) & 0x00010000)
+ chid = (nv_rd32(gr, 0x400148) & 0x1f000000) >> 24;
if (chan->chid == chid) {
- nv_wr32(priv, 0x400784, nv_gpuobj(chan)->addr >> 4);
- nv_wr32(priv, 0x400788, 0x00000002);
- nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
- nv_wr32(priv, 0x400144, 0x10000000);
- nv_mask(priv, 0x400148, 0xff000000, 0x1f000000);
+ nv_wr32(gr, 0x400784, nv_gpuobj(chan)->addr >> 4);
+ nv_wr32(gr, 0x400788, 0x00000002);
+ nv_wait(gr, 0x400700, 0xffffffff, 0x00000000);
+ nv_wr32(gr, 0x400144, 0x10000000);
+ nv_mask(gr, 0x400148, 0xff000000, 0x1f000000);
}
- nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
+ nv_mask(gr, 0x400720, 0x00000001, 0x00000001);
- nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000);
+ nv_wo32(gr->ctxtab, chan->chid * 4, 0x00000000);
return nvkm_gr_context_fini(&chan->base, suspend);
}
{
struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i];
struct nvkm_fifo *fifo = nvkm_fifo(engine);
- struct nv20_gr_priv *priv = (void *)engine;
+ struct nv20_gr *gr = (void *)engine;
unsigned long flags;
fifo->pause(fifo, &flags);
- nv04_gr_idle(priv);
+ nv04_gr_idle(gr);
- nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
- nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
- nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
+ nv_wr32(gr, NV20_PGRAPH_TLIMIT(i), tile->limit);
+ nv_wr32(gr, NV20_PGRAPH_TSIZE(i), tile->pitch);
+ nv_wr32(gr, NV20_PGRAPH_TILE(i), tile->addr);
- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
- nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->limit);
- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
- nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->pitch);
- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
- nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->addr);
+ nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
+ nv_wr32(gr, NV10_PGRAPH_RDI_DATA, tile->limit);
+ nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
+ nv_wr32(gr, NV10_PGRAPH_RDI_DATA, tile->pitch);
+ nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
+ nv_wr32(gr, NV10_PGRAPH_RDI_DATA, tile->addr);
if (nv_device(engine)->chipset != 0x34) {
- nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
- nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp);
+ nv_wr32(gr, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
+ nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
+ nv_wr32(gr, NV10_PGRAPH_RDI_DATA, tile->zcomp);
}
fifo->start(fifo, &flags);
struct nvkm_engine *engine = nv_engine(subdev);
struct nvkm_object *engctx;
struct nvkm_handle *handle;
- struct nv20_gr_priv *priv = (void *)subdev;
- u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
- u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
- u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
- u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
+ struct nv20_gr *gr = (void *)subdev;
+ u32 stat = nv_rd32(gr, NV03_PGRAPH_INTR);
+ u32 nsource = nv_rd32(gr, NV03_PGRAPH_NSOURCE);
+ u32 nstatus = nv_rd32(gr, NV03_PGRAPH_NSTATUS);
+ u32 addr = nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR);
u32 chid = (addr & 0x01f00000) >> 20;
u32 subc = (addr & 0x00070000) >> 16;
u32 mthd = (addr & 0x00001ffc);
- u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
- u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff;
+ u32 data = nv_rd32(gr, NV04_PGRAPH_TRAPPED_DATA);
+ u32 class = nv_rd32(gr, 0x400160 + subc * 4) & 0xfff;
u32 show = stat;
engctx = nvkm_engctx_get(engine, chid);
}
}
- nv_wr32(priv, NV03_PGRAPH_INTR, stat);
- nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
+ nv_wr32(gr, NV03_PGRAPH_INTR, stat);
+ nv_wr32(gr, NV04_PGRAPH_FIFO, 0x00000001);
if (show) {
- nv_error(priv, "%s", "");
+ nv_error(gr, "%s", "");
nvkm_bitfield_print(nv10_gr_intr_name, show);
pr_cont(" nsource:");
nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
pr_cont("\n");
- nv_error(priv,
+ nv_error(gr,
"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, nvkm_client_name(engctx), subc, class, mthd,
data);
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
- struct nv20_gr_priv *priv;
+ struct nv20_gr *gr;
int ret;
- ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
- *pobject = nv_object(priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
+ *pobject = nv_object(gr);
if (ret)
return ret;
- ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
+ ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab);
if (ret)
return ret;
- nv_subdev(priv)->unit = 0x00001000;
- nv_subdev(priv)->intr = nv20_gr_intr;
- nv_engine(priv)->cclass = &nv20_gr_cclass;
- nv_engine(priv)->sclass = nv20_gr_sclass;
- nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
+ nv_subdev(gr)->unit = 0x00001000;
+ nv_subdev(gr)->intr = nv20_gr_intr;
+ nv_engine(gr)->cclass = &nv20_gr_cclass;
+ nv_engine(gr)->sclass = nv20_gr_sclass;
+ nv_engine(gr)->tile_prog = nv20_gr_tile_prog;
return 0;
}
void
nv20_gr_dtor(struct nvkm_object *object)
{
- struct nv20_gr_priv *priv = (void *)object;
- nvkm_gpuobj_ref(NULL, &priv->ctxtab);
- nvkm_gr_destroy(&priv->base);
+ struct nv20_gr *gr = (void *)object;
+ nvkm_gpuobj_ref(NULL, &gr->ctxtab);
+ nvkm_gr_destroy(&gr->base);
}
int
nv20_gr_init(struct nvkm_object *object)
{
struct nvkm_engine *engine = nv_engine(object);
- struct nv20_gr_priv *priv = (void *)engine;
+ struct nv20_gr *gr = (void *)engine;
struct nvkm_fb *fb = nvkm_fb(object);
u32 tmp, vramsz;
int ret, i;
- ret = nvkm_gr_init(&priv->base);
+ ret = nvkm_gr_init(&gr->base);
if (ret)
return ret;
- nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4);
+ nv_wr32(gr, NV20_PGRAPH_CHANNEL_CTX_TABLE, gr->ctxtab->addr >> 4);
- if (nv_device(priv)->chipset == 0x20) {
- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
+ if (nv_device(gr)->chipset == 0x20) {
+ nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
for (i = 0; i < 15; i++)
- nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
- nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
+ nv_wr32(gr, NV10_PGRAPH_RDI_DATA, 0x00000000);
+ nv_wait(gr, 0x400700, 0xffffffff, 0x00000000);
} else {
- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
+ nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
for (i = 0; i < 32; i++)
- nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
- nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
+ nv_wr32(gr, NV10_PGRAPH_RDI_DATA, 0x00000000);
+ nv_wait(gr, 0x400700, 0xffffffff, 0x00000000);
}
- nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF);
- nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
+ nv_wr32(gr, NV03_PGRAPH_INTR , 0xFFFFFFFF);
+ nv_wr32(gr, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
- nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700);
- nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
- nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000);
- nv_wr32(priv, 0x40009C , 0x00000040);
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x00000000);
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_1, 0x00118700);
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
+ nv_wr32(gr, NV10_PGRAPH_DEBUG_4, 0x00000000);
+ nv_wr32(gr, 0x40009C , 0x00000040);
- if (nv_device(priv)->chipset >= 0x25) {
- nv_wr32(priv, 0x400890, 0x00a8cfff);
- nv_wr32(priv, 0x400610, 0x304B1FB6);
- nv_wr32(priv, 0x400B80, 0x1cbd3883);
- nv_wr32(priv, 0x400B84, 0x44000000);
- nv_wr32(priv, 0x400098, 0x40000080);
- nv_wr32(priv, 0x400B88, 0x000000ff);
+ if (nv_device(gr)->chipset >= 0x25) {
+ nv_wr32(gr, 0x400890, 0x00a8cfff);
+ nv_wr32(gr, 0x400610, 0x304B1FB6);
+ nv_wr32(gr, 0x400B80, 0x1cbd3883);
+ nv_wr32(gr, 0x400B84, 0x44000000);
+ nv_wr32(gr, 0x400098, 0x40000080);
+ nv_wr32(gr, 0x400B88, 0x000000ff);
} else {
- nv_wr32(priv, 0x400880, 0x0008c7df);
- nv_wr32(priv, 0x400094, 0x00000005);
- nv_wr32(priv, 0x400B80, 0x45eae20e);
- nv_wr32(priv, 0x400B84, 0x24000000);
- nv_wr32(priv, 0x400098, 0x00000040);
- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
- nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
- nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
+ nv_wr32(gr, 0x400880, 0x0008c7df);
+ nv_wr32(gr, 0x400094, 0x00000005);
+ nv_wr32(gr, 0x400B80, 0x45eae20e);
+ nv_wr32(gr, 0x400B84, 0x24000000);
+ nv_wr32(gr, 0x400098, 0x00000040);
+ nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
+ nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000030);
+ nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
+ nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000030);
}
/* Turn all the tiling regions off. */
for (i = 0; i < fb->tile.regions; i++)
engine->tile_prog(engine, i);
- nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324));
- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
- nv_wr32(priv, NV10_PGRAPH_RDI_DATA, nv_rd32(priv, 0x100324));
+ nv_wr32(gr, 0x4009a0, nv_rd32(gr, 0x100324));
+ nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
+ nv_wr32(gr, NV10_PGRAPH_RDI_DATA, nv_rd32(gr, 0x100324));
- nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
- nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF);
+ nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
+ nv_wr32(gr, NV10_PGRAPH_STATE , 0xFFFFFFFF);
- tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) & 0x0007ff00;
- nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
- tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) | 0x00020100;
- nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
+ tmp = nv_rd32(gr, NV10_PGRAPH_SURFACE) & 0x0007ff00;
+ nv_wr32(gr, NV10_PGRAPH_SURFACE, tmp);
+ tmp = nv_rd32(gr, NV10_PGRAPH_SURFACE) | 0x00020100;
+ nv_wr32(gr, NV10_PGRAPH_SURFACE, tmp);
/* begin RAM config */
- vramsz = nv_device_resource_len(nv_device(priv), 0) - 1;
- nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
- nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
- nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100200));
- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
- nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100204));
- nv_wr32(priv, 0x400820, 0);
- nv_wr32(priv, 0x400824, 0);
- nv_wr32(priv, 0x400864, vramsz - 1);
- nv_wr32(priv, 0x400868, vramsz - 1);
+ vramsz = nv_device_resource_len(nv_device(gr), 1) - 1;
+ nv_wr32(gr, 0x4009A4, nv_rd32(gr, 0x100200));
+ nv_wr32(gr, 0x4009A8, nv_rd32(gr, 0x100204));
+ nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
+ nv_wr32(gr, NV10_PGRAPH_RDI_DATA , nv_rd32(gr, 0x100200));
+ nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
+ nv_wr32(gr, NV10_PGRAPH_RDI_DATA , nv_rd32(gr, 0x100204));
+ nv_wr32(gr, 0x400820, 0);
+ nv_wr32(gr, 0x400824, 0);
+ nv_wr32(gr, 0x400864, vramsz - 1);
+ nv_wr32(gr, 0x400868, vramsz - 1);
/* interesting.. the below overwrites some of the tile setup above.. */
- nv_wr32(priv, 0x400B20, 0x00000000);
- nv_wr32(priv, 0x400B04, 0xFFFFFFFF);
+ nv_wr32(gr, 0x400B20, 0x00000000);
+ nv_wr32(gr, 0x400B04, 0xFFFFFFFF);
- nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
- nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
- nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
- nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
+ nv_wr32(gr, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
+ nv_wr32(gr, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
+ nv_wr32(gr, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
+ nv_wr32(gr, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
return 0;
}
#define __NV20_GR_H__
#include <engine/gr.h>
-struct nv20_gr_priv {
+struct nv20_gr {
struct nvkm_gr base;
struct nvkm_gpuobj *ctxtab;
};
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
- struct nv20_gr_priv *priv;
+ struct nv20_gr *gr;
int ret;
- ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
- *pobject = nv_object(priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
+ *pobject = nv_object(gr);
if (ret)
return ret;
- ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
+ ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab);
if (ret)
return ret;
- nv_subdev(priv)->unit = 0x00001000;
- nv_subdev(priv)->intr = nv20_gr_intr;
- nv_engine(priv)->cclass = &nv25_gr_cclass;
- nv_engine(priv)->sclass = nv25_gr_sclass;
- nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
+ nv_subdev(gr)->unit = 0x00001000;
+ nv_subdev(gr)->intr = nv20_gr_intr;
+ nv_engine(gr)->cclass = &nv25_gr_cclass;
+ nv_engine(gr)->sclass = nv25_gr_sclass;
+ nv_engine(gr)->tile_prog = nv20_gr_tile_prog;
return 0;
}
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
- struct nv20_gr_priv *priv;
+ struct nv20_gr *gr;
int ret;
- ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
- *pobject = nv_object(priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
+ *pobject = nv_object(gr);
if (ret)
return ret;
- ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
+ ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab);
if (ret)
return ret;
- nv_subdev(priv)->unit = 0x00001000;
- nv_subdev(priv)->intr = nv20_gr_intr;
- nv_engine(priv)->cclass = &nv2a_gr_cclass;
- nv_engine(priv)->sclass = nv25_gr_sclass;
- nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
+ nv_subdev(gr)->unit = 0x00001000;
+ nv_subdev(gr)->intr = nv20_gr_intr;
+ nv_engine(gr)->cclass = &nv2a_gr_cclass;
+ nv_engine(gr)->sclass = nv25_gr_sclass;
+ nv_engine(gr)->tile_prog = nv20_gr_tile_prog;
return 0;
}
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
- struct nv20_gr_priv *priv;
+ struct nv20_gr *gr;
int ret;
- ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
- *pobject = nv_object(priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
+ *pobject = nv_object(gr);
if (ret)
return ret;
- ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
+ ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab);
if (ret)
return ret;
- nv_subdev(priv)->unit = 0x00001000;
- nv_subdev(priv)->intr = nv20_gr_intr;
- nv_engine(priv)->cclass = &nv30_gr_cclass;
- nv_engine(priv)->sclass = nv30_gr_sclass;
- nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
+ nv_subdev(gr)->unit = 0x00001000;
+ nv_subdev(gr)->intr = nv20_gr_intr;
+ nv_engine(gr)->cclass = &nv30_gr_cclass;
+ nv_engine(gr)->sclass = nv30_gr_sclass;
+ nv_engine(gr)->tile_prog = nv20_gr_tile_prog;
return 0;
}
nv30_gr_init(struct nvkm_object *object)
{
struct nvkm_engine *engine = nv_engine(object);
- struct nv20_gr_priv *priv = (void *)engine;
+ struct nv20_gr *gr = (void *)engine;
struct nvkm_fb *fb = nvkm_fb(object);
int ret, i;
- ret = nvkm_gr_init(&priv->base);
+ ret = nvkm_gr_init(&gr->base);
if (ret)
return ret;
- nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4);
-
- nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF);
- nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
-
- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
- nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0);
- nv_wr32(priv, 0x400890, 0x01b463ff);
- nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xf2de0475);
- nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000);
- nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
- nv_wr32(priv, 0x400B80, 0x1003d888);
- nv_wr32(priv, 0x400B84, 0x0c000000);
- nv_wr32(priv, 0x400098, 0x00000000);
- nv_wr32(priv, 0x40009C, 0x0005ad00);
- nv_wr32(priv, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */
- nv_wr32(priv, 0x4000a0, 0x00000000);
- nv_wr32(priv, 0x4000a4, 0x00000008);
- nv_wr32(priv, 0x4008a8, 0xb784a400);
- nv_wr32(priv, 0x400ba0, 0x002f8685);
- nv_wr32(priv, 0x400ba4, 0x00231f3f);
- nv_wr32(priv, 0x4008a4, 0x40000020);
-
- if (nv_device(priv)->chipset == 0x34) {
- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
- nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00200201);
- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0008);
- nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000008);
- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
- nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000032);
- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00004);
- nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000002);
+ nv_wr32(gr, NV20_PGRAPH_CHANNEL_CTX_TABLE, gr->ctxtab->addr >> 4);
+
+ nv_wr32(gr, NV03_PGRAPH_INTR , 0xFFFFFFFF);
+ nv_wr32(gr, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
+
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x00000000);
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_1, 0x401287c0);
+ nv_wr32(gr, 0x400890, 0x01b463ff);
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0xf2de0475);
+ nv_wr32(gr, NV10_PGRAPH_DEBUG_4, 0x00008000);
+ nv_wr32(gr, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
+ nv_wr32(gr, 0x400B80, 0x1003d888);
+ nv_wr32(gr, 0x400B84, 0x0c000000);
+ nv_wr32(gr, 0x400098, 0x00000000);
+ nv_wr32(gr, 0x40009C, 0x0005ad00);
+ nv_wr32(gr, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */
+ nv_wr32(gr, 0x4000a0, 0x00000000);
+ nv_wr32(gr, 0x4000a4, 0x00000008);
+ nv_wr32(gr, 0x4008a8, 0xb784a400);
+ nv_wr32(gr, 0x400ba0, 0x002f8685);
+ nv_wr32(gr, 0x400ba4, 0x00231f3f);
+ nv_wr32(gr, 0x4008a4, 0x40000020);
+
+ if (nv_device(gr)->chipset == 0x34) {
+ nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
+ nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00200201);
+ nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0008);
+ nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000008);
+ nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
+ nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000032);
+ nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00E00004);
+ nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000002);
}
- nv_wr32(priv, 0x4000c0, 0x00000016);
+ nv_wr32(gr, 0x4000c0, 0x00000016);
/* Turn all the tiling regions off. */
for (i = 0; i < fb->tile.regions; i++)
engine->tile_prog(engine, i);
- nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
- nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF);
- nv_wr32(priv, 0x0040075c , 0x00000001);
+ nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
+ nv_wr32(gr, NV10_PGRAPH_STATE , 0xFFFFFFFF);
+ nv_wr32(gr, 0x0040075c , 0x00000001);
/* begin RAM config */
- /* vramsz = pci_resource_len(priv->dev->pdev, 0) - 1; */
- nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
- nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
- if (nv_device(priv)->chipset != 0x34) {
- nv_wr32(priv, 0x400750, 0x00EA0000);
- nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100200));
- nv_wr32(priv, 0x400750, 0x00EA0004);
- nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100204));
+ /* vramsz = pci_resource_len(gr->dev->pdev, 1) - 1; */
+ nv_wr32(gr, 0x4009A4, nv_rd32(gr, 0x100200));
+ nv_wr32(gr, 0x4009A8, nv_rd32(gr, 0x100204));
+ if (nv_device(gr)->chipset != 0x34) {
+ nv_wr32(gr, 0x400750, 0x00EA0000);
+ nv_wr32(gr, 0x400754, nv_rd32(gr, 0x100200));
+ nv_wr32(gr, 0x400750, 0x00EA0004);
+ nv_wr32(gr, 0x400754, nv_rd32(gr, 0x100204));
}
return 0;
}
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
- struct nv20_gr_priv *priv;
+ struct nv20_gr *gr;
int ret;
- ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
- *pobject = nv_object(priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
+ *pobject = nv_object(gr);
if (ret)
return ret;
- ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
+ ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab);
if (ret)
return ret;
- nv_subdev(priv)->unit = 0x00001000;
- nv_subdev(priv)->intr = nv20_gr_intr;
- nv_engine(priv)->cclass = &nv34_gr_cclass;
- nv_engine(priv)->sclass = nv34_gr_sclass;
- nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
+ nv_subdev(gr)->unit = 0x00001000;
+ nv_subdev(gr)->intr = nv20_gr_intr;
+ nv_engine(gr)->cclass = &nv34_gr_cclass;
+ nv_engine(gr)->sclass = nv34_gr_sclass;
+ nv_engine(gr)->tile_prog = nv20_gr_tile_prog;
return 0;
}
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
- struct nv20_gr_priv *priv;
+ struct nv20_gr *gr;
int ret;
- ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
- *pobject = nv_object(priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
+ *pobject = nv_object(gr);
if (ret)
return ret;
- ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
+ ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab);
if (ret)
return ret;
- nv_subdev(priv)->unit = 0x00001000;
- nv_subdev(priv)->intr = nv20_gr_intr;
- nv_engine(priv)->cclass = &nv35_gr_cclass;
- nv_engine(priv)->sclass = nv35_gr_sclass;
- nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
+ nv_subdev(gr)->unit = 0x00001000;
+ nv_subdev(gr)->intr = nv20_gr_intr;
+ nv_engine(gr)->cclass = &nv35_gr_cclass;
+ nv_engine(gr)->sclass = nv35_gr_sclass;
+ nv_engine(gr)->tile_prog = nv20_gr_tile_prog;
return 0;
}
#include <subdev/timer.h>
#include <engine/fifo.h>
-struct nv40_gr_priv {
+struct nv40_gr {
struct nvkm_gr base;
u32 size;
};
static u64
nv40_gr_units(struct nvkm_gr *gr)
{
- struct nv40_gr_priv *priv = (void *)gr;
-
- return nv_rd32(priv, 0x1540);
+ return nv_rd32(gr, 0x1540);
}
/*******************************************************************************
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
- struct nv40_gr_priv *priv = (void *)engine;
+ struct nv40_gr *gr = (void *)engine;
struct nv40_gr_chan *chan;
int ret;
- ret = nvkm_gr_context_create(parent, engine, oclass, NULL, priv->size,
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL, gr->size,
16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
- nv40_grctx_fill(nv_device(priv), nv_gpuobj(chan));
+ nv40_grctx_fill(nv_device(gr), nv_gpuobj(chan));
nv_wo32(chan, 0x00000, nv_gpuobj(chan)->addr >> 4);
return 0;
}
static int
nv40_gr_context_fini(struct nvkm_object *object, bool suspend)
{
- struct nv40_gr_priv *priv = (void *)object->engine;
+ struct nv40_gr *gr = (void *)object->engine;
struct nv40_gr_chan *chan = (void *)object;
u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4;
int ret = 0;
- nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
+ nv_mask(gr, 0x400720, 0x00000001, 0x00000000);
- if (nv_rd32(priv, 0x40032c) == inst) {
+ if (nv_rd32(gr, 0x40032c) == inst) {
if (suspend) {
- nv_wr32(priv, 0x400720, 0x00000000);
- nv_wr32(priv, 0x400784, inst);
- nv_mask(priv, 0x400310, 0x00000020, 0x00000020);
- nv_mask(priv, 0x400304, 0x00000001, 0x00000001);
- if (!nv_wait(priv, 0x400300, 0x00000001, 0x00000000)) {
- u32 insn = nv_rd32(priv, 0x400308);
- nv_warn(priv, "ctxprog timeout 0x%08x\n", insn);
+ nv_wr32(gr, 0x400720, 0x00000000);
+ nv_wr32(gr, 0x400784, inst);
+ nv_mask(gr, 0x400310, 0x00000020, 0x00000020);
+ nv_mask(gr, 0x400304, 0x00000001, 0x00000001);
+ if (!nv_wait(gr, 0x400300, 0x00000001, 0x00000000)) {
+ u32 insn = nv_rd32(gr, 0x400308);
+ nv_warn(gr, "ctxprog timeout 0x%08x\n", insn);
ret = -EBUSY;
}
}
- nv_mask(priv, 0x40032c, 0x01000000, 0x00000000);
+ nv_mask(gr, 0x40032c, 0x01000000, 0x00000000);
}
- if (nv_rd32(priv, 0x400330) == inst)
- nv_mask(priv, 0x400330, 0x01000000, 0x00000000);
+ if (nv_rd32(gr, 0x400330) == inst)
+ nv_mask(gr, 0x400330, 0x01000000, 0x00000000);
- nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
+ nv_mask(gr, 0x400720, 0x00000001, 0x00000001);
return ret;
}
{
struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i];
struct nvkm_fifo *fifo = nvkm_fifo(engine);
- struct nv40_gr_priv *priv = (void *)engine;
+ struct nv40_gr *gr = (void *)engine;
unsigned long flags;
fifo->pause(fifo, &flags);
- nv04_gr_idle(priv);
+ nv04_gr_idle(gr);
- switch (nv_device(priv)->chipset) {
+ switch (nv_device(gr)->chipset) {
case 0x40:
case 0x41:
case 0x42:
case 0x43:
case 0x45:
case 0x4e:
- nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
- nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
- nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
- nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);
- nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);
- nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);
- switch (nv_device(priv)->chipset) {
+ nv_wr32(gr, NV20_PGRAPH_TSIZE(i), tile->pitch);
+ nv_wr32(gr, NV20_PGRAPH_TLIMIT(i), tile->limit);
+ nv_wr32(gr, NV20_PGRAPH_TILE(i), tile->addr);
+ nv_wr32(gr, NV40_PGRAPH_TSIZE1(i), tile->pitch);
+ nv_wr32(gr, NV40_PGRAPH_TLIMIT1(i), tile->limit);
+ nv_wr32(gr, NV40_PGRAPH_TILE1(i), tile->addr);
+ switch (nv_device(gr)->chipset) {
case 0x40:
case 0x45:
- nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
- nv_wr32(priv, NV40_PGRAPH_ZCOMP1(i), tile->zcomp);
+ nv_wr32(gr, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
+ nv_wr32(gr, NV40_PGRAPH_ZCOMP1(i), tile->zcomp);
break;
case 0x41:
case 0x42:
case 0x43:
- nv_wr32(priv, NV41_PGRAPH_ZCOMP0(i), tile->zcomp);
- nv_wr32(priv, NV41_PGRAPH_ZCOMP1(i), tile->zcomp);
+ nv_wr32(gr, NV41_PGRAPH_ZCOMP0(i), tile->zcomp);
+ nv_wr32(gr, NV41_PGRAPH_ZCOMP1(i), tile->zcomp);
break;
default:
break;
break;
case 0x44:
case 0x4a:
- nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
- nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
- nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
+ nv_wr32(gr, NV20_PGRAPH_TSIZE(i), tile->pitch);
+ nv_wr32(gr, NV20_PGRAPH_TLIMIT(i), tile->limit);
+ nv_wr32(gr, NV20_PGRAPH_TILE(i), tile->addr);
break;
case 0x46:
case 0x4c:
case 0x63:
case 0x67:
case 0x68:
- nv_wr32(priv, NV47_PGRAPH_TSIZE(i), tile->pitch);
- nv_wr32(priv, NV47_PGRAPH_TLIMIT(i), tile->limit);
- nv_wr32(priv, NV47_PGRAPH_TILE(i), tile->addr);
- nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);
- nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);
- nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);
- switch (nv_device(priv)->chipset) {
+ nv_wr32(gr, NV47_PGRAPH_TSIZE(i), tile->pitch);
+ nv_wr32(gr, NV47_PGRAPH_TLIMIT(i), tile->limit);
+ nv_wr32(gr, NV47_PGRAPH_TILE(i), tile->addr);
+ nv_wr32(gr, NV40_PGRAPH_TSIZE1(i), tile->pitch);
+ nv_wr32(gr, NV40_PGRAPH_TLIMIT1(i), tile->limit);
+ nv_wr32(gr, NV40_PGRAPH_TILE1(i), tile->addr);
+ switch (nv_device(gr)->chipset) {
case 0x47:
case 0x49:
case 0x4b:
- nv_wr32(priv, NV47_PGRAPH_ZCOMP0(i), tile->zcomp);
- nv_wr32(priv, NV47_PGRAPH_ZCOMP1(i), tile->zcomp);
+ nv_wr32(gr, NV47_PGRAPH_ZCOMP0(i), tile->zcomp);
+ nv_wr32(gr, NV47_PGRAPH_ZCOMP1(i), tile->zcomp);
break;
default:
break;
struct nvkm_engine *engine = nv_engine(subdev);
struct nvkm_object *engctx;
struct nvkm_handle *handle = NULL;
- struct nv40_gr_priv *priv = (void *)subdev;
- u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
- u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
- u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
- u32 inst = nv_rd32(priv, 0x40032c) & 0x000fffff;
- u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
+ struct nv40_gr *gr = (void *)subdev;
+ u32 stat = nv_rd32(gr, NV03_PGRAPH_INTR);
+ u32 nsource = nv_rd32(gr, NV03_PGRAPH_NSOURCE);
+ u32 nstatus = nv_rd32(gr, NV03_PGRAPH_NSTATUS);
+ u32 inst = nv_rd32(gr, 0x40032c) & 0x000fffff;
+ u32 addr = nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR);
u32 subc = (addr & 0x00070000) >> 16;
u32 mthd = (addr & 0x00001ffc);
- u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
- u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xffff;
+ u32 data = nv_rd32(gr, NV04_PGRAPH_TRAPPED_DATA);
+ u32 class = nv_rd32(gr, 0x400160 + subc * 4) & 0xffff;
u32 show = stat;
int chid;
}
if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
- nv_mask(priv, 0x402000, 0, 0);
+ nv_mask(gr, 0x402000, 0, 0);
}
}
- nv_wr32(priv, NV03_PGRAPH_INTR, stat);
- nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
+ nv_wr32(gr, NV03_PGRAPH_INTR, stat);
+ nv_wr32(gr, NV04_PGRAPH_FIFO, 0x00000001);
if (show) {
- nv_error(priv, "%s", "");
+ nv_error(gr, "%s", "");
nvkm_bitfield_print(nv10_gr_intr_name, show);
pr_cont(" nsource:");
nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
pr_cont("\n");
- nv_error(priv,
+ nv_error(gr,
"ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, inst << 4, nvkm_client_name(engctx), subc,
class, mthd, data);
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
- struct nv40_gr_priv *priv;
+ struct nv40_gr *gr;
int ret;
- ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
- *pobject = nv_object(priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
+ *pobject = nv_object(gr);
if (ret)
return ret;
- nv_subdev(priv)->unit = 0x00001000;
- nv_subdev(priv)->intr = nv40_gr_intr;
- nv_engine(priv)->cclass = &nv40_gr_cclass;
- if (nv44_gr_class(priv))
- nv_engine(priv)->sclass = nv44_gr_sclass;
+ nv_subdev(gr)->unit = 0x00001000;
+ nv_subdev(gr)->intr = nv40_gr_intr;
+ nv_engine(gr)->cclass = &nv40_gr_cclass;
+ if (nv44_gr_class(gr))
+ nv_engine(gr)->sclass = nv44_gr_sclass;
else
- nv_engine(priv)->sclass = nv40_gr_sclass;
- nv_engine(priv)->tile_prog = nv40_gr_tile_prog;
+ nv_engine(gr)->sclass = nv40_gr_sclass;
+ nv_engine(gr)->tile_prog = nv40_gr_tile_prog;
- priv->base.units = nv40_gr_units;
+ gr->base.units = nv40_gr_units;
return 0;
}
{
struct nvkm_engine *engine = nv_engine(object);
struct nvkm_fb *fb = nvkm_fb(object);
- struct nv40_gr_priv *priv = (void *)engine;
+ struct nv40_gr *gr = (void *)engine;
int ret, i, j;
u32 vramsz;
- ret = nvkm_gr_init(&priv->base);
+ ret = nvkm_gr_init(&gr->base);
if (ret)
return ret;
/* generate and upload context program */
- ret = nv40_grctx_init(nv_device(priv), &priv->size);
+ ret = nv40_grctx_init(nv_device(gr), &gr->size);
if (ret)
return ret;
/* No context present currently */
- nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
+ nv_wr32(gr, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
- nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF);
- nv_wr32(priv, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
+ nv_wr32(gr, NV03_PGRAPH_INTR , 0xFFFFFFFF);
+ nv_wr32(gr, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
- nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0);
- nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
- nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000);
- nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x00000000);
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_1, 0x401287c0);
+ nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
+ nv_wr32(gr, NV10_PGRAPH_DEBUG_4, 0x00008000);
+ nv_wr32(gr, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
- nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
- nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF);
+ nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
+ nv_wr32(gr, NV10_PGRAPH_STATE , 0xFFFFFFFF);
- j = nv_rd32(priv, 0x1540) & 0xff;
+ j = nv_rd32(gr, 0x1540) & 0xff;
if (j) {
for (i = 0; !(j & 1); j >>= 1, i++)
;
- nv_wr32(priv, 0x405000, i);
+ nv_wr32(gr, 0x405000, i);
}
- if (nv_device(priv)->chipset == 0x40) {
- nv_wr32(priv, 0x4009b0, 0x83280fff);
- nv_wr32(priv, 0x4009b4, 0x000000a0);
+ if (nv_device(gr)->chipset == 0x40) {
+ nv_wr32(gr, 0x4009b0, 0x83280fff);
+ nv_wr32(gr, 0x4009b4, 0x000000a0);
} else {
- nv_wr32(priv, 0x400820, 0x83280eff);
- nv_wr32(priv, 0x400824, 0x000000a0);
+ nv_wr32(gr, 0x400820, 0x83280eff);
+ nv_wr32(gr, 0x400824, 0x000000a0);
}
- switch (nv_device(priv)->chipset) {
+ switch (nv_device(gr)->chipset) {
case 0x40:
case 0x45:
- nv_wr32(priv, 0x4009b8, 0x0078e366);
- nv_wr32(priv, 0x4009bc, 0x0000014c);
+ nv_wr32(gr, 0x4009b8, 0x0078e366);
+ nv_wr32(gr, 0x4009bc, 0x0000014c);
break;
case 0x41:
case 0x42: /* pciid also 0x00Cx */
/* case 0x0120: XXX (pciid) */
- nv_wr32(priv, 0x400828, 0x007596ff);
- nv_wr32(priv, 0x40082c, 0x00000108);
+ nv_wr32(gr, 0x400828, 0x007596ff);
+ nv_wr32(gr, 0x40082c, 0x00000108);
break;
case 0x43:
- nv_wr32(priv, 0x400828, 0x0072cb77);
- nv_wr32(priv, 0x40082c, 0x00000108);
+ nv_wr32(gr, 0x400828, 0x0072cb77);
+ nv_wr32(gr, 0x40082c, 0x00000108);
break;
case 0x44:
case 0x46: /* G72 */
case 0x4a:
case 0x4c: /* G7x-based C51 */
case 0x4e:
- nv_wr32(priv, 0x400860, 0);
- nv_wr32(priv, 0x400864, 0);
+ nv_wr32(gr, 0x400860, 0);
+ nv_wr32(gr, 0x400864, 0);
break;
case 0x47: /* G70 */
case 0x49: /* G71 */
case 0x4b: /* G73 */
- nv_wr32(priv, 0x400828, 0x07830610);
- nv_wr32(priv, 0x40082c, 0x0000016A);
+ nv_wr32(gr, 0x400828, 0x07830610);
+ nv_wr32(gr, 0x40082c, 0x0000016A);
break;
default:
break;
}
- nv_wr32(priv, 0x400b38, 0x2ffff800);
- nv_wr32(priv, 0x400b3c, 0x00006000);
+ nv_wr32(gr, 0x400b38, 0x2ffff800);
+ nv_wr32(gr, 0x400b3c, 0x00006000);
/* Tiling related stuff. */
- switch (nv_device(priv)->chipset) {
+ switch (nv_device(gr)->chipset) {
case 0x44:
case 0x4a:
- nv_wr32(priv, 0x400bc4, 0x1003d888);
- nv_wr32(priv, 0x400bbc, 0xb7a7b500);
+ nv_wr32(gr, 0x400bc4, 0x1003d888);
+ nv_wr32(gr, 0x400bbc, 0xb7a7b500);
break;
case 0x46:
- nv_wr32(priv, 0x400bc4, 0x0000e024);
- nv_wr32(priv, 0x400bbc, 0xb7a7b520);
+ nv_wr32(gr, 0x400bc4, 0x0000e024);
+ nv_wr32(gr, 0x400bbc, 0xb7a7b520);
break;
case 0x4c:
case 0x4e:
case 0x67:
- nv_wr32(priv, 0x400bc4, 0x1003d888);
- nv_wr32(priv, 0x400bbc, 0xb7a7b540);
+ nv_wr32(gr, 0x400bc4, 0x1003d888);
+ nv_wr32(gr, 0x400bbc, 0xb7a7b540);
break;
default:
break;
engine->tile_prog(engine, i);
/* begin RAM config */
- vramsz = nv_device_resource_len(nv_device(priv), 0) - 1;
- switch (nv_device(priv)->chipset) {
+ vramsz = nv_device_resource_len(nv_device(gr), 1) - 1;
+ switch (nv_device(gr)->chipset) {
case 0x40:
- nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
- nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
- nv_wr32(priv, 0x4069A4, nv_rd32(priv, 0x100200));
- nv_wr32(priv, 0x4069A8, nv_rd32(priv, 0x100204));
- nv_wr32(priv, 0x400820, 0);
- nv_wr32(priv, 0x400824, 0);
- nv_wr32(priv, 0x400864, vramsz);
- nv_wr32(priv, 0x400868, vramsz);
+ nv_wr32(gr, 0x4009A4, nv_rd32(gr, 0x100200));
+ nv_wr32(gr, 0x4009A8, nv_rd32(gr, 0x100204));
+ nv_wr32(gr, 0x4069A4, nv_rd32(gr, 0x100200));
+ nv_wr32(gr, 0x4069A8, nv_rd32(gr, 0x100204));
+ nv_wr32(gr, 0x400820, 0);
+ nv_wr32(gr, 0x400824, 0);
+ nv_wr32(gr, 0x400864, vramsz);
+ nv_wr32(gr, 0x400868, vramsz);
break;
default:
- switch (nv_device(priv)->chipset) {
+ switch (nv_device(gr)->chipset) {
case 0x41:
case 0x42:
case 0x43:
case 0x4e:
case 0x44:
case 0x4a:
- nv_wr32(priv, 0x4009F0, nv_rd32(priv, 0x100200));
- nv_wr32(priv, 0x4009F4, nv_rd32(priv, 0x100204));
+ nv_wr32(gr, 0x4009F0, nv_rd32(gr, 0x100200));
+ nv_wr32(gr, 0x4009F4, nv_rd32(gr, 0x100204));
break;
default:
- nv_wr32(priv, 0x400DF0, nv_rd32(priv, 0x100200));
- nv_wr32(priv, 0x400DF4, nv_rd32(priv, 0x100204));
+ nv_wr32(gr, 0x400DF0, nv_rd32(gr, 0x100200));
+ nv_wr32(gr, 0x400DF4, nv_rd32(gr, 0x100204));
break;
}
- nv_wr32(priv, 0x4069F0, nv_rd32(priv, 0x100200));
- nv_wr32(priv, 0x4069F4, nv_rd32(priv, 0x100204));
- nv_wr32(priv, 0x400840, 0);
- nv_wr32(priv, 0x400844, 0);
- nv_wr32(priv, 0x4008A0, vramsz);
- nv_wr32(priv, 0x4008A4, vramsz);
+ nv_wr32(gr, 0x4069F0, nv_rd32(gr, 0x100200));
+ nv_wr32(gr, 0x4069F4, nv_rd32(gr, 0x100204));
+ nv_wr32(gr, 0x400840, 0);
+ nv_wr32(gr, 0x400844, 0);
+ nv_wr32(gr, 0x4008A0, vramsz);
+ nv_wr32(gr, 0x4008A4, vramsz);
break;
}
#include <engine/fifo.h>
#include <subdev/timer.h>
-struct nv50_gr_priv {
+struct nv50_gr {
struct nvkm_gr base;
spinlock_t lock;
u32 size;
static u64
nv50_gr_units(struct nvkm_gr *gr)
{
- struct nv50_gr_priv *priv = (void *)gr;
-
- return nv_rd32(priv, 0x1540);
+ return nv_rd32(gr, 0x1540);
}
/*******************************************************************************
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
- struct nv50_gr_priv *priv = (void *)engine;
+ struct nv50_gr *gr = (void *)engine;
struct nv50_gr_chan *chan;
int ret;
- ret = nvkm_gr_context_create(parent, engine, oclass, NULL, priv->size,
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL, gr->size,
0, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
- nv50_grctx_fill(nv_device(priv), nv_gpuobj(chan));
+ nv50_grctx_fill(nv_device(gr), nv_gpuobj(chan));
return 0;
}
* PGRAPH engine/subdev functions
******************************************************************************/
-static const struct nvkm_bitfield nv50_pgr_status[] = {
+static const struct nvkm_bitfield nv50_gr_status[] = {
{ 0x00000001, "BUSY" }, /* set when any bit is set */
{ 0x00000002, "DISPATCH" },
{ 0x00000004, "UNK2" },
{}
};
-static const char *const nv50_pgr_vstatus_0[] = {
+static const char *const nv50_gr_vstatus_0[] = {
"VFETCH", "CCACHE", "PREGEOM", "POSTGEOM", "VATTR", "STRMOUT", "VCLIP",
NULL
};
-static const char *const nv50_pgr_vstatus_1[] = {
+static const char *const nv50_gr_vstatus_1[] = {
"TPC_RAST", "TPC_PROP", "TPC_TEX", "TPC_GEOM", "TPC_MP", NULL
};
-static const char *const nv50_pgr_vstatus_2[] = {
+static const char *const nv50_gr_vstatus_2[] = {
"RATTR", "APLANE", "TRAST", "CLIPID", "ZCULL", "ENG2D", "RMASK",
"ROP", NULL
};
static void
-nvkm_pgr_vstatus_print(struct nv50_gr_priv *priv, int r,
+nvkm_gr_vstatus_print(struct nv50_gr *gr, int r,
const char *const units[], u32 status)
{
int i;
- nv_error(priv, "PGRAPH_VSTATUS%d: 0x%08x", r, status);
+ nv_error(gr, "PGRAPH_VSTATUS%d: 0x%08x", r, status);
for (i = 0; units[i] && status; i++) {
if ((status & 7) == 1)
g84_gr_tlb_flush(struct nvkm_engine *engine)
{
struct nvkm_timer *tmr = nvkm_timer(engine);
- struct nv50_gr_priv *priv = (void *)engine;
+ struct nv50_gr *gr = (void *)engine;
bool idle, timeout = false;
unsigned long flags;
u64 start;
u32 tmp;
- spin_lock_irqsave(&priv->lock, flags);
- nv_mask(priv, 0x400500, 0x00000001, 0x00000000);
+ spin_lock_irqsave(&gr->lock, flags);
+ nv_mask(gr, 0x400500, 0x00000001, 0x00000000);
start = tmr->read(tmr);
do {
idle = true;
- for (tmp = nv_rd32(priv, 0x400380); tmp && idle; tmp >>= 3) {
+ for (tmp = nv_rd32(gr, 0x400380); tmp && idle; tmp >>= 3) {
if ((tmp & 7) == 1)
idle = false;
}
- for (tmp = nv_rd32(priv, 0x400384); tmp && idle; tmp >>= 3) {
+ for (tmp = nv_rd32(gr, 0x400384); tmp && idle; tmp >>= 3) {
if ((tmp & 7) == 1)
idle = false;
}
- for (tmp = nv_rd32(priv, 0x400388); tmp && idle; tmp >>= 3) {
+ for (tmp = nv_rd32(gr, 0x400388); tmp && idle; tmp >>= 3) {
if ((tmp & 7) == 1)
idle = false;
}
!(timeout = tmr->read(tmr) - start > 2000000000));
if (timeout) {
- nv_error(priv, "PGRAPH TLB flush idle timeout fail\n");
+ nv_error(gr, "PGRAPH TLB flush idle timeout fail\n");
- tmp = nv_rd32(priv, 0x400700);
- nv_error(priv, "PGRAPH_STATUS : 0x%08x", tmp);
- nvkm_bitfield_print(nv50_pgr_status, tmp);
+ tmp = nv_rd32(gr, 0x400700);
+ nv_error(gr, "PGRAPH_STATUS : 0x%08x", tmp);
+ nvkm_bitfield_print(nv50_gr_status, tmp);
pr_cont("\n");
- nvkm_pgr_vstatus_print(priv, 0, nv50_pgr_vstatus_0,
- nv_rd32(priv, 0x400380));
- nvkm_pgr_vstatus_print(priv, 1, nv50_pgr_vstatus_1,
- nv_rd32(priv, 0x400384));
- nvkm_pgr_vstatus_print(priv, 2, nv50_pgr_vstatus_2,
- nv_rd32(priv, 0x400388));
+ nvkm_gr_vstatus_print(gr, 0, nv50_gr_vstatus_0,
+ nv_rd32(gr, 0x400380));
+ nvkm_gr_vstatus_print(gr, 1, nv50_gr_vstatus_1,
+ nv_rd32(gr, 0x400384));
+ nvkm_gr_vstatus_print(gr, 2, nv50_gr_vstatus_2,
+ nv_rd32(gr, 0x400388));
}
- nv_wr32(priv, 0x100c80, 0x00000001);
- if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000))
- nv_error(priv, "vm flush timeout\n");
- nv_mask(priv, 0x400500, 0x00000001, 0x00000001);
- spin_unlock_irqrestore(&priv->lock, flags);
+ nv_wr32(gr, 0x100c80, 0x00000001);
+ if (!nv_wait(gr, 0x100c80, 0x00000001, 0x00000000))
+ nv_error(gr, "vm flush timeout\n");
+ nv_mask(gr, 0x400500, 0x00000001, 0x00000001);
+ spin_unlock_irqrestore(&gr->lock, flags);
return timeout ? -EBUSY : 0;
}
};
static void
-nv50_priv_prop_trap(struct nv50_gr_priv *priv,
+nv50_gr_prop_trap(struct nv50_gr *gr,
u32 ustatus_addr, u32 ustatus, u32 tp)
{
- u32 e0c = nv_rd32(priv, ustatus_addr + 0x04);
- u32 e10 = nv_rd32(priv, ustatus_addr + 0x08);
- u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c);
- u32 e18 = nv_rd32(priv, ustatus_addr + 0x10);
- u32 e1c = nv_rd32(priv, ustatus_addr + 0x14);
- u32 e20 = nv_rd32(priv, ustatus_addr + 0x18);
- u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c);
+ u32 e0c = nv_rd32(gr, ustatus_addr + 0x04);
+ u32 e10 = nv_rd32(gr, ustatus_addr + 0x08);
+ u32 e14 = nv_rd32(gr, ustatus_addr + 0x0c);
+ u32 e18 = nv_rd32(gr, ustatus_addr + 0x10);
+ u32 e1c = nv_rd32(gr, ustatus_addr + 0x14);
+ u32 e20 = nv_rd32(gr, ustatus_addr + 0x18);
+ u32 e24 = nv_rd32(gr, ustatus_addr + 0x1c);
/* CUDA memory: l[], g[] or stack. */
if (ustatus & 0x00000080) {
if (e18 & 0x80000000) {
/* g[] read fault? */
- nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n",
+ nv_error(gr, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n",
tp, e14, e10 | ((e18 >> 24) & 0x1f));
e18 &= ~0x1f000000;
} else if (e18 & 0xc) {
/* g[] write fault? */
- nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n",
+ nv_error(gr, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n",
tp, e14, e10 | ((e18 >> 7) & 0x1f));
e18 &= ~0x00000f80;
} else {
- nv_error(priv, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n",
+ nv_error(gr, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n",
tp, e14, e10);
}
ustatus &= ~0x00000080;
}
if (ustatus) {
- nv_error(priv, "TRAP_PROP - TP %d -", tp);
+ nv_error(gr, "TRAP_PROP - TP %d -", tp);
nvkm_bitfield_print(nv50_gr_trap_prop, ustatus);
pr_cont(" - Address %02x%08x\n", e14, e10);
}
- nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
+ nv_error(gr, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
tp, e0c, e18, e1c, e20, e24);
}
static void
-nv50_priv_mp_trap(struct nv50_gr_priv *priv, int tpid, int display)
+nv50_gr_mp_trap(struct nv50_gr *gr, int tpid, int display)
{
- u32 units = nv_rd32(priv, 0x1540);
+ u32 units = nv_rd32(gr, 0x1540);
u32 addr, mp10, status, pc, oplow, ophigh;
int i;
int mps = 0;
for (i = 0; i < 4; i++) {
if (!(units & 1 << (i+24)))
continue;
- if (nv_device(priv)->chipset < 0xa0)
+ if (nv_device(gr)->chipset < 0xa0)
addr = 0x408200 + (tpid << 12) + (i << 7);
else
addr = 0x408100 + (tpid << 11) + (i << 7);
- mp10 = nv_rd32(priv, addr + 0x10);
- status = nv_rd32(priv, addr + 0x14);
+ mp10 = nv_rd32(gr, addr + 0x10);
+ status = nv_rd32(gr, addr + 0x14);
if (!status)
continue;
if (display) {
- nv_rd32(priv, addr + 0x20);
- pc = nv_rd32(priv, addr + 0x24);
- oplow = nv_rd32(priv, addr + 0x70);
- ophigh = nv_rd32(priv, addr + 0x74);
- nv_error(priv, "TRAP_MP_EXEC - "
+ nv_rd32(gr, addr + 0x20);
+ pc = nv_rd32(gr, addr + 0x24);
+ oplow = nv_rd32(gr, addr + 0x70);
+ ophigh = nv_rd32(gr, addr + 0x74);
+ nv_error(gr, "TRAP_MP_EXEC - "
"TP %d MP %d:", tpid, i);
nvkm_bitfield_print(nv50_mp_exec_errors, status);
pr_cont(" at %06x warp %d, opcode %08x %08x\n",
pc&0xffffff, pc >> 24,
oplow, ophigh);
}
- nv_wr32(priv, addr + 0x10, mp10);
- nv_wr32(priv, addr + 0x14, 0);
+ nv_wr32(gr, addr + 0x10, mp10);
+ nv_wr32(gr, addr + 0x14, 0);
mps++;
}
if (!mps && display)
- nv_error(priv, "TRAP_MP_EXEC - TP %d: "
+ nv_error(gr, "TRAP_MP_EXEC - TP %d: "
"No MPs claiming errors?\n", tpid);
}
static void
-nv50_priv_tp_trap(struct nv50_gr_priv *priv, int type, u32 ustatus_old,
+nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old,
u32 ustatus_new, int display, const char *name)
{
int tps = 0;
- u32 units = nv_rd32(priv, 0x1540);
+ u32 units = nv_rd32(gr, 0x1540);
int i, r;
u32 ustatus_addr, ustatus;
for (i = 0; i < 16; i++) {
if (!(units & (1 << i)))
continue;
- if (nv_device(priv)->chipset < 0xa0)
+ if (nv_device(gr)->chipset < 0xa0)
ustatus_addr = ustatus_old + (i << 12);
else
ustatus_addr = ustatus_new + (i << 11);
- ustatus = nv_rd32(priv, ustatus_addr) & 0x7fffffff;
+ ustatus = nv_rd32(gr, ustatus_addr) & 0x7fffffff;
if (!ustatus)
continue;
tps++;
switch (type) {
case 6: /* texture error... unknown for now */
if (display) {
- nv_error(priv, "magic set %d:\n", i);
+ nv_error(gr, "magic set %d:\n", i);
for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
- nv_error(priv, "\t0x%08x: 0x%08x\n", r,
- nv_rd32(priv, r));
+ nv_error(gr, "\t0x%08x: 0x%08x\n", r,
+ nv_rd32(gr, r));
if (ustatus) {
- nv_error(priv, "%s - TP%d:", name, i);
+ nv_error(gr, "%s - TP%d:", name, i);
nvkm_bitfield_print(nv50_tex_traps,
ustatus);
pr_cont("\n");
break;
case 7: /* MP error */
if (ustatus & 0x04030000) {
- nv50_priv_mp_trap(priv, i, display);
+ nv50_gr_mp_trap(gr, i, display);
ustatus &= ~0x04030000;
}
if (ustatus && display) {
- nv_error(priv, "%s - TP%d:", name, i);
+ nv_error(gr, "%s - TP%d:", name, i);
nvkm_bitfield_print(nv50_mpc_traps, ustatus);
pr_cont("\n");
ustatus = 0;
break;
case 8: /* PROP error */
if (display)
- nv50_priv_prop_trap(
- priv, ustatus_addr, ustatus, i);
+ nv50_gr_prop_trap(
+ gr, ustatus_addr, ustatus, i);
ustatus = 0;
break;
}
if (ustatus) {
if (display)
- nv_error(priv, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
+ nv_error(gr, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
}
- nv_wr32(priv, ustatus_addr, 0xc0000000);
+ nv_wr32(gr, ustatus_addr, 0xc0000000);
}
if (!tps && display)
- nv_warn(priv, "%s - No TPs claiming errors?\n", name);
+ nv_warn(gr, "%s - No TPs claiming errors?\n", name);
}
static int
-nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display,
+nv50_gr_trap_handler(struct nv50_gr *gr, u32 display,
int chid, u64 inst, struct nvkm_object *engctx)
{
- u32 status = nv_rd32(priv, 0x400108);
+ u32 status = nv_rd32(gr, 0x400108);
u32 ustatus;
if (!status && display) {
- nv_error(priv, "TRAP: no units reporting traps?\n");
+ nv_error(gr, "TRAP: no units reporting traps?\n");
return 1;
}
* COND, QUERY. If you get a trap from it, the command is still stuck
* in DISPATCH and you need to do something about it. */
if (status & 0x001) {
- ustatus = nv_rd32(priv, 0x400804) & 0x7fffffff;
+ ustatus = nv_rd32(gr, 0x400804) & 0x7fffffff;
if (!ustatus && display) {
- nv_error(priv, "TRAP_DISPATCH - no ustatus?\n");
+ nv_error(gr, "TRAP_DISPATCH - no ustatus?\n");
}
- nv_wr32(priv, 0x400500, 0x00000000);
+ nv_wr32(gr, 0x400500, 0x00000000);
/* Known to be triggered by screwed up NOTIFY and COND... */
if (ustatus & 0x00000001) {
- u32 addr = nv_rd32(priv, 0x400808);
+ u32 addr = nv_rd32(gr, 0x400808);
u32 subc = (addr & 0x00070000) >> 16;
u32 mthd = (addr & 0x00001ffc);
- u32 datal = nv_rd32(priv, 0x40080c);
- u32 datah = nv_rd32(priv, 0x400810);
- u32 class = nv_rd32(priv, 0x400814);
- u32 r848 = nv_rd32(priv, 0x400848);
+ u32 datal = nv_rd32(gr, 0x40080c);
+ u32 datah = nv_rd32(gr, 0x400810);
+ u32 class = nv_rd32(gr, 0x400814);
+ u32 r848 = nv_rd32(gr, 0x400848);
- nv_error(priv, "TRAP DISPATCH_FAULT\n");
+ nv_error(gr, "TRAP DISPATCH_FAULT\n");
if (display && (addr & 0x80000000)) {
- nv_error(priv,
+ nv_error(gr,
"ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n",
chid, inst,
nvkm_client_name(engctx), subc,
class, mthd, datah, datal, addr, r848);
} else
if (display) {
- nv_error(priv, "no stuck command?\n");
+ nv_error(gr, "no stuck command?\n");
}
- nv_wr32(priv, 0x400808, 0);
- nv_wr32(priv, 0x4008e8, nv_rd32(priv, 0x4008e8) & 3);
- nv_wr32(priv, 0x400848, 0);
+ nv_wr32(gr, 0x400808, 0);
+ nv_wr32(gr, 0x4008e8, nv_rd32(gr, 0x4008e8) & 3);
+ nv_wr32(gr, 0x400848, 0);
ustatus &= ~0x00000001;
}
if (ustatus & 0x00000002) {
- u32 addr = nv_rd32(priv, 0x40084c);
+ u32 addr = nv_rd32(gr, 0x40084c);
u32 subc = (addr & 0x00070000) >> 16;
u32 mthd = (addr & 0x00001ffc);
- u32 data = nv_rd32(priv, 0x40085c);
- u32 class = nv_rd32(priv, 0x400814);
+ u32 data = nv_rd32(gr, 0x40085c);
+ u32 class = nv_rd32(gr, 0x400814);
- nv_error(priv, "TRAP DISPATCH_QUERY\n");
+ nv_error(gr, "TRAP DISPATCH_QUERY\n");
if (display && (addr & 0x80000000)) {
- nv_error(priv,
+ nv_error(gr,
"ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n",
chid, inst,
nvkm_client_name(engctx), subc,
class, mthd, data, addr);
} else
if (display) {
- nv_error(priv, "no stuck command?\n");
+ nv_error(gr, "no stuck command?\n");
}
- nv_wr32(priv, 0x40084c, 0);
+ nv_wr32(gr, 0x40084c, 0);
ustatus &= ~0x00000002;
}
if (ustatus && display) {
- nv_error(priv, "TRAP_DISPATCH (unknown "
+ nv_error(gr, "TRAP_DISPATCH (unknown "
"0x%08x)\n", ustatus);
}
- nv_wr32(priv, 0x400804, 0xc0000000);
- nv_wr32(priv, 0x400108, 0x001);
+ nv_wr32(gr, 0x400804, 0xc0000000);
+ nv_wr32(gr, 0x400108, 0x001);
status &= ~0x001;
if (!status)
return 0;
/* M2MF: Memory to memory copy engine. */
if (status & 0x002) {
- u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff;
+ u32 ustatus = nv_rd32(gr, 0x406800) & 0x7fffffff;
if (display) {
- nv_error(priv, "TRAP_M2MF");
+ nv_error(gr, "TRAP_M2MF");
nvkm_bitfield_print(nv50_gr_trap_m2mf, ustatus);
pr_cont("\n");
- nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n",
- nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808),
- nv_rd32(priv, 0x40680c), nv_rd32(priv, 0x406810));
+ nv_error(gr, "TRAP_M2MF %08x %08x %08x %08x\n",
+ nv_rd32(gr, 0x406804), nv_rd32(gr, 0x406808),
+ nv_rd32(gr, 0x40680c), nv_rd32(gr, 0x406810));
}
/* No sane way found yet -- just reset the bugger. */
- nv_wr32(priv, 0x400040, 2);
- nv_wr32(priv, 0x400040, 0);
- nv_wr32(priv, 0x406800, 0xc0000000);
- nv_wr32(priv, 0x400108, 0x002);
+ nv_wr32(gr, 0x400040, 2);
+ nv_wr32(gr, 0x400040, 0);
+ nv_wr32(gr, 0x406800, 0xc0000000);
+ nv_wr32(gr, 0x400108, 0x002);
status &= ~0x002;
}
/* VFETCH: Fetches data from vertex buffers. */
if (status & 0x004) {
- u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff;
+ u32 ustatus = nv_rd32(gr, 0x400c04) & 0x7fffffff;
if (display) {
- nv_error(priv, "TRAP_VFETCH");
+ nv_error(gr, "TRAP_VFETCH");
nvkm_bitfield_print(nv50_gr_trap_vfetch, ustatus);
pr_cont("\n");
- nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n",
- nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08),
- nv_rd32(priv, 0x400c0c), nv_rd32(priv, 0x400c10));
+ nv_error(gr, "TRAP_VFETCH %08x %08x %08x %08x\n",
+ nv_rd32(gr, 0x400c00), nv_rd32(gr, 0x400c08),
+ nv_rd32(gr, 0x400c0c), nv_rd32(gr, 0x400c10));
}
- nv_wr32(priv, 0x400c04, 0xc0000000);
- nv_wr32(priv, 0x400108, 0x004);
+ nv_wr32(gr, 0x400c04, 0xc0000000);
+ nv_wr32(gr, 0x400108, 0x004);
status &= ~0x004;
}
/* STRMOUT: DirectX streamout / OpenGL transform feedback. */
if (status & 0x008) {
- ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff;
+ ustatus = nv_rd32(gr, 0x401800) & 0x7fffffff;
if (display) {
- nv_error(priv, "TRAP_STRMOUT");
+ nv_error(gr, "TRAP_STRMOUT");
nvkm_bitfield_print(nv50_gr_trap_strmout, ustatus);
pr_cont("\n");
- nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n",
- nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808),
- nv_rd32(priv, 0x40180c), nv_rd32(priv, 0x401810));
+ nv_error(gr, "TRAP_STRMOUT %08x %08x %08x %08x\n",
+ nv_rd32(gr, 0x401804), nv_rd32(gr, 0x401808),
+ nv_rd32(gr, 0x40180c), nv_rd32(gr, 0x401810));
}
/* No sane way found yet -- just reset the bugger. */
- nv_wr32(priv, 0x400040, 0x80);
- nv_wr32(priv, 0x400040, 0);
- nv_wr32(priv, 0x401800, 0xc0000000);
- nv_wr32(priv, 0x400108, 0x008);
+ nv_wr32(gr, 0x400040, 0x80);
+ nv_wr32(gr, 0x400040, 0);
+ nv_wr32(gr, 0x401800, 0xc0000000);
+ nv_wr32(gr, 0x400108, 0x008);
status &= ~0x008;
}
/* CCACHE: Handles code and c[] caches and fills them. */
if (status & 0x010) {
- ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff;
+ ustatus = nv_rd32(gr, 0x405018) & 0x7fffffff;
if (display) {
- nv_error(priv, "TRAP_CCACHE");
+ nv_error(gr, "TRAP_CCACHE");
nvkm_bitfield_print(nv50_gr_trap_ccache, ustatus);
pr_cont("\n");
- nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x"
+ nv_error(gr, "TRAP_CCACHE %08x %08x %08x %08x"
" %08x %08x %08x\n",
- nv_rd32(priv, 0x405000), nv_rd32(priv, 0x405004),
- nv_rd32(priv, 0x405008), nv_rd32(priv, 0x40500c),
- nv_rd32(priv, 0x405010), nv_rd32(priv, 0x405014),
- nv_rd32(priv, 0x40501c));
+ nv_rd32(gr, 0x405000), nv_rd32(gr, 0x405004),
+ nv_rd32(gr, 0x405008), nv_rd32(gr, 0x40500c),
+ nv_rd32(gr, 0x405010), nv_rd32(gr, 0x405014),
+ nv_rd32(gr, 0x40501c));
}
- nv_wr32(priv, 0x405018, 0xc0000000);
- nv_wr32(priv, 0x400108, 0x010);
+ nv_wr32(gr, 0x405018, 0xc0000000);
+ nv_wr32(gr, 0x400108, 0x010);
status &= ~0x010;
}
* remaining, so try to handle it anyway. Perhaps related to that
* unknown DMA slot on tesla? */
if (status & 0x20) {
- ustatus = nv_rd32(priv, 0x402000) & 0x7fffffff;
+ ustatus = nv_rd32(gr, 0x402000) & 0x7fffffff;
if (display)
- nv_error(priv, "TRAP_UNKC04 0x%08x\n", ustatus);
- nv_wr32(priv, 0x402000, 0xc0000000);
+ nv_error(gr, "TRAP_UNKC04 0x%08x\n", ustatus);
+ nv_wr32(gr, 0x402000, 0xc0000000);
/* no status modifiction on purpose */
}
/* TEXTURE: CUDA texturing units */
if (status & 0x040) {
- nv50_priv_tp_trap(priv, 6, 0x408900, 0x408600, display,
+ nv50_gr_tp_trap(gr, 6, 0x408900, 0x408600, display,
"TRAP_TEXTURE");
- nv_wr32(priv, 0x400108, 0x040);
+ nv_wr32(gr, 0x400108, 0x040);
status &= ~0x040;
}
/* MP: CUDA execution engines. */
if (status & 0x080) {
- nv50_priv_tp_trap(priv, 7, 0x408314, 0x40831c, display,
+ nv50_gr_tp_trap(gr, 7, 0x408314, 0x40831c, display,
"TRAP_MP");
- nv_wr32(priv, 0x400108, 0x080);
+ nv_wr32(gr, 0x400108, 0x080);
status &= ~0x080;
}
/* PROP: Handles TP-initiated uncached memory accesses:
* l[], g[], stack, 2d surfaces, render targets. */
if (status & 0x100) {
- nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display,
+ nv50_gr_tp_trap(gr, 8, 0x408e08, 0x408708, display,
"TRAP_PROP");
- nv_wr32(priv, 0x400108, 0x100);
+ nv_wr32(gr, 0x400108, 0x100);
status &= ~0x100;
}
if (status) {
if (display)
- nv_error(priv, "TRAP: unknown 0x%08x\n", status);
- nv_wr32(priv, 0x400108, status);
+ nv_error(gr, "TRAP: unknown 0x%08x\n", status);
+ nv_wr32(gr, 0x400108, status);
}
return 1;
struct nvkm_engine *engine = nv_engine(subdev);
struct nvkm_object *engctx;
struct nvkm_handle *handle = NULL;
- struct nv50_gr_priv *priv = (void *)subdev;
- u32 stat = nv_rd32(priv, 0x400100);
- u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff;
- u32 addr = nv_rd32(priv, 0x400704);
+ struct nv50_gr *gr = (void *)subdev;
+ u32 stat = nv_rd32(gr, 0x400100);
+ u32 inst = nv_rd32(gr, 0x40032c) & 0x0fffffff;
+ u32 addr = nv_rd32(gr, 0x400704);
u32 subc = (addr & 0x00070000) >> 16;
u32 mthd = (addr & 0x00001ffc);
- u32 data = nv_rd32(priv, 0x400708);
- u32 class = nv_rd32(priv, 0x400814);
+ u32 data = nv_rd32(gr, 0x400708);
+ u32 class = nv_rd32(gr, 0x400814);
u32 show = stat, show_bitfield = stat;
int chid;
}
if (show & 0x00100000) {
- u32 ecode = nv_rd32(priv, 0x400110);
- nv_error(priv, "DATA_ERROR ");
+ u32 ecode = nv_rd32(gr, 0x400110);
+ nv_error(gr, "DATA_ERROR ");
nvkm_enum_print(nv50_data_error_names, ecode);
pr_cont("\n");
show_bitfield &= ~0x00100000;
}
if (stat & 0x00200000) {
- if (!nv50_gr_trap_handler(priv, show, chid, (u64)inst << 12,
+ if (!nv50_gr_trap_handler(gr, show, chid, (u64)inst << 12,
engctx))
show &= ~0x00200000;
show_bitfield &= ~0x00200000;
}
- nv_wr32(priv, 0x400100, stat);
- nv_wr32(priv, 0x400500, 0x00010001);
+ nv_wr32(gr, 0x400100, stat);
+ nv_wr32(gr, 0x400500, 0x00010001);
if (show) {
show &= show_bitfield;
if (show) {
- nv_error(priv, "%s", "");
+ nv_error(gr, "%s", "");
nvkm_bitfield_print(nv50_gr_intr_name, show);
pr_cont("\n");
}
- nv_error(priv,
+ nv_error(gr,
"ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, (u64)inst << 12, nvkm_client_name(engctx),
subc, class, mthd, data);
}
- if (nv_rd32(priv, 0x400824) & (1 << 31))
- nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31));
+ if (nv_rd32(gr, 0x400824) & (1 << 31))
+ nv_wr32(gr, 0x400824, nv_rd32(gr, 0x400824) & ~(1 << 31));
nvkm_engctx_put(engctx);
}
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
- struct nv50_gr_priv *priv;
+ struct nv50_gr *gr;
int ret;
- ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
- *pobject = nv_object(priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
+ *pobject = nv_object(gr);
if (ret)
return ret;
- nv_subdev(priv)->unit = 0x00201000;
- nv_subdev(priv)->intr = nv50_gr_intr;
- nv_engine(priv)->cclass = &nv50_gr_cclass;
+ nv_subdev(gr)->unit = 0x00201000;
+ nv_subdev(gr)->intr = nv50_gr_intr;
+ nv_engine(gr)->cclass = &nv50_gr_cclass;
- priv->base.units = nv50_gr_units;
+ gr->base.units = nv50_gr_units;
- switch (nv_device(priv)->chipset) {
+ switch (nv_device(gr)->chipset) {
case 0x50:
- nv_engine(priv)->sclass = nv50_gr_sclass;
+ nv_engine(gr)->sclass = nv50_gr_sclass;
break;
case 0x84:
case 0x86:
case 0x94:
case 0x96:
case 0x98:
- nv_engine(priv)->sclass = g84_gr_sclass;
+ nv_engine(gr)->sclass = g84_gr_sclass;
break;
case 0xa0:
case 0xaa:
case 0xac:
- nv_engine(priv)->sclass = gt200_gr_sclass;
+ nv_engine(gr)->sclass = gt200_gr_sclass;
break;
case 0xa3:
case 0xa5:
case 0xa8:
- nv_engine(priv)->sclass = gt215_gr_sclass;
+ nv_engine(gr)->sclass = gt215_gr_sclass;
break;
case 0xaf:
- nv_engine(priv)->sclass = mcp89_gr_sclass;
+ nv_engine(gr)->sclass = mcp89_gr_sclass;
break;
}
/* unfortunate hw bug workaround... */
- if (nv_device(priv)->chipset != 0x50 &&
- nv_device(priv)->chipset != 0xac)
- nv_engine(priv)->tlb_flush = g84_gr_tlb_flush;
+ if (nv_device(gr)->chipset != 0x50 &&
+ nv_device(gr)->chipset != 0xac)
+ nv_engine(gr)->tlb_flush = g84_gr_tlb_flush;
- spin_lock_init(&priv->lock);
+ spin_lock_init(&gr->lock);
return 0;
}
static int
nv50_gr_init(struct nvkm_object *object)
{
- struct nv50_gr_priv *priv = (void *)object;
+ struct nv50_gr *gr = (void *)object;
int ret, units, i;
- ret = nvkm_gr_init(&priv->base);
+ ret = nvkm_gr_init(&gr->base);
if (ret)
return ret;
/* NV_PGRAPH_DEBUG_3_HW_CTX_SWITCH_ENABLED */
- nv_wr32(priv, 0x40008c, 0x00000004);
+ nv_wr32(gr, 0x40008c, 0x00000004);
/* reset/enable traps and interrupts */
- nv_wr32(priv, 0x400804, 0xc0000000);
- nv_wr32(priv, 0x406800, 0xc0000000);
- nv_wr32(priv, 0x400c04, 0xc0000000);
- nv_wr32(priv, 0x401800, 0xc0000000);
- nv_wr32(priv, 0x405018, 0xc0000000);
- nv_wr32(priv, 0x402000, 0xc0000000);
-
- units = nv_rd32(priv, 0x001540);
+ nv_wr32(gr, 0x400804, 0xc0000000);
+ nv_wr32(gr, 0x406800, 0xc0000000);
+ nv_wr32(gr, 0x400c04, 0xc0000000);
+ nv_wr32(gr, 0x401800, 0xc0000000);
+ nv_wr32(gr, 0x405018, 0xc0000000);
+ nv_wr32(gr, 0x402000, 0xc0000000);
+
+ units = nv_rd32(gr, 0x001540);
for (i = 0; i < 16; i++) {
if (!(units & (1 << i)))
continue;
- if (nv_device(priv)->chipset < 0xa0) {
- nv_wr32(priv, 0x408900 + (i << 12), 0xc0000000);
- nv_wr32(priv, 0x408e08 + (i << 12), 0xc0000000);
- nv_wr32(priv, 0x408314 + (i << 12), 0xc0000000);
+ if (nv_device(gr)->chipset < 0xa0) {
+ nv_wr32(gr, 0x408900 + (i << 12), 0xc0000000);
+ nv_wr32(gr, 0x408e08 + (i << 12), 0xc0000000);
+ nv_wr32(gr, 0x408314 + (i << 12), 0xc0000000);
} else {
- nv_wr32(priv, 0x408600 + (i << 11), 0xc0000000);
- nv_wr32(priv, 0x408708 + (i << 11), 0xc0000000);
- nv_wr32(priv, 0x40831c + (i << 11), 0xc0000000);
+ nv_wr32(gr, 0x408600 + (i << 11), 0xc0000000);
+ nv_wr32(gr, 0x408708 + (i << 11), 0xc0000000);
+ nv_wr32(gr, 0x40831c + (i << 11), 0xc0000000);
}
}
- nv_wr32(priv, 0x400108, 0xffffffff);
- nv_wr32(priv, 0x400138, 0xffffffff);
- nv_wr32(priv, 0x400100, 0xffffffff);
- nv_wr32(priv, 0x40013c, 0xffffffff);
- nv_wr32(priv, 0x400500, 0x00010001);
+ nv_wr32(gr, 0x400108, 0xffffffff);
+ nv_wr32(gr, 0x400138, 0xffffffff);
+ nv_wr32(gr, 0x400100, 0xffffffff);
+ nv_wr32(gr, 0x40013c, 0xffffffff);
+ nv_wr32(gr, 0x400500, 0x00010001);
/* upload context program, initialise ctxctl defaults */
- ret = nv50_grctx_init(nv_device(priv), &priv->size);
+ ret = nv50_grctx_init(nv_device(gr), &gr->size);
if (ret)
return ret;
- nv_wr32(priv, 0x400824, 0x00000000);
- nv_wr32(priv, 0x400828, 0x00000000);
- nv_wr32(priv, 0x40082c, 0x00000000);
- nv_wr32(priv, 0x400830, 0x00000000);
- nv_wr32(priv, 0x40032c, 0x00000000);
- nv_wr32(priv, 0x400330, 0x00000000);
+ nv_wr32(gr, 0x400824, 0x00000000);
+ nv_wr32(gr, 0x400828, 0x00000000);
+ nv_wr32(gr, 0x40082c, 0x00000000);
+ nv_wr32(gr, 0x400830, 0x00000000);
+ nv_wr32(gr, 0x40032c, 0x00000000);
+ nv_wr32(gr, 0x400330, 0x00000000);
/* some unknown zcull magic */
- switch (nv_device(priv)->chipset & 0xf0) {
+ switch (nv_device(gr)->chipset & 0xf0) {
case 0x50:
case 0x80:
case 0x90:
- nv_wr32(priv, 0x402ca8, 0x00000800);
+ nv_wr32(gr, 0x402ca8, 0x00000800);
break;
case 0xa0:
default:
- if (nv_device(priv)->chipset == 0xa0 ||
- nv_device(priv)->chipset == 0xaa ||
- nv_device(priv)->chipset == 0xac) {
- nv_wr32(priv, 0x402ca8, 0x00000802);
+ if (nv_device(gr)->chipset == 0xa0 ||
+ nv_device(gr)->chipset == 0xaa ||
+ nv_device(gr)->chipset == 0xac) {
+ nv_wr32(gr, 0x402ca8, 0x00000802);
} else {
- nv_wr32(priv, 0x402cc0, 0x00000000);
- nv_wr32(priv, 0x402ca8, 0x00000002);
+ nv_wr32(gr, 0x402cc0, 0x00000000);
+ nv_wr32(gr, 0x402ca8, 0x00000002);
}
break;
/* zero out zcull regions */
for (i = 0; i < 8; i++) {
- nv_wr32(priv, 0x402c20 + (i * 0x10), 0x00000000);
- nv_wr32(priv, 0x402c24 + (i * 0x10), 0x00000000);
- nv_wr32(priv, 0x402c28 + (i * 0x10), 0x00000000);
- nv_wr32(priv, 0x402c2c + (i * 0x10), 0x00000000);
+ nv_wr32(gr, 0x402c20 + (i * 0x10), 0x00000000);
+ nv_wr32(gr, 0x402c24 + (i * 0x10), 0x00000000);
+ nv_wr32(gr, 0x402c28 + (i * 0x10), 0x00000000);
+ nv_wr32(gr, 0x402c2c + (i * 0x10), 0x00000000);
}
return 0;
}
projects / firefly-linux-kernel-4.4.55.git / commitdiff