drm/i915: Initialize new chv primary plane and pipe blender registers

CHV adds a bunch of new registers for primary plane size/position and
pipe blender setup. Initialize all those registers to avoid nasty
surprises. PRIMSIZE is especially important as without programming it
the outout will be garbled whenever the primary plane size would not
match what the BIOS set up.

Also program the sprite constant alpha register to disable the constant
alpha blending factor. This applies to vlv as well as chv.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ea84e1ec5e5f23e4d35726c0c4d4e577987572b2..a9a861798ff57e2946a221befda73ec695a5ff7a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4272,9 +4272,11 @@ enum punit_power_well {
 #define   DISPPLANE_NO_LINE_DOUBLE             0
 #define   DISPPLANE_STEREO_POLARITY_FIRST      0
 #define   DISPPLANE_STEREO_POLARITY_SECOND     (1<<18)
-#define   DISPPLANE_ROTATE_180         (1<<15)
+#define   DISPPLANE_ALPHA_PREMULTIPLY          (1<<16) /* CHV pipe B */
+#define   DISPPLANE_ROTATE_180                 (1<<15)
 #define   DISPPLANE_TRICKLE_FEED_DISABLE       (1<<14) /* Ironlake */
 #define   DISPPLANE_TILED                      (1<<10)
+#define   DISPPLANE_MIRROR                     (1<<8) /* CHV pipe B */
 #define _DSPAADDR                              0x70184
 #define _DSPASTRIDE                            0x70188
 #define _DSPAPOS                               0x7018C /* reserved */
@@ -4295,6 +4297,24 @@ enum punit_power_well {
 #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
 #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
 
+/* CHV pipe B blender and primary plane */
+#define _CHV_BLEND_A           0x60a00
+#define   CHV_BLEND_LEGACY             (0<<30)
+#define   CHV_BLEND_ANDROID            (1<<30)
+#define   CHV_BLEND_MPO                        (2<<30)
+#define   CHV_BLEND_MASK               (3<<30)
+#define _CHV_CANVAS_A          0x60a04
+#define _PRIMPOS_A             0x60a08
+#define _PRIMSIZE_A            0x60a0c
+#define _PRIMCNSTALPHA_A       0x60a10
+#define   PRIM_CONST_ALPHA_ENABLE      (1<<31)
+
+#define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A)
+#define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A)
+#define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A)
+#define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A)
+#define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A)
+
 /* Display/Sprite base address macros */
 #define DISP_BASEADDR_MASK     (0xfffff000)
 #define I915_LO_DISPBASE(val)  (val & ~DISP_BASEADDR_MASK)
@@ -4496,6 +4516,7 @@ enum punit_power_well {
 #define   SP_FORMAT_RGBA1010102                (9<<26)
 #define   SP_FORMAT_RGBX8888           (0xe<<26)
 #define   SP_FORMAT_RGBA8888           (0xf<<26)
+#define   SP_ALPHA_PREMULTIPLY         (1<<23) /* CHV pipe B */
 #define   SP_SOURCE_KEY                        (1<<22)
 #define   SP_YUV_BYTE_ORDER_MASK       (3<<16)
 #define   SP_YUV_ORDER_YUYV            (0<<16)
@@ -4504,6 +4525,7 @@ enum punit_power_well {
 #define   SP_YUV_ORDER_VYUY            (3<<16)
 #define   SP_ROTATE_180                        (1<<15)
 #define   SP_TILED                     (1<<10)
+#define   SP_MIRROR                    (1<<8) /* CHV pipe B */
 #define _SPALINOFF             (VLV_DISPLAY_BASE + 0x72184)
 #define _SPASTRIDE             (VLV_DISPLAY_BASE + 0x72188)
 #define _SPAPOS                        (VLV_DISPLAY_BASE + 0x7218c)
@@ -4514,6 +4536,7 @@ enum punit_power_well {
 #define _SPAKEYMAXVAL          (VLV_DISPLAY_BASE + 0x721a0)
 #define _SPATILEOFF            (VLV_DISPLAY_BASE + 0x721a4)
 #define _SPACONSTALPHA         (VLV_DISPLAY_BASE + 0x721a8)
+#define   SP_CONST_ALPHA_ENABLE                (1<<31)
 #define _SPAGAMC               (VLV_DISPLAY_BASE + 0x721f4)
 
 #define _SPBCNTR               (VLV_DISPLAY_BASE + 0x72280)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d678bc0c81844b26c9087ea172dc5aacc5a130fc..c17ec502b0872b02c84615197733a8dbccce8a9f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2451,6 +2451,12 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
                           ((intel_crtc->config.pipe_src_h - 1) << 16) |
                           (intel_crtc->config.pipe_src_w - 1));
                I915_WRITE(DSPPOS(plane), 0);
+       } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
+               I915_WRITE(PRIMSIZE(plane),
+                          ((intel_crtc->config.pipe_src_h - 1) << 16) |
+                          (intel_crtc->config.pipe_src_w - 1));
+               I915_WRITE(PRIMPOS(plane), 0);
+               I915_WRITE(PRIMCNSTALPHA(plane), 0);
        }
 
        switch (fb->pixel_format) {
@@ -4856,6 +4862,13 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 
        intel_set_pipe_timings(intel_crtc);
 
+       if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
+               struct drm_i915_private *dev_priv = dev->dev_private;
+
+               I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
+               I915_WRITE(CHV_CANVAS(pipe), 0);
+       }
+
        i9xx_set_pipeconf(intel_crtc);
 
        intel_crtc->active = true;

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 8b80d68619afabcedc452f67f0d352f0a2da7387..4912161c95b3183165e5227fd3e2a5b0efb9e95a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -438,6 +438,8 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
        else
                I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
 
+       I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
+
        I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
        I915_WRITE(SPCNTR(pipe, plane), sprctl);
        I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +