ARM: allow predicated barriers in Thumb mode

The barrier instructions are only "always-execute" in ARM mode, they can quite
happily sit inside an IT block in Thumb.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184964 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 5448ee3457dda3360a61818987acef3069926ef4..3b18df085654626c79b3c9ea5b5f4f54f09ac003 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -3136,26 +3136,24 @@ def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
 
 // memory barriers protect the atomic sequences
 let hasSideEffects = 1 in {
-def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
-                  "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
-                  Requires<[IsThumb, HasDB]> {
+def t2DMB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
+                "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
+                Requires<[HasDB]> {
   bits<4> opt;
   let Inst{31-4} = 0xf3bf8f5;
   let Inst{3-0} = opt;
 }
 }
 
-def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
-                  "dsb", "\t$opt", []>,
-                  Requires<[IsThumb, HasDB]> {
+def t2DSB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
+                "dsb", "\t$opt", []>, Requires<[HasDB]> {
   bits<4> opt;
   let Inst{31-4} = 0xf3bf8f4;
   let Inst{3-0} = opt;
 }
 
-def t2ISB : AInoP<(outs), (ins instsyncb_opt:$opt), ThumbFrm, NoItinerary,
-                  "isb", "\t$opt",
-                  []>, Requires<[IsThumb, HasDB]> {
+def t2ISB : T2I<(outs), (ins instsyncb_opt:$opt), NoItinerary,
+                "isb", "\t$opt", []>, Requires<[HasDB]> {
   bits<4> opt;
   let Inst{31-4} = 0xf3bf8f6;
   let Inst{3-0} = opt;
@@ -4141,9 +4139,9 @@ def : t2InstAlias<"tst${p} $Rn, $Rm",
                   (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
 
 // Memory barriers
-def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb, HasDB]>;
-def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb, HasDB]>;
-def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb, HasDB]>;
+def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p)>, Requires<[IsThumb2, HasDB]>;
+def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p)>, Requires<[IsThumb2, HasDB]>;
+def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p)>, Requires<[IsThumb2, HasDB]>;
 
 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
 // width specifier.

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 647fdb396d7f9f4c9e71ea210ff170c20301de97..f80fba610286b30d4a407c58bfcbd8bed612c0ec 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -4966,12 +4966,12 @@ getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
   } else
     CanAcceptCarrySet = false;
 
-  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
-      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
-      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
-      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
-      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
-      (Mnemonic == "clrex" && !isThumb()) ||
+  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "cps" ||
+      Mnemonic == "mcr2" || Mnemonic == "it" || Mnemonic == "mcrr2" ||
+      Mnemonic == "cbz" || Mnemonic == "cdp2" || Mnemonic == "trap" ||
+      Mnemonic == "mrc2" || Mnemonic == "mrrc2" || Mnemonic == "setend" ||
+      ((Mnemonic == "clrex" ||  Mnemonic == "dmb" || Mnemonic == "dsb" ||
+       Mnemonic == "isb") && !isThumb()) ||
       (Mnemonic == "nop" && isThumbOne()) ||
       ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
         Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||

diff --git a/test/CodeGen/Thumb2/thumb2-branch.ll b/test/CodeGen/Thumb2/thumb2-branch.ll
index f1c097c1892d2824852e4e9e5ee858f0f11e178b..5e3a7d1c95ca6440ff974b61b49e95812023c66e 100644 (file)
--- a/test/CodeGen/Thumb2/thumb2-branch.ll
+++ b/test/CodeGen/Thumb2/thumb2-branch.ll
@@ -1,8 +1,10 @@
 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
-; If-conversion defeats the purpose of this test, which is to check conditional
-; branch generation, so use memory barrier instruction to make sure it doesn't
+; If-conversion defeats the purpose of this test, which is to check
+; conditional branch generation, so a call to make sure it doesn't
 ; happen and we get actual branches.
 
+declare void @foo()
+
 define i32 @f1(i32 %a, i32 %b, i32* %v) {
 entry:
 ; CHECK: f1:
@@ -11,12 +13,12 @@ entry:
         br i1 %tmp, label %cond_true, label %return
 
 cond_true:              ; preds = %entry
-        fence seq_cst
+        call void @foo()
         store i32 0, i32* %v
         ret i32 0
 
 return:         ; preds = %entry
-        fence seq_cst
+        call void @foo()
         ret i32 1
 }
 
@@ -28,12 +30,12 @@ entry:
         br i1 %tmp, label %cond_true, label %return
 
 cond_true:              ; preds = %entry
-        fence seq_cst
+        call void @foo()
         store i32 0, i32* %v
         ret i32 0
 
 return:         ; preds = %entry
-        fence seq_cst
+        call void @foo()
         ret i32 1
 }
 
@@ -45,12 +47,12 @@ entry:
         br i1 %tmp, label %cond_true, label %return
 
 cond_true:              ; preds = %entry
-        fence seq_cst
+        call void @foo()
         store i32 0, i32* %v
         ret i32 0
 
 return:         ; preds = %entry
-        fence seq_cst
+        call void @foo()
         ret i32 1
 }
 
@@ -62,11 +64,11 @@ entry:
         br i1 %tmp, label %cond_true, label %return
 
 cond_true:              ; preds = %entry
-        fence seq_cst
+        call void @foo()
         store i32 0, i32* %v
         ret i32 0
 
 return:         ; preds = %entry
-        fence seq_cst
+        call void @foo()
         ret i32 1
 }

diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s
index 82d6ae34655db1a1681f76daeb3c234f5b3f98d3..21fda1cce17e6ac91154aec4e59017ad4bb87ba2 100644 (file)
--- a/test/MC/ARM/diagnostics.s
+++ b/test/MC/ARM/diagnostics.s
@@ -379,3 +379,17 @@
 
         nop.n
 @ CHECK-ERRORS: error: instruction with .n (narrow) qualifier not allowed in arm mode
+
+       dmbeq #5
+       dsble #15
+       isblo #7
+@ CHECK-ERRORS: error: instruction 'dmb' is not predicable, but condition code specified
+@ CHECK-ERRORS: error: instruction 'dsb' is not predicable, but condition code specified
+@ CHECK-ERRORS: error: instruction 'isb' is not predicable, but condition code specified
+
+       dmblt
+       dsbne
+       isbeq
+@ CHECK-ERRORS: error: instruction 'dmb' is not predicable, but condition code specified
+@ CHECK-ERRORS: error: instruction 'dsb' is not predicable, but condition code specified
+@ CHECK-ERRORS: error: instruction 'isb' is not predicable, but condition code specified

diff --git a/test/MC/ARM/thumb-only-conditionals.s b/test/MC/ARM/thumb-only-conditionals.s
new file mode 100644 (file)
index 0000000..55b2cf4
--- /dev/null
+++ b/test/MC/ARM/thumb-only-conditionals.s
@@ -0,0 +1,19 @@
+@ RUN: llvm-mc -triple=thumbv7-apple-ios -o - %s | FileCheck %s
+
+        itte eq
+        dmbeq #11
+        dsbeq #7
+        isbne #15
+@ CHECK: itte eq
+@ CHECK-NEXT: dmbeq ish
+@ CHECK-NEXT: dsbeq nsh
+@ CHECK-NEXT: isbne sy
+
+        itet le
+        dmble
+        dsbgt
+        isble
+@ CHECK: itet le
+@ CHECK-NEXT: dmble sy
+@ CHECK-NEXT: dsbgt sy
+@ CHECK-NEXT: isble sy