case Hexagon::ADD_ri:
return isInt<8>(MI->getOperand(2).getImm());
- case Hexagon::ASLH:
+ case Hexagon::A2_aslh:
case Hexagon::ASRH:
case Hexagon::A2_sxtb:
case Hexagon::A2_sxth:
case Hexagon::A2_pandfnew:
case Hexagon::A2_pandt:
case Hexagon::A2_pandtnew:
+ case Hexagon::A4_paslhf:
+ case Hexagon::A4_paslhfnew:
+ case Hexagon::A4_paslht:
+ case Hexagon::A4_paslhtnew:
case Hexagon::A2_porf:
case Hexagon::A2_porfnew:
case Hexagon::A2_port:
case Hexagon::COMBINE_rr_cPt:
case Hexagon::COMBINE_rr_cNotPt:
return true;
- case Hexagon::ASLH_cPt_V4:
- case Hexagon::ASLH_cNotPt_V4:
case Hexagon::ASRH_cPt_V4:
case Hexagon::ASRH_cNotPt_V4:
return QRI.Subtarget.hasV4TOps();
}
}
+defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
}
}
-defm ASLH : ALU32_2op_base2<"aslh">, PredNewRel;
defm ASRH : ALU32_2op_base2<"asrh">, PredNewRel;
def : Pat <(shl (i32 IntRegs:$src1), (i32 16)),
- (ASLH IntRegs:$src1)>;
+ (A2_aslh IntRegs:$src1)>;
def : Pat <(sra (i32 IntRegs:$src1), (i32 16)),
(ASRH IntRegs:$src1)>;
--- /dev/null
+;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
+;; RUN: | llvm-objdump -s - | FileCheck %s
+
+define i32 @foo (i32 %a)
+{
+ %1 = shl i32 %a, 16
+ ret i32 %1
+}
+
+; CHECK: 0000 00400070 00c09f52
\ No newline at end of file