UPSTREAM: PCI: rockchip: fix wrong negotiated lanes calculation

The calculation of negotiated lanes is wrong since it should
be shifted by PCIE_CORE_PL_CONF_LANE_SHIFT, but it is shifted
by PCIE_CORE_PL_CONF_LANE_MASK. Let's fix it.

Change-Id: I164d07c86e944fdab7c1a3100c87fdd24ec0ee82
Fixes: commit e77f847df54c ("PCI: rockchip: Add Rockchip PCIe controller support")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(am from git.kernel.org/cgit/linux/kernel/git/next/linux-next.git
commit 898a2301cf002e1d96c0d56e41131a0d57cacb65)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index f204f8b60b00f9c63d50821a143dd09b9dd2f3e9..fd8620f92cae9586d3f28b96bcce19826188665b 100644 (file)
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -595,8 +595,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 
        /* Check the final link width from negotiated lane counter from MGMT */
        status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
-       status =  0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
-                         PCIE_CORE_PL_CONF_LANE_MASK);
+       status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
+                         PCIE_CORE_PL_CONF_LANE_SHIFT);
        dev_dbg(dev, "current link width is x%d\n", status);
 
        rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,