Move the machine operand MC encoding patterns to the parent classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117956 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index 4ec6ad7e0c66dccfb303601453cf6034d293b945..e3a547fadf0abaf12014ed1e268998936ae96496 100644 (file)
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -1573,6 +1573,19 @@ class ADbI_vmlX<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
            dag iops, InstrItinClass itin, string opc, string asm,
            list<dag> pattern>
   : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
+  // Instruction operands.
+  bits<5> Dd;
+  bits<5> Dn;
+  bits<5> Dm;
+
+  // Encode instruction operands.
+  let Inst{19-16} = Dn{3-0};
+  let Inst{7}     = Dn{4};
+  let Inst{15-12} = Dd{3-0};
+  let Inst{22}    = Dd{4};
+  let Inst{3-0}   = Dm{3-0};
+  let Inst{5}     = Dm{4};
+
   let Inst{27-23} = opcod1;
   let Inst{21-20} = opcod2;
   let Inst{11-9}  = 0b101;

diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index 729712c76447f31da0ce28e33ea056355a61c384..8e1f891cf15204ae2b1d0f80f0765c8ef2e5c9f6 100644 (file)
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -728,30 +728,12 @@ def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1,
 // FP FMA Operations.
 //
 
-class ADbI_vmlX_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4,
-                       dag oops, dag iops, InstrItinClass itin, string opc,
-                       string asm, list<dag> pattern>
-  : ADbI_vmlX<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
-  // Instruction operands.
-  bits<5> Dd;
-  bits<5> Dn;
-  bits<5> Dm;
-
-  // Encode instruction operands.
-  let Inst{19-16} = Dn{3-0};
-  let Inst{7}     = Dn{4};
-  let Inst{15-12} = Dd{3-0};
-  let Inst{22}    = Dd{4};
-  let Inst{3-0}   = Dm{3-0};
-  let Inst{5}     = Dm{4};
-}
-
-def VMLAD : ADbI_vmlX_Encode<0b11100, 0b00, 0, 0,
-                             (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
-                             IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
-                             [(set DPR:$Dd, (fadd (fmul DPR:$Dn, DPR:$Dm),
-                                                  (f64 DPR:$Ddin)))]>,
-                             RegConstraint<"$Ddin = $Dd">;
+def VMLAD : ADbI_vmlX<0b11100, 0b00, 0, 0,
+                      (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
+                      IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
+                      [(set DPR:$Dd, (fadd (fmul DPR:$Dn, DPR:$Dm),
+                                           (f64 DPR:$Ddin)))]>,
+              RegConstraint<"$Ddin = $Dd">;
 
 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
                   (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
@@ -765,12 +747,12 @@ def : Pat<(fadd DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))),
 def : Pat<(fadd SPR:$dstin, (fmul SPR:$a, SPR:$b)),
           (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
 
-def VMLSD : ADbI_vmlX_Encode<0b11100, 0b00, 1, 0,
-                             (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
-                             IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
-                             [(set DPR:$Dd, (fadd (fneg (fmul DPR:$Dn,DPR:$Dm)),
-                                                        (f64 DPR:$Ddin)))]>,
-                             RegConstraint<"$Ddin = $Dd">;
+def VMLSD : ADbI_vmlX<0b11100, 0b00, 1, 0,
+                      (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
+                      IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
+                      [(set DPR:$Dd, (fadd (fneg (fmul DPR:$Dn,DPR:$Dm)),
+                                                 (f64 DPR:$Ddin)))]>,
+              RegConstraint<"$Ddin = $Dd">;
 
 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
                   (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
@@ -784,11 +766,11 @@ def : Pat<(fsub DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))),
 def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)),
           (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
 
-def VNMLAD : ADbI_vmlX_Encode<0b11100, 0b01, 1, 0,
-                              (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
-                              IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
-                              [(set DPR:$Dd,(fsub (fneg (fmul DPR:$Dn,DPR:$Dm)),
-                                                  (f64 DPR:$Ddin)))]>,
+def VNMLAD : ADbI_vmlX<0b11100, 0b01, 1, 0,
+                       (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
+                       IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
+                       [(set DPR:$Dd,(fsub (fneg (fmul DPR:$Dn,DPR:$Dm)),
+                                           (f64 DPR:$Ddin)))]>,
                 RegConstraint<"$Ddin = $Dd">;
 
 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
@@ -803,12 +785,12 @@ def : Pat<(fsub (fneg (fmul DPR:$a, (f64 DPR:$b))), DPR:$dstin),
 def : Pat<(fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin),
           (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
 
-def VNMLSD : ADbI_vmlX_Encode<0b11100, 0b01, 0, 0,
-                              (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
-                              IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
-                              [(set DPR:$Dd, (fsub (fmul DPR:$Dn, DPR:$Dm),
-                                                   (f64 DPR:$Ddin)))]>,
-                              RegConstraint<"$Ddin = $Dd">;
+def VNMLSD : ADbI_vmlX<0b11100, 0b01, 0, 0,
+                       (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
+                       IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
+                       [(set DPR:$Dd, (fsub (fmul DPR:$Dn, DPR:$Dm),
+                                            (f64 DPR:$Ddin)))]>,
+               RegConstraint<"$Ddin = $Dd">;
 
 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
                   (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),