Fix CodeGen/X86/inline-asm-x-scalar.ll:test4, by retaining regclass info

for tied register constraints.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37601 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index b29fb0d65ed24e98bf12bc614e0b6e5452a0ffdb..c9ed8b624736416207d9c508eb5325a218a87501 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3222,7 +3222,8 @@ GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
   // Otherwise, if this was a reference to an LLVM register class, create vregs
   // for this reference.
   std::vector<unsigned> RegClassRegs;
-  if (PhysReg.second) {
+  const TargetRegisterClass *RC = PhysReg.second;
+  if (RC) {
     // If this is an early clobber or tied register, our regalloc doesn't know
     // how to maintain the constraint.  If it isn't, go ahead and create vreg
     // and let the regalloc do the right thing.
@@ -3272,11 +3273,13 @@ GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
     
     // Check to see if this register is allocatable (i.e. don't give out the
     // stack pointer).
-    const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
-    if (!RC) {
-      // Make sure we find consecutive registers.
-      NumAllocated = 0;
-      continue;
+    if (RC == 0) {
+      RC = isAllocatableRegister(Reg, MF, TLI, MRI);
+      if (!RC) {        // Couldn't allocate this register.
+        // Reset NumAllocated to make sure we return consecutive registers.
+        NumAllocated = 0;
+        continue;
+      }
     }
     
     // Okay, this register is good, we can use it.