Thumb2 assembly parsing for MOV in IT block.

Select the right 16 vs. 32 bit encoding in an IT block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139714 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 614150dd09e08a87b0ea5c2d72e0204a2304cf21..dc310a183dc95df0c03d8e1b95adf9f5ce284463 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -3806,8 +3806,9 @@ processInstruction(MCInst &Inst,
     // request the 32-bit variant, transform it here.
     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
         Inst.getOperand(1).getImm() <= 255 &&
-        Inst.getOperand(2).getImm() == ARMCC::AL &&
-        Inst.getOperand(4).getReg() == ARM::CPSR &&
+        ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
+         Inst.getOperand(4).getReg() == ARM::CPSR) ||
+        (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
         (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
          static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
       // The operands aren't in the same order for tMOVi8...

diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s
index 5da74024bbdb7b817ef733579309b1c5f8e127c3..adedabd86429aab2127725a3780a6e77b4ab051b 100644 (file)
--- a/test/MC/ARM/basic-thumb2-instructions.s
+++ b/test/MC/ARM/basic-thumb2-instructions.s
@@ -1009,6 +1009,10 @@ _func:
         mov.w r0, #0x3fc0000
         mov r0, #0x3fc0000
         movs.w r0, #0x3fc0000
+        itte eq
+        movseq r1, #12
+        moveq r1, #12
+        movne.w r1, #12
 
 @ CHECK: movs  r1, #21                 @ encoding: [0x15,0x21]
 @ CHECK: movs.w        r1, #21                 @ encoding: [0x5f,0xf0,0x15,0x01]
@@ -1019,6 +1023,11 @@ _func:
 @ CHECK: mov.w r0, #66846720           @ encoding: [0x4f,0xf0,0x7f,0x70]
 @ CHECK: mov.w r0, #66846720           @ encoding: [0x4f,0xf0,0x7f,0x70]
 @ CHECK: movs.w        r0, #66846720           @ encoding: [0x5f,0xf0,0x7f,0x70]
+@ CHECK: itte  eq                      @ encoding: [0x06,0xbf]
+@ CHECK: movseq.w      r1, #12         @ encoding: [0x5f,0xf0,0x0c,0x01]
+@ CHECK: moveq r1, #12                 @ encoding: [0x0c,0x21]
+@ CHECK: movne.w r1, #12                @ encoding: [0x4f,0xf0,0x0c,0x01]
+
 
 
 @------------------------------------------------------------------------------