#include "comedi_fc.h"
/*
- * PCI BAR2 Register map (devpriv->mmio)
+ * PCI BAR2 Register map (dev->mmio)
*/
#define FIRMWARE_REV_REG 0x00
#define FEATURES_REG_PRESENT_BIT (1 << 15)
struct hpdi_private {
void __iomem *plx9080_mmio;
- void __iomem *mmio;
uint32_t *dio_buffer[NUM_DMA_BUFFERS]; /* dma buffers */
/* physical addresses of dma buffers */
dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];
if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
return IRQ_NONE;
- hpdi_intr_status = readl(devpriv->mmio + INTERRUPT_STATUS_REG);
- hpdi_board_status = readl(devpriv->mmio + BOARD_STATUS_REG);
+ hpdi_intr_status = readl(dev->mmio + INTERRUPT_STATUS_REG);
+ hpdi_board_status = readl(dev->mmio + BOARD_STATUS_REG);
if (hpdi_intr_status)
- writel(hpdi_intr_status, devpriv->mmio + INTERRUPT_STATUS_REG);
+ writel(hpdi_intr_status, dev->mmio + INTERRUPT_STATUS_REG);
/* spin lock makes sure no one else changes plx dma control reg */
spin_lock_irqsave(&dev->spinlock, flags);
static int gsc_hpdi_cancel(struct comedi_device *dev,
struct comedi_subdevice *s)
{
- struct hpdi_private *devpriv = dev->private;
-
- writel(0, devpriv->mmio + BOARD_CONTROL_REG);
- writel(0, devpriv->mmio + INTERRUPT_CONTROL_REG);
+ writel(0, dev->mmio + BOARD_CONTROL_REG);
+ writel(0, dev->mmio + INTERRUPT_CONTROL_REG);
gsc_hpdi_abort_dma(dev, 0);
if (s->io_bits)
return -EINVAL;
- writel(RX_FIFO_RESET_BIT, devpriv->mmio + BOARD_CONTROL_REG);
+ writel(RX_FIFO_RESET_BIT, dev->mmio + BOARD_CONTROL_REG);
gsc_hpdi_abort_dma(dev, 0);
devpriv->dio_count = 1;
/* clear over/under run status flags */
- writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT,
- devpriv->mmio + BOARD_STATUS_REG);
+ writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT, dev->mmio + BOARD_STATUS_REG);
/* enable interrupts */
- writel(RX_FULL_INTR, devpriv->mmio + INTERRUPT_CONTROL_REG);
+ writel(RX_FULL_INTR, dev->mmio + INTERRUPT_CONTROL_REG);
- writel(RX_ENABLE_BIT, devpriv->mmio + BOARD_CONTROL_REG);
+ writel(RX_ENABLE_BIT, dev->mmio + BOARD_CONTROL_REG);
return 0;
}
uint32_t plx_intcsr_bits;
/* wait 10usec after reset before accessing fifos */
- writel(BOARD_RESET_BIT, devpriv->mmio + BOARD_CONTROL_REG);
+ writel(BOARD_RESET_BIT, dev->mmio + BOARD_CONTROL_REG);
udelay(10);
writel(ALMOST_EMPTY_BITS(32) | ALMOST_FULL_BITS(32),
- devpriv->mmio + RX_PROG_ALMOST_REG);
+ dev->mmio + RX_PROG_ALMOST_REG);
writel(ALMOST_EMPTY_BITS(32) | ALMOST_FULL_BITS(32),
- devpriv->mmio + TX_PROG_ALMOST_REG);
+ dev->mmio + TX_PROG_ALMOST_REG);
- devpriv->tx_fifo_size = readl(devpriv->mmio + TX_FIFO_SIZE_REG) &
+ devpriv->tx_fifo_size = readl(dev->mmio + TX_FIFO_SIZE_REG) &
FIFO_SIZE_MASK;
- devpriv->rx_fifo_size = readl(devpriv->mmio + RX_FIFO_SIZE_REG) &
+ devpriv->rx_fifo_size = readl(dev->mmio + RX_FIFO_SIZE_REG) &
FIFO_SIZE_MASK;
- writel(0, devpriv->mmio + INTERRUPT_CONTROL_REG);
+ writel(0, dev->mmio + INTERRUPT_CONTROL_REG);
/* enable interrupts */
plx_intcsr_bits =
pci_set_master(pcidev);
devpriv->plx9080_mmio = pci_ioremap_bar(pcidev, 0);
- devpriv->mmio = pci_ioremap_bar(pcidev, 2);
- if (!devpriv->plx9080_mmio || !devpriv->mmio) {
+ dev->mmio = pci_ioremap_bar(pcidev, 2);
+ if (!devpriv->plx9080_mmio || !dev->mmio) {
dev_warn(dev->class_dev, "failed to remap io memory\n");
return -ENOMEM;
}
writel(0, devpriv->plx9080_mmio + PLX_INTRCS_REG);
iounmap(devpriv->plx9080_mmio);
}
- if (devpriv->mmio)
- iounmap(devpriv->mmio);
+ if (dev->mmio)
+ iounmap(dev->mmio);
/* free pci dma buffers */
for (i = 0; i < NUM_DMA_BUFFERS; i++) {
if (devpriv->dio_buffer[i])