drm/rockchip: vop: add rk3366 vop lit support

Change-Id: Iaf869f0fbf7b703dff3c38e9df4b8570d9260bd4
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
index 12314a9fffe131c9898767d6f261e96b09a2a459..46f80e6a5025b9db66f62fad1e685f88efd90a95 100644 (file)
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
@@ -10,6 +10,7 @@ Required properties:
                "rockchip,rk3288-vop";
                "rockchip,rk3368-vop";
                "rockchip,rk3366-vop";
+               "rockchip,rk3366-vop-lit";
                "rockchip,rk3399-vop-big";
                "rockchip,rk3399-vop-lit";
                "rockchip,rk322x-vop";

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 15c9badbd9be94b703470b38180fe1820e6262cf..7608a02d72f0255456476713f613c947b5840219 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1699,6 +1699,9 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
                VOP_CTRL_SET(vop, rgb_en, 1);
                VOP_CTRL_SET(vop, rgb_pin_pol, val);
                VOP_CTRL_SET(vop, rgb_dclk_pol, 1);
+               VOP_CTRL_SET(vop, lvds_en, 1);
+               VOP_CTRL_SET(vop, lvds_pin_pol, val);
+               VOP_CTRL_SET(vop, lvds_dclk_pol, 1);
                break;
        case DRM_MODE_CONNECTOR_eDP:
                VOP_CTRL_SET(vop, edp_en, 1);

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 746a1ab4cd4fbb3cf2014b713af89138fa0f236a..0782d1b3fb297719450c190da8f7e6491e8e0278 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -106,6 +106,7 @@ struct vop_ctrl {
        struct vop_reg dclk_ddr;
        struct vop_reg p2i_en;
        struct vop_reg rgb_en;
+       struct vop_reg lvds_en;
        struct vop_reg edp_en;
        struct vop_reg hdmi_en;
        struct vop_reg mipi_en;
@@ -114,6 +115,8 @@ struct vop_ctrl {
        struct vop_reg pin_pol;
        struct vop_reg rgb_dclk_pol;
        struct vop_reg rgb_pin_pol;
+       struct vop_reg lvds_dclk_pol;
+       struct vop_reg lvds_pin_pol;
        struct vop_reg hdmi_dclk_pol;
        struct vop_reg hdmi_pin_pol;
        struct vop_reg edp_dclk_pol;

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index e2055ef8c86d0d553cce7ea603c142cea5a0308c..e252738d19aedfb6dd688323d15c703948c503d0 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -754,6 +754,131 @@ static const struct vop_data rk3036_vop = {
        .win_size = ARRAY_SIZE(rk3036_vop_win_data),
 };
 
+static const int rk3366_vop_lit_intrs[] = {
+       FS_INTR,
+       FS_NEW_INTR,
+       ADDR_SAME_INTR,
+       LINE_FLAG_INTR,
+       LINE_FLAG1_INTR,
+       BUS_ERROR_INTR,
+       WIN0_EMPTY_INTR,
+       WIN1_EMPTY_INTR,
+       DSP_HOLD_VALID_INTR,
+};
+
+static const struct vop_scl_regs rk3366_lit_win_scl = {
+       .scale_yrgb_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
+       .scale_yrgb_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
+       .scale_cbcr_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
+       .scale_cbcr_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
+};
+
+static const struct vop_win_phy rk3366_lit_win0_data = {
+       .scl = &rk3366_lit_win_scl,
+       .data_formats = formats_win_full,
+       .nformats = ARRAY_SIZE(formats_win_full),
+
+       .enable = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 0),
+       .format = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x7, 1),
+       .rb_swap = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 12),
+       .act_info = VOP_REG(RK3366_LIT_WIN0_ACT_INFO, 0xffffffff, 0),
+       .dsp_info = VOP_REG(RK3366_LIT_WIN0_DSP_INFO, 0xffffffff, 0),
+       .dsp_st = VOP_REG(RK3366_LIT_WIN0_DSP_ST, 0xffffffff, 0),
+       .yrgb_mst = VOP_REG(RK3366_LIT_WIN0_YRGB_MST0, 0xffffffff, 0),
+       .uv_mst = VOP_REG(RK3366_LIT_WIN0_CBR_MST0, 0xffffffff, 0),
+       .yrgb_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 0),
+       .uv_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 16),
+
+       .alpha_mode = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 1),
+       .alpha_en = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 0),
+       .key_color = VOP_REG(RK3366_LIT_WIN0_COLOR_KEY, 0xffffff, 0),
+       .key_en = VOP_REG(RK3366_LIT_WIN0_COLOR_KEY, 0x1, 24),
+};
+
+static const struct vop_win_phy rk3366_lit_win1_data = {
+       .data_formats = formats_win_lite,
+       .nformats = ARRAY_SIZE(formats_win_lite),
+
+       .enable = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 0),
+       .format = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x7, 4),
+       .rb_swap = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 12),
+       .dsp_info = VOP_REG(RK3366_LIT_WIN1_DSP_INFO, 0xffffffff, 0),
+       .dsp_st = VOP_REG(RK3366_LIT_WIN1_DSP_ST, 0xffffffff, 0),
+       .yrgb_mst = VOP_REG(RK3366_LIT_WIN1_MST, 0xffffffff, 0),
+       .yrgb_vir = VOP_REG(RK3366_LIT_WIN1_VIR, 0x1fff, 0),
+
+       .alpha_mode = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 1),
+       .alpha_en = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 0),
+       .key_color = VOP_REG(RK3366_LIT_WIN1_COLOR_KEY, 0xffffff, 0),
+       .key_en = VOP_REG(RK3366_LIT_WIN1_COLOR_KEY, 0x1, 24),
+};
+
+static const struct vop_win_data rk3366_vop_lit_win_data[] = {
+       { .base = 0x00, .phy = &rk3366_lit_win0_data,
+         .type = DRM_PLANE_TYPE_PRIMARY },
+       { .base = 0x00, .phy = &rk3366_lit_win1_data,
+         .type = DRM_PLANE_TYPE_CURSOR },
+};
+
+static const struct vop_intr rk3366_lit_intr = {
+       .intrs = rk3366_vop_lit_intrs,
+       .nintrs = ARRAY_SIZE(rk3366_vop_lit_intrs),
+       .line_flag_num[0] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 0),
+       .line_flag_num[1] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 16),
+       .status = VOP_REG_MASK(RK3366_LIT_INTR_STATUS, 0xffff, 0),
+       .enable = VOP_REG_MASK(RK3366_LIT_INTR_EN, 0xffff, 0),
+       .clear = VOP_REG_MASK(RK3366_LIT_INTR_CLEAR, 0xffff, 0),
+};
+
+static const struct vop_ctrl rk3366_lit_ctrl_data = {
+       .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1),
+       .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
+       .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0),
+       .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
+       .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0),
+       .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0),
+       .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0),
+       .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0),
+       .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13),
+       .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0),
+       .dsp_layer_sel = VOP_REG(RK3366_LIT_SYS_CTRL0, 0x1, 1),
+       .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4),
+       .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13),
+       .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14),
+       .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0),
+       .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2),
+       .hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8),
+       .hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10),
+       .lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16),
+       .lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18),
+       .mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24),
+       .mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26),
+       .mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25),
+       .lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17),
+       .hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9),
+       .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
+       .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
+       .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6),
+       .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
+       .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
+       .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
+       .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
+       .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3),
+       .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5),
+       .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16),
+       .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0),
+       .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0),
+};
+
+static const struct vop_data rk3366_vop_lit = {
+       .max_input = {1920, 8192},
+       .max_output = {1920, 1080},
+       .ctrl = &rk3366_lit_ctrl_data,
+       .intr = &rk3366_lit_intr,
+       .win = rk3366_vop_lit_win_data,
+       .win_size = ARRAY_SIZE(rk3366_vop_lit_win_data),
+};
+
 static const struct of_device_id vop_driver_dt_match[] = {
        { .compatible = "rockchip,rk3036-vop",
          .data = &rk3036_vop },
@@ -763,6 +888,8 @@ static const struct of_device_id vop_driver_dt_match[] = {
          .data = &rk3368_vop },
        { .compatible = "rockchip,rk3366-vop",
          .data = &rk3366_vop },
+       { .compatible = "rockchip,rk3366-vop-lit",
+         .data = &rk3366_vop_lit },
        { .compatible = "rockchip,rk3399-vop-big",
          .data = &rk3399_vop_big },
        { .compatible = "rockchip,rk3399-vop-lit",

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
index 20f3b603dbed706bf395ddc4234c58ce5f213573..285ff6e5733b3a682384e6d0fd0699b4ec7d0360 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
@@ -879,4 +879,69 @@
 #define RK3036_HWC_LUT_ADDR            0x800
 /* rk3036 register definition end */
 
+/* rk3366 register definition */
+#define RK3366_LIT_REG_CFG_DONE                        0x00000
+#define RK3366_LIT_VERSION                     0x00004
+#define RK3366_LIT_DSP_BG                      0x00008
+#define RK3366_LIT_MCU_RESERVED                        0x0000c
+#define RK3366_LIT_SYS_CTRL0                   0x00010
+#define RK3366_LIT_SYS_CTRL1                   0x00014
+#define RK3366_LIT_SYS_CTRL2                   0x00018
+#define RK3366_LIT_DSP_CTRL0                   0x00020
+#define RK3366_LIT_DSP_CTRL2                   0x00028
+#define RK3366_LIT_VOP_STATUS                  0x0002c
+#define RK3366_LIT_LINE_FLAG                   0x00030
+#define RK3366_LIT_INTR_EN                     0x00034
+#define RK3366_LIT_INTR_CLEAR                  0x00038
+#define RK3366_LIT_INTR_STATUS                 0x0003c
+#define RK3366_LIT_WIN0_CTRL0                  0x00050
+#define RK3366_LIT_WIN0_CTRL1                  0x00054
+#define RK3366_LIT_WIN0_COLOR_KEY              0x00058
+#define RK3366_LIT_WIN0_VIR                    0x0005c
+#define RK3366_LIT_WIN0_YRGB_MST0              0x00060
+#define RK3366_LIT_WIN0_CBR_MST0               0x00064
+#define RK3366_LIT_WIN0_ACT_INFO               0x00068
+#define RK3366_LIT_WIN0_DSP_INFO               0x0006c
+#define RK3366_LIT_WIN0_DSP_ST                 0x00070
+#define RK3366_LIT_WIN0_SCL_FACTOR_YRGB                0x00074
+#define RK3366_LIT_WIN0_SCL_FACTOR_CBR         0x00078
+#define RK3366_LIT_WIN0_SCL_OFFSET             0x0007c
+#define RK3366_LIT_WIN0_ALPHA_CTRL             0x00080
+#define RK3366_LIT_WIN1_CTRL0                  0x00090
+#define RK3366_LIT_WIN1_CTRL1                  0x00094
+#define RK3366_LIT_WIN1_VIR                    0x00098
+#define RK3366_LIT_WIN1_MST                    0x000a0
+#define RK3366_LIT_WIN1_DSP_INFO               0x000a4
+#define RK3366_LIT_WIN1_DSP_ST                 0x000a8
+#define RK3366_LIT_WIN1_COLOR_KEY              0x000ac
+#define RK3366_LIT_WIN1_ALPHA_CTRL             0x000bc
+#define RK3366_LIT_HWC_CTRL0                   0x000e0
+#define RK3366_LIT_HWC_CTRL1                   0x000e4
+#define RK3366_LIT_HWC_MST                     0x000e8
+#define RK3366_LIT_HWC_DSP_ST                  0x000ec
+#define RK3366_LIT_HWC_ALPHA_CTRL              0x000f0
+#define RK3366_LIT_DSP_HTOTAL_HS_END           0x00100
+#define RK3366_LIT_DSP_HACT_ST_END             0x00104
+#define RK3366_LIT_DSP_VTOTAL_VS_END           0x00108
+#define RK3366_LIT_DSP_VACT_ST_END             0x0010c
+#define RK3366_LIT_DSP_VS_ST_END_F1            0x00110
+#define RK3366_LIT_DSP_VACT_ST_END_F1          0x00114
+#define RK3366_LIT_BCSH_CTRL                   0x00160
+#define RK3366_LIT_BCSH_COL_BAR                        0x00164
+#define RK3366_LIT_BCSH_BCS                    0x00168
+#define RK3366_LIT_BCSH_H                      0x0016c
+#define RK3366_LIT_FRC_LOWER01_0               0x00170
+#define RK3366_LIT_FRC_LOWER01_1               0x00174
+#define RK3366_LIT_FRC_LOWER10_0               0x00178
+#define RK3366_LIT_FRC_LOWER10_1               0x0017c
+#define RK3366_LIT_FRC_LOWER11_0               0x00180
+#define RK3366_LIT_FRC_LOWER11_1               0x00184
+#define RK3366_LIT_DBG_REG_000                 0x00190
+#define RK3366_LIT_BLANKING_VALUE              0x001f4
+#define RK3366_LIT_FLAG_REG_FRM_VALID          0x001f8
+#define RK3366_LIT_FLAG_REG                    0x001fc
+#define RK3366_LIT_HWC_LUT_ADDR                        0x00600
+#define RK3366_LIT_GAMMA_LUT_ADDR              0x00a00
+/* rk3366 register definition end */
+
 #endif /* _ROCKCHIP_VOP_REG_H */