Enable PostRA scheduling for SPU.

This speeds up selected test cases with up to
5% - no slowdowns observed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120286 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/CellSPU/SPUSubtarget.cpp b/lib/Target/CellSPU/SPUSubtarget.cpp
index 0f18b7fa8b26a3eec0ecefeb448a4ce02a3e1afc..07c8352fba9f7581ac1d41a1fb4d2379bb2a00b7 100644 (file)
--- a/lib/Target/CellSPU/SPUSubtarget.cpp
+++ b/lib/Target/CellSPU/SPUSubtarget.cpp
@@ -14,6 +14,8 @@
 #include "SPUSubtarget.h"
 #include "SPU.h"
 #include "SPUGenSubtarget.inc"
+#include "llvm/ADT/SmallVector.h"
+#include "SPURegisterInfo.h"
 
 using namespace llvm;
 
@@ -34,3 +36,22 @@ SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &FS) :
 /// producing code for the JIT.
 void SPUSubtarget::SetJITMode() {
 }
+
+/// Enable PostRA scheduling for optimization levels -O2 and -O3.
+bool SPUSubtarget::enablePostRAScheduler(
+                       CodeGenOpt::Level OptLevel,
+                       TargetSubtarget::AntiDepBreakMode& Mode,
+                       RegClassVector& CriticalPathRCs) const {
+  Mode = TargetSubtarget::ANTIDEP_CRITICAL;
+  // CriticalPathsRCs seems to be the set of
+  // RegisterClasses that antidep breakings are performed for.
+  // Do it for all register classes 
+  CriticalPathRCs.clear();
+  CriticalPathRCs.push_back(&SPU::R8CRegClass);
+  CriticalPathRCs.push_back(&SPU::R16CRegClass);
+  CriticalPathRCs.push_back(&SPU::R32CRegClass);
+  CriticalPathRCs.push_back(&SPU::R32FPRegClass);
+  CriticalPathRCs.push_back(&SPU::R64CRegClass);
+  CriticalPathRCs.push_back(&SPU::VECREGRegClass);
+  return OptLevel >= CodeGenOpt::Default;
+}

diff --git a/lib/Target/CellSPU/SPUSubtarget.h b/lib/Target/CellSPU/SPUSubtarget.h
index 147163d52ef73b2b9362d046f0921a81aa2a4e38..d7929302f0806b5bc60c1ed2a2f366af749ab69e 100644 (file)
--- a/lib/Target/CellSPU/SPUSubtarget.h
+++ b/lib/Target/CellSPU/SPUSubtarget.h
@@ -84,6 +84,10 @@ namespace llvm {
              "-i16:16:128-i8:8:128-i1:8:128-a:0:128-v64:64:128-v128:128:128"
              "-s:128:128-n32:64";
     }
+
+    bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
+                               TargetSubtarget::AntiDepBreakMode& Mode,
+                               RegClassVector& CriticalPathRCs) const;
   };
 } // End llvm namespace
 

diff --git a/test/CodeGen/CellSPU/sext128.ll b/test/CodeGen/CellSPU/sext128.ll
index 8a5b609d79ac7c632216bce84d0c3afcae41eb12..027c1c58afbc0627e42f148dc223990829b1edf1 100644 (file)
--- a/test/CodeGen/CellSPU/sext128.ll
+++ b/test/CodeGen/CellSPU/sext128.ll
@@ -13,8 +13,8 @@ entry:
 ; CHECK:       long    66051
 ; CHECK:       long    67438087
 ; CHECK-NOT: rotqmbyi
-; CHECK:       rotmai
 ; CHECK:       lqa
+; CHECK:       rotmai
 ; CHECK:       shufb
 }
 
@@ -27,8 +27,8 @@ entry:
 ; CHECK:       long    269488144
 ; CHECK:       long    66051
 ; CHECK-NOT: rotqmbyi
-; CHECK:       rotmai
 ; CHECK:       lqa
+; CHECK:       rotmai
 ; CHECK:       shufb
 }
 
@@ -42,8 +42,8 @@ entry:
 ; CHECK:       long    269488144
 ; CHECK:       long    66051
 ; CHECK-NOT: rotqmbyi
-; CHECK:       rotmai
 ; CHECK:       lqa
+; CHECK:       rotmai
 ; CHECK:       shufb
 }
 

diff --git a/test/CodeGen/CellSPU/shuffles.ll b/test/CodeGen/CellSPU/shuffles.ll
index 94b5fbd6baa8fc3f36fd10dc9997133bd2ce9396..c88a258c26c7635fc00c11da468341c14e8356b9 100644 (file)
--- a/test/CodeGen/CellSPU/shuffles.ll
+++ b/test/CodeGen/CellSPU/shuffles.ll
@@ -1,4 +1,4 @@
-; RUN: llc --march=cellspu < %s | FileCheck %s
+; RUN: llc -O1  --march=cellspu < %s | FileCheck %s
 
 define <4 x float> @shuffle(<4 x float> %param1, <4 x float> %param2) {
   ; CHECK: cwd {{\$.}}, 0($sp)