git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128243
91177308-0d34-0410-b5e6-
96231b3b80d8
// VMOV (immediate)
// Qd/Dd imm
+// VBIC (immediate)
// VORR (immediate)
// Qd/Dd imm src(=Qd/Dd)
static bool DisassembleN1RegModImmFrm(MCInst &MI, unsigned Opcode,
case ARM::VMOVv8i16:
case ARM::VMVNv4i16:
case ARM::VMVNv8i16:
+ case ARM::VBICiv4i16:
+ case ARM::VBICiv8i16:
case ARM::VORRiv4i16:
case ARM::VORRiv8i16:
esize = ESize16;
case ARM::VMOVv4i32:
case ARM::VMVNv2i32:
case ARM::VMVNv4i32:
+ case ARM::VBICiv2i32:
+ case ARM::VBICiv4i32:
case ARM::VORRiv2i32:
case ARM::VORRiv4i32:
esize = ESize32;
esize = ESize64;
break;
default:
- assert(0 && "Unreachable code!");
+ assert(0 && "Unexpected opcode!");
return false;
}
NumOpsAdded = 2;
- // VORRiv*i* variants have an extra $src = $Vd to be filled in.
+ // VBIC/VORRiv*i* variants have an extra $src = $Vd to be filled in.
if (NumOps >= 3 &&
(OpInfo[2].RegClass == ARM::DPRRegClassID ||
OpInfo[2].RegClass == ARM::QPRRegClassID)) {
# CHECK: vorr.i32 q15, #0x4F0000
0x5f 0xe5 0xc4 0xf2
+
+# CHECK: vbic.i32 q2, #0xA900
+0x79 0x53 0x82 0xf3