add usb debug for rk2928

diff --git a/drivers/usb/dwc_otg/dwc_otg_cil.c b/drivers/usb/dwc_otg/dwc_otg_cil.c
index fefde8c8749f394186d2be83ccc4378b303ebb5c..1dea667cd47742dce87ac72172a53bbf49514d45 100755 (executable)
--- a/drivers/usb/dwc_otg/dwc_otg_cil.c
+++ b/drivers/usb/dwc_otg/dwc_otg_cil.c
@@ -732,7 +732,7 @@ void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if)
     dwc_write_reg32( &global_regs->dptxfsiz_dieptxf[3], 0x00800330 );  //ep7 tx fifo
     dwc_write_reg32( &global_regs->dptxfsiz_dieptxf[4], 0x001003b0 );  //ep9 tx fifo
 #endif
-#ifdef CONFIG_ARCH_RK2928  //@lyz the same with RK30
+#ifdef CONFIG_ARCH_RK2928  
     /* Configure data FIFO sizes, RK30 otg has 0x3cc dwords total */
     dwc_write_reg32( &global_regs->grxfsiz, 0x00000120 );
     dwc_write_reg32( &global_regs->gnptxfsiz, 0x00100120 );             //ep0 tx fifo 

diff --git a/drivers/usb/dwc_otg/dwc_otg_pcd.c b/drivers/usb/dwc_otg/dwc_otg_pcd.c
index 25dfd65c35e07f273bca82d65e0e0a31cfc6d55d..c73bc98f2747ced595d1b3c28ce8e67efeef1fbf 100755 (executable)
--- a/drivers/usb/dwc_otg/dwc_otg_pcd.c
+++ b/drivers/usb/dwc_otg/dwc_otg_pcd.c
@@ -1590,7 +1590,6 @@ int dwc_pcd_reset(dwc_otg_pcd_t *pcd)
 {
     dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
     dwc_otg_disable_global_interrupts( core_if );
-    //
 #ifdef CONFIG_ARCH_RK29
     cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_AHB_BUS, true);
     cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_PHY, true);
@@ -1762,34 +1761,44 @@ static void dwc_otg_pcd_check_vbus_timer( unsigned long data )
        dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)_dev->platform_data));
     dwc_otg_pcd_t * _pcd = otg_dev->pcd;
     unsigned long flags;
-
-       local_irq_save(flags);
+    local_irq_save(flags);
     _pcd->check_vbus_timer.expires = jiffies + (HZ); /* 1 s */
-    if(!pldata->get_status(USB_STATUS_ID)){  // id low
-        if( pldata->phy_status){ 
+    if(!pldata->get_status(USB_STATUS_ID))
+    {  // id low
+        if( pldata->dwc_otg_uart_mode != NULL )
+        {//exit phy bypass to uart & enable usb phy
+            pldata->dwc_otg_uart_mode( pldata, PHY_USB_MODE);
+        }
+        if( pldata->phy_status)
+        { 
             pldata->clock_enable( pldata, 1);          
             pldata->phy_suspend(pldata, USB_PHY_ENABLED);
         } 
     }
-       else if(pldata->get_status(USB_STATUS_BVABLID)){  // bvalid
+       else if(pldata->get_status(USB_STATUS_BVABLID))
+       {  // bvalid
         /* if usb not connect before ,then start connect */
-         if( _pcd->vbus_status == 0 ) {
+         if( _pcd->vbus_status == 0 ) 
+         {
             DWC_PRINT("********vbus detect*********************************************\n");
            _pcd->vbus_status = 1;
             if(_pcd->conn_en)
                 goto connect;
-            else if( pldata->phy_status == USB_PHY_ENABLED ){
+            else if( pldata->phy_status == USB_PHY_ENABLED )
+            {
                 // not connect, suspend phy
                 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
                 udelay(3);
                 pldata->clock_enable( pldata, 0);
             }
         } 
-        else if((_pcd->conn_en)&&(_pcd->conn_status>=0)&&(_pcd->conn_status <3)){
+        else if((_pcd->conn_en)&&(_pcd->conn_status>=0)&&(_pcd->conn_status <3))
+        {
             DWC_PRINT("********soft reconnect******************************************\n");
            goto connect;
         }
-        else if(_pcd->conn_status ==3){
+        else if(_pcd->conn_status ==3)
+        {
                        //*Á¬½Ó²»ÉÏʱÊÍ·ÅËø£¬ÔÊÐíϵͳ½øÈë¶þ¼¶Ë¯Ãߣ¬yk@rk,20100331*//
             dwc_otg_msc_unlock(_pcd);
             _pcd->conn_status++;
@@ -1797,24 +1806,32 @@ static void dwc_otg_pcd_check_vbus_timer( unsigned long data )
                 _pcd->vbus_status = 2;
                 
             // not connect, suspend phy
-            if( pldata->phy_status == USB_PHY_ENABLED ){
+            if( pldata->phy_status == USB_PHY_ENABLED )
+            {
                 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
                 udelay(3);
                 pldata->clock_enable( pldata, 0);
             }
         }
-       }else {
+       }
+    else 
+    {
         _pcd->vbus_status = 0;
-        if(_pcd->conn_status){
+        if(_pcd->conn_status)
+        {
              _pcd->conn_status = 0;
              dwc_otg_msc_unlock(_pcd);
         }
-        else if( pldata->phy_status == USB_PHY_ENABLED ){ 
+        else if( pldata->phy_status == USB_PHY_ENABLED )
+        { 
             /* no vbus detect here , close usb phy  */
             pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
             udelay(3);
-            pldata->clock_enable( pldata, 0);          
-        }
+            pldata->clock_enable( pldata, 0);
+            /* usb phy bypass to uart mode  */
+            if( pldata->dwc_otg_uart_mode != NULL )
+                pldata->dwc_otg_uart_mode( pldata, PHY_UART_MODE);    
+        }  
     }
     add_timer(&_pcd->check_vbus_timer); 
        local_irq_restore(flags);
@@ -1823,7 +1840,8 @@ static void dwc_otg_pcd_check_vbus_timer( unsigned long data )
 connect:
     if(_pcd->conn_status==0)
         dwc_otg_msc_lock(_pcd);
-    if( pldata->phy_status){
+    if( pldata->phy_status)
+    {
         pldata->clock_enable( pldata, 1);      
         pldata->phy_suspend(pldata, USB_PHY_ENABLED);
     }
@@ -1873,7 +1891,8 @@ int dwc_otg_pcd_init(struct device *dev)
        static char pcd_name[] = "dwc_otg_pcd";
        dwc_otg_pcd_t *pcd;
        dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)dev->platform_data));
-    dwc_otg_core_if_t *core_if = otg_dev->core_if;
+    dwc_otg_core_if_t *core_if = otg_dev->core_if; 
+       struct dwc_otg_platform_data *pldata = dev->platform_data;
        int retval = 0;
        int irq;
         /*
@@ -1970,9 +1989,26 @@ int dwc_otg_pcd_init(struct device *dev)
     
     INIT_DELAYED_WORK(&pcd->reconnect , dwc_phy_reconnect);
     pcd->vbus_status  = 0;
-    pcd->phy_suspend  = 0;
-    if(dwc_otg_is_device_mode(core_if))
-        mod_timer(&pcd->check_vbus_timer, jiffies+(HZ<<4)); // delay 16 S  
+    pcd->phy_suspend  = 0; 
+    if(dwc_otg_is_device_mode(core_if)){
+#ifdef CONFIG_RK_USB_UART        
+        if(pldata->get_status(USB_STATUS_BVABLID))
+        {
+             pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
+        }//phy usb mode
+        else
+        {
+            pldata->phy_suspend(pldata,USB_PHY_SUSPEND);
+            pldata->dwc_otg_uart_mode(pldata, PHY_UART_MODE);
+        }//phy bypass to uart mode
+#endif
+        mod_timer(&pcd->check_vbus_timer, jiffies+(HZ<<4)); // delay 16 S 
+    }
+#ifdef CONFIG_RK_USB_UART
+    else if(pldata->dwc_otg_uart_mode != NULL)
+        pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);//disable phy bypass uart  
+#endif
+
        return 0;
 }
 /**

diff --git a/drivers/usb/dwc_otg/usbdev_rk.h b/drivers/usb/dwc_otg/usbdev_rk.h
index fb5a774258aa984c5343f59a18aa21421da9dce0..686ff71e035d8cdc403e8e726f7d7082c402ab6b 100755 (executable)
--- a/drivers/usb/dwc_otg/usbdev_rk.h
+++ b/drivers/usb/dwc_otg/usbdev_rk.h
@@ -2,9 +2,13 @@
 #define USB_PHY_ENABLED 0\r
 #define USB_PHY_SUSPEND 1\r
 \r
-#define USB_STATUS_BVABLID 1\r
-#define USB_STATUS_DPDM                 2\r
-#define USB_STATUS_ID                   3\r
+#define PHY_USB_MODE    0\r
+#define PHY_UART_MODE   1\r
+\r
+#define USB_STATUS_BVABLID    1\r
+#define USB_STATUS_DPDM                  2\r
+#define USB_STATUS_ID         3\r
+#define USB_STATUS_UARTMODE   4\r
 \r
 struct dwc_otg_platform_data {\r
     void *privdata;\r
@@ -18,5 +22,6 @@ struct dwc_otg_platform_data {
     void (*clock_init)(void* pdata);\r
     void (*clock_enable)(void* pdata, int enable);\r
     void (*power_enable)(int enable);\r
+    void (*dwc_otg_uart_mode)(void* pdata, int enter_usb_uart_mode);\r
     int (*get_status)(int id);\r
-};
\ No newline at end of file
+};\r

diff --git a/drivers/usb/dwc_otg/usbdev_rk2928.c b/drivers/usb/dwc_otg/usbdev_rk2928.c
index e3d74450a216808c8af5c07da8195990155a1080..02f7f1e86ae1f629685f5540f86b88d4b76ab838 100755 (executable)
--- a/drivers/usb/dwc_otg/usbdev_rk2928.c
+++ b/drivers/usb/dwc_otg/usbdev_rk2928.c
@@ -17,9 +17,9 @@
 #define USBOTG_SIZE    RK2928_USBOTG20_SIZE\r
 #define USBGRF_SOC_STATUS0     (GRF_REG_BASE+0x14c)\r
 #define USBGRF_UOC0_CON5       (GRF_REG_BASE+0x17c)\r
+#define USBGRF_UOC1_CON4    (GRF_REG_BASE+0X190)\r
 #define USBGRF_UOC1_CON5       (GRF_REG_BASE+0x194)\r
 \r
-\r
 int dwc_otg_check_dpdm(void)\r
 {\r
        static uint8_t * reg_base = 0;\r
@@ -27,23 +27,22 @@ int dwc_otg_check_dpdm(void)
     volatile unsigned int * otg_gotgctl;\r
     volatile unsigned int * otg_hprt0;\r
     int bus_status = 0;\r
-    unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC0_CON5);//@lyz modify UOC0_CON2 to CON5\r
+    unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC0_CON5) ;\r
     \r
-    // softreset & clockgate //@lyz modify RK2928_CRU_BASE\r
     *(unsigned int*)(RK2928_CRU_BASE+0x120) = ((7<<5)<<16)|(7<<5);    // otg0 phy clkgate\r
     udelay(3);\r
     *(unsigned int*)(RK2928_CRU_BASE+0x120) = ((7<<5)<<16)|(0<<5);    // otg0 phy clkgate\r
     dsb();\r
     *(unsigned int*)(RK2928_CRU_BASE+0xd4) = ((1<<5)<<16);    // otg0 phy clkgate\r
     *(unsigned int*)(RK2928_CRU_BASE+0xe4) = ((1<<13)<<16);   // otg0 hclk clkgate\r
-    *(unsigned int*)(RK2928_CRU_BASE+0xf4) = ((3<<10)<<16);    // hclk usb clkgate//@lyz to be check\r
-    \r
+    *(unsigned int*)(RK2928_CRU_BASE+0xf4) = ((3<<10)<<16);    // hclk usb clkgat\r
+   \r
     // exit phy suspend \r
-        *otg_phy_con1 = ((0x01<<0)<<16);    // exit suspend.@lyz\r
+        *otg_phy_con1 = ((0x01<<0)<<16);  \r
     \r
     // soft connect\r
     if(reg_base == 0){\r
-        reg_base = ioremap(RK2928_USBOTG20_PHYS,USBOTG_SIZE);//@lyz\r
+        reg_base = ioremap(RK2928_USBOTG20_PHYS,USBOTG_SIZE);\r
         if(!reg_base){\r
             bus_status = -1;\r
             goto out;\r
@@ -103,7 +102,7 @@ void usb20otg_phy_suspend(void* pdata, int suspend)
     struct dwc_otg_platform_data *usbpdata=pdata;\r
     unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC0_CON5);\r
     if(suspend){\r
-        *otg_phy_con1 = 0x1D5 |(0x1ff<<16);   // enter suspend.\r
+        *otg_phy_con1 = 0x55 |(0x7f<<16);   // enter suspend.\r
         usbpdata->phy_status = 1;\r
     }\r
     else{\r
@@ -152,6 +151,7 @@ int usb20otg_get_status(int id)
 {\r
     int ret = -1;\r
     unsigned int usbgrf_status = *(unsigned int*)(USBGRF_SOC_STATUS0);\r
+    unsigned int uoc1_con4 = *(unsigned int*)(USBGRF_UOC1_CON4);\r
     switch(id)\r
     {\r
         case USB_STATUS_BVABLID:\r
@@ -166,11 +166,34 @@ int usb20otg_get_status(int id)
             // id in grf\r
             ret = (usbgrf_status &(1<<10));\r
             break;\r
+        case USB_STATUS_UARTMODE:\r
+            // usb_uart_mode in grf\r
+            ret = (uoc1_con4 &(1<<13));\r
         default:\r
             break;\r
     }\r
     return ret;\r
 }\r
+void dwc_otg_uart_mode(void* pdata, int enter_usb_uart_mode)\r
+{\r
+#ifdef CONFIG_RK_USB_UART\r
+    //struct dwc_otg_platform_data *usbpdata=pdata;//1:uart 0:usb\r
+    unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC1_CON4);\r
+    //printk("usb_uart_mode = %d,enter_usb_uart_mode = %d\n",otg_phy_con1,enter_usb_uart_mode);\r
+    if(1 == enter_usb_uart_mode)   //uart mode\r
+    {\r
+        *otg_phy_con1 = (0x03 << 12 | (0x03<<(16+12)));//bypass dm\r
+        //printk("phy enter uart mode USBGRF_UOC1_CON4 = %08x\n",*otg_phy_con1);\r
+        \r
+    }\r
+    if(0 == enter_usb_uart_mode)   //usb mode\r
+    {   \r
+        *otg_phy_con1 = (0x03<<(12+16)); //bypass dm disable \r
+        //printk("phy enter usb mode USBGRF_UOC1_CON4 = %8x\n",*otg_phy_con1);\r
+    }\r
+#endif\r
+}\r
+\r
 void usb20otg_power_enable(int enable)\r
 {\r
 }\r
@@ -185,6 +208,7 @@ struct dwc_otg_platform_data usb20otg_pdata = {
     .clock_init=usb20otg_clock_init,\r
     .clock_enable=usb20otg_clock_enable,\r
     .get_status=usb20otg_get_status,\r
+    .dwc_otg_uart_mode=dwc_otg_uart_mode,\r
 };\r
 \r
 struct platform_device device_usb20_otg = {\r