net: phy: dp83867: Disable FORCE_LINK_GOOD in PHYCTRL

With FORCE_LINK_GOOD we are not able to get a link.
According to the TRM this bit should be 0 (Normal operation) in default.

Set FORCE_LINK_GOOD to default.

Change-Id: Iaa30bef20fc6f8313c018d18646879f62db49004
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 47d06622dda87c7209c4c96c91ffa324b03a70e8..c98ebdff07ec952a8b200b49f4364012c536d40c 100644 (file)
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -41,6 +41,9 @@
 #define DP83867_SW_RESET       BIT(15)
 #define DP83867_SW_RESTART     BIT(14)
 
+/* PHYCTRL bits */
+#define MII_DP83867_PHYCTRL_FORCE_LINK_GOOD    BIT(10)
+
 /* MICR Interrupt bits */
 #define MII_DP83867_MICR_AN_ERR_INT_EN         BIT(15)
 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN     BIT(14)
@@ -303,6 +306,13 @@ static int dp83867_config_init(struct phy_device *phydev)
        phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
                               DP83867_DEVADDR, val);
 
+       /* Disable FORCE_LINK_GOOD */
+       val = phy_read(phydev, MII_DP83867_PHYCTRL);
+       if (val & MII_DP83867_PHYCTRL_FORCE_LINK_GOOD) {
+               val &= ~(MII_DP83867_PHYCTRL_FORCE_LINK_GOOD);
+               phy_write(phydev, MII_DP83867_PHYCTRL, val);
+       }
+
        return 0;
 }