Combine the F2 and F3 instruction classes into one file for simplicity

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16484 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Sparc/SparcInstrFormats.td b/lib/Target/Sparc/SparcInstrFormats.td
new file mode 100644 (file)
index 0000000..cef4ecb
--- /dev/null
+++ b/lib/Target/Sparc/SparcInstrFormats.td
@@ -0,0 +1,97 @@
+//===- SparcV8InstrFormats.td - SparcV8 Instr Formats ------*- tablegen -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Format #2 instruction classes in the SparcV8
+//===----------------------------------------------------------------------===//
+
+class F2 : InstV8 {                   // Format 2 instructions
+  bits<3>  op2;
+  bits<22> imm22;
+  let op          = 0;    // op = 0
+  let Inst{24-22} = op2;
+  let Inst{21-0}  = imm22;
+}
+
+// Specific F2 classes: SparcV8 manual, page 44
+//
+class F2_1<bits<3> op2Val, string name> : F2 {
+  bits<5>  rd;
+  bits<22> imm;
+
+  let op2         = op2Val;
+  let Name        = name;
+
+  let Inst{29-25} = rd;
+}
+
+class F2_2<bits<4> condVal, bits<3> op2Val, string name> : F2 {
+  bits<4>   cond;
+  bit       annul = 0;     // currently unused
+
+  let cond        = condVal;
+  let op2         = op2Val;
+  let Name        = name;
+
+  let Inst{29}    = annul;
+  let Inst{28-25} = cond;
+}
+
+//===----------------------------------------------------------------------===//
+// Format #3 instruction classes in the SparcV8
+//===----------------------------------------------------------------------===//
+
+class F3 : InstV8 {
+  bits<5> rd;
+  bits<6> op3;
+  bits<5> rs1;
+  let op{1} = 1;   // Op = 2 or 3
+  let Inst{29-25} = rd;
+  let Inst{24-19} = op3;
+  let Inst{18-14} = rs1;
+}
+
+// Specific F3 classes: SparcV8 manual, page 44
+//
+class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3 {
+  bits<8> asi;
+  bits<5> rs2;
+
+  let op         = opVal;
+  let op3        = op3val;
+  let Name       = name;
+
+  let Inst{13}   = 0;     // i field = 0
+  let Inst{12-5} = asi;   // address space identifier
+  let Inst{4-0}  = rs2;
+}
+
+class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3 {
+  bits<13> simm13;
+
+  let op         = opVal;
+  let op3        = op3val;
+  let Name       = name;
+
+  let Inst{13}   = 1;     // i field = 1
+  let Inst{12-0} = simm13;
+}
+
+// floating-point
+class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, string name> : F3 {
+  bits<8> asi;
+  bits<5> rs2;
+
+  let op         = opVal;
+  let op3        = op3val;
+  let Name       = name;
+
+  let Inst{13-5} = opfval;   // fp opcode
+  let Inst{4-0}  = rs2;
+}

diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index 07491eb1c10e8d5344c4a555c96655d74f1aabe2..110ac8b0f82922cbfbeb77b6460fda8b2e6c8f43 100644 (file)
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -28,8 +28,7 @@ class InstV8 : Instruction {          // SparcV8 instruction baseline
   bit isPrivileged = 0; // Is this a privileged instruction?
 }
 
-include "SparcV8InstrInfo_F2.td"
-include "SparcV8InstrInfo_F3.td"
+include "SparcV8InstrFormats.td"
 
 //===----------------------------------------------------------------------===//
 // Instructions

diff --git a/lib/Target/Sparc/SparcV8InstrInfo_F2.td b/lib/Target/Sparc/SparcV8InstrInfo_F2.td
deleted file mode 100644 (file)
index 7b550bd..0000000
--- a/lib/Target/Sparc/SparcV8InstrInfo_F2.td
+++ /dev/null
@@ -1,44 +0,0 @@
-//===- SparcV8Instrs_F2.td - Format 2 instructions: SparcV8 Target --------===//
-// 
-//                     The LLVM Compiler Infrastructure
-//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
-//===----------------------------------------------------------------------===//
-//
-// Format #2 instruction classes in the SparcV8
-//
-//===----------------------------------------------------------------------===//
-
-class F2 : InstV8 {                   // Format 2 instructions
-  bits<3>  op2;
-  bits<22> imm22;
-  let op          = 0;    // op = 0
-  let Inst{24-22} = op2;
-  let Inst{21-0}  = imm22;
-}
-
-// Specific F2 classes: SparcV8 manual, page 44
-//
-class F2_1<bits<3> op2Val, string name> : F2 {
-  bits<5>  rd;
-  bits<22> imm;
-
-  let op2         = op2Val;
-  let Name        = name;
-
-  let Inst{29-25} = rd;
-}
-
-class F2_2<bits<4> condVal, bits<3> op2Val, string name> : F2 {
-  bits<4>   cond;
-  bit       annul = 0;     // currently unused
-
-  let cond        = condVal;
-  let op2         = op2Val;
-  let Name        = name;
-
-  let Inst{29}    = annul;
-  let Inst{28-25} = cond;
-}

diff --git a/lib/Target/Sparc/SparcV8InstrInfo_F3.td b/lib/Target/Sparc/SparcV8InstrInfo_F3.td
deleted file mode 100644 (file)
index 4906b9d..0000000
--- a/lib/Target/Sparc/SparcV8InstrInfo_F3.td
+++ /dev/null
@@ -1,61 +0,0 @@
-//===- SparcV8Instrs_F3.td - Format 3 Instructions: SparcV8 Target --------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
-//===----------------------------------------------------------------------===//
-//
-// Format #3 instruction classes in the SparcV8
-//
-//===----------------------------------------------------------------------===//
-
-class F3 : InstV8 {
-  bits<5> rd;
-  bits<6> op3;
-  bits<5> rs1;
-  let op{1} = 1;   // Op = 2 or 3
-  let Inst{29-25} = rd;
-  let Inst{24-19} = op3;
-  let Inst{18-14} = rs1;
-}
-
-// Specific F3 classes: SparcV8 manual, page 44
-//
-class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3 {
-  bits<8> asi;
-  bits<5> rs2;
-
-  let op         = opVal;
-  let op3        = op3val;
-  let Name       = name;
-
-  let Inst{13}   = 0;     // i field = 0
-  let Inst{12-5} = asi;   // address space identifier
-  let Inst{4-0}  = rs2;
-}
-
-class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3 {
-  bits<13> simm13;
-
-  let op         = opVal;
-  let op3        = op3val;
-  let Name       = name;
-
-  let Inst{13}   = 1;     // i field = 1
-  let Inst{12-0} = simm13;
-}
-
-// floating-point
-class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, string name> : F3 {
-  bits<8> asi;
-  bits<5> rs2;
-
-  let op         = opVal;
-  let op3        = op3val;
-  let Name       = name;
-
-  let Inst{13-5} = opfval;   // fp opcode
-  let Inst{4-0}  = rs2;
-}

diff --git a/lib/Target/SparcV8/SparcV8InstrFormats.td b/lib/Target/SparcV8/SparcV8InstrFormats.td
new file mode 100644 (file)
index 0000000..cef4ecb
--- /dev/null
+++ b/lib/Target/SparcV8/SparcV8InstrFormats.td
@@ -0,0 +1,97 @@
+//===- SparcV8InstrFormats.td - SparcV8 Instr Formats ------*- tablegen -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Format #2 instruction classes in the SparcV8
+//===----------------------------------------------------------------------===//
+
+class F2 : InstV8 {                   // Format 2 instructions
+  bits<3>  op2;
+  bits<22> imm22;
+  let op          = 0;    // op = 0
+  let Inst{24-22} = op2;
+  let Inst{21-0}  = imm22;
+}
+
+// Specific F2 classes: SparcV8 manual, page 44
+//
+class F2_1<bits<3> op2Val, string name> : F2 {
+  bits<5>  rd;
+  bits<22> imm;
+
+  let op2         = op2Val;
+  let Name        = name;
+
+  let Inst{29-25} = rd;
+}
+
+class F2_2<bits<4> condVal, bits<3> op2Val, string name> : F2 {
+  bits<4>   cond;
+  bit       annul = 0;     // currently unused
+
+  let cond        = condVal;
+  let op2         = op2Val;
+  let Name        = name;
+
+  let Inst{29}    = annul;
+  let Inst{28-25} = cond;
+}
+
+//===----------------------------------------------------------------------===//
+// Format #3 instruction classes in the SparcV8
+//===----------------------------------------------------------------------===//
+
+class F3 : InstV8 {
+  bits<5> rd;
+  bits<6> op3;
+  bits<5> rs1;
+  let op{1} = 1;   // Op = 2 or 3
+  let Inst{29-25} = rd;
+  let Inst{24-19} = op3;
+  let Inst{18-14} = rs1;
+}
+
+// Specific F3 classes: SparcV8 manual, page 44
+//
+class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3 {
+  bits<8> asi;
+  bits<5> rs2;
+
+  let op         = opVal;
+  let op3        = op3val;
+  let Name       = name;
+
+  let Inst{13}   = 0;     // i field = 0
+  let Inst{12-5} = asi;   // address space identifier
+  let Inst{4-0}  = rs2;
+}
+
+class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3 {
+  bits<13> simm13;
+
+  let op         = opVal;
+  let op3        = op3val;
+  let Name       = name;
+
+  let Inst{13}   = 1;     // i field = 1
+  let Inst{12-0} = simm13;
+}
+
+// floating-point
+class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, string name> : F3 {
+  bits<8> asi;
+  bits<5> rs2;
+
+  let op         = opVal;
+  let op3        = op3val;
+  let Name       = name;
+
+  let Inst{13-5} = opfval;   // fp opcode
+  let Inst{4-0}  = rs2;
+}

diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.td b/lib/Target/SparcV8/SparcV8InstrInfo.td
index 07491eb1c10e8d5344c4a555c96655d74f1aabe2..110ac8b0f82922cbfbeb77b6460fda8b2e6c8f43 100644 (file)
--- a/lib/Target/SparcV8/SparcV8InstrInfo.td
+++ b/lib/Target/SparcV8/SparcV8InstrInfo.td
@@ -28,8 +28,7 @@ class InstV8 : Instruction {          // SparcV8 instruction baseline
   bit isPrivileged = 0; // Is this a privileged instruction?
 }
 
-include "SparcV8InstrInfo_F2.td"
-include "SparcV8InstrInfo_F3.td"
+include "SparcV8InstrFormats.td"
 
 //===----------------------------------------------------------------------===//
 // Instructions

diff --git a/lib/Target/SparcV8/SparcV8InstrInfo_F2.td b/lib/Target/SparcV8/SparcV8InstrInfo_F2.td
deleted file mode 100644 (file)
index 7b550bd..0000000
--- a/lib/Target/SparcV8/SparcV8InstrInfo_F2.td
+++ /dev/null
@@ -1,44 +0,0 @@
-//===- SparcV8Instrs_F2.td - Format 2 instructions: SparcV8 Target --------===//
-// 
-//                     The LLVM Compiler Infrastructure
-//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
-//===----------------------------------------------------------------------===//
-//
-// Format #2 instruction classes in the SparcV8
-//
-//===----------------------------------------------------------------------===//
-
-class F2 : InstV8 {                   // Format 2 instructions
-  bits<3>  op2;
-  bits<22> imm22;
-  let op          = 0;    // op = 0
-  let Inst{24-22} = op2;
-  let Inst{21-0}  = imm22;
-}
-
-// Specific F2 classes: SparcV8 manual, page 44
-//
-class F2_1<bits<3> op2Val, string name> : F2 {
-  bits<5>  rd;
-  bits<22> imm;
-
-  let op2         = op2Val;
-  let Name        = name;
-
-  let Inst{29-25} = rd;
-}
-
-class F2_2<bits<4> condVal, bits<3> op2Val, string name> : F2 {
-  bits<4>   cond;
-  bit       annul = 0;     // currently unused
-
-  let cond        = condVal;
-  let op2         = op2Val;
-  let Name        = name;
-
-  let Inst{29}    = annul;
-  let Inst{28-25} = cond;
-}

diff --git a/lib/Target/SparcV8/SparcV8InstrInfo_F3.td b/lib/Target/SparcV8/SparcV8InstrInfo_F3.td
deleted file mode 100644 (file)
index 4906b9d..0000000
--- a/lib/Target/SparcV8/SparcV8InstrInfo_F3.td
+++ /dev/null
@@ -1,61 +0,0 @@
-//===- SparcV8Instrs_F3.td - Format 3 Instructions: SparcV8 Target --------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
-//===----------------------------------------------------------------------===//
-//
-// Format #3 instruction classes in the SparcV8
-//
-//===----------------------------------------------------------------------===//
-
-class F3 : InstV8 {
-  bits<5> rd;
-  bits<6> op3;
-  bits<5> rs1;
-  let op{1} = 1;   // Op = 2 or 3
-  let Inst{29-25} = rd;
-  let Inst{24-19} = op3;
-  let Inst{18-14} = rs1;
-}
-
-// Specific F3 classes: SparcV8 manual, page 44
-//
-class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3 {
-  bits<8> asi;
-  bits<5> rs2;
-
-  let op         = opVal;
-  let op3        = op3val;
-  let Name       = name;
-
-  let Inst{13}   = 0;     // i field = 0
-  let Inst{12-5} = asi;   // address space identifier
-  let Inst{4-0}  = rs2;
-}
-
-class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3 {
-  bits<13> simm13;
-
-  let op         = opVal;
-  let op3        = op3val;
-  let Name       = name;
-
-  let Inst{13}   = 1;     // i field = 1
-  let Inst{12-0} = simm13;
-}
-
-// floating-point
-class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, string name> : F3 {
-  bits<8> asi;
-  bits<5> rs2;
-
-  let op         = opVal;
-  let op3        = op3val;
-  let Name       = name;
-
-  let Inst{13-5} = opfval;   // fp opcode
-  let Inst{4-0}  = rs2;
-}