drm/radeon/kms: Add support for SI GPU reset
authorAlex Deucher <alexander.deucher@amd.com>
Tue, 20 Mar 2012 21:18:12 +0000 (17:18 -0400)
committerDave Airlie <airlied@redhat.com>
Wed, 21 Mar 2012 06:55:52 +0000 (06:55 +0000)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/radeon/si.c
drivers/gpu/drm/radeon/sid.h

index dd9e7d3d23be21b549814d968e58229ba41d04f3..58ad9008cf05ba6fbad03a86807f5ef30b5e86ba 100644 (file)
@@ -29,6 +29,8 @@
 #include "atom.h"
 
 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
+extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
+extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
 
 /* get temperature in millidegrees */
 int si_get_temp(struct radeon_device *rdev)
@@ -1508,3 +1510,101 @@ static void si_gpu_init(struct radeon_device *rdev)
 
        udelay(50);
 }
+
+bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
+{
+       u32 srbm_status;
+       u32 grbm_status, grbm_status2;
+       u32 grbm_status_se0, grbm_status_se1;
+       struct r100_gpu_lockup *lockup = &rdev->config.si.lockup;
+       int r;
+
+       srbm_status = RREG32(SRBM_STATUS);
+       grbm_status = RREG32(GRBM_STATUS);
+       grbm_status2 = RREG32(GRBM_STATUS2);
+       grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
+       grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
+       if (!(grbm_status & GUI_ACTIVE)) {
+               r100_gpu_lockup_update(lockup, ring);
+               return false;
+       }
+       /* force CP activities */
+       r = radeon_ring_lock(rdev, ring, 2);
+       if (!r) {
+               /* PACKET2 NOP */
+               radeon_ring_write(ring, 0x80000000);
+               radeon_ring_write(ring, 0x80000000);
+               radeon_ring_unlock_commit(rdev, ring);
+       }
+       /* XXX deal with CP0,1,2 */
+       ring->rptr = RREG32(ring->rptr_reg);
+       return r100_gpu_cp_is_lockup(rdev, lockup, ring);
+}
+
+static int si_gpu_soft_reset(struct radeon_device *rdev)
+{
+       struct evergreen_mc_save save;
+       u32 grbm_reset = 0;
+
+       if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
+               return 0;
+
+       dev_info(rdev->dev, "GPU softreset \n");
+       dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
+               RREG32(GRBM_STATUS));
+       dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
+               RREG32(GRBM_STATUS2));
+       dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
+               RREG32(GRBM_STATUS_SE0));
+       dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
+               RREG32(GRBM_STATUS_SE1));
+       dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
+               RREG32(SRBM_STATUS));
+       evergreen_mc_stop(rdev, &save);
+       if (radeon_mc_wait_for_idle(rdev)) {
+               dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
+       }
+       /* Disable CP parsing/prefetching */
+       WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
+
+       /* reset all the gfx blocks */
+       grbm_reset = (SOFT_RESET_CP |
+                     SOFT_RESET_CB |
+                     SOFT_RESET_DB |
+                     SOFT_RESET_GDS |
+                     SOFT_RESET_PA |
+                     SOFT_RESET_SC |
+                     SOFT_RESET_SPI |
+                     SOFT_RESET_SX |
+                     SOFT_RESET_TC |
+                     SOFT_RESET_TA |
+                     SOFT_RESET_VGT |
+                     SOFT_RESET_IA);
+
+       dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
+       WREG32(GRBM_SOFT_RESET, grbm_reset);
+       (void)RREG32(GRBM_SOFT_RESET);
+       udelay(50);
+       WREG32(GRBM_SOFT_RESET, 0);
+       (void)RREG32(GRBM_SOFT_RESET);
+       /* Wait a little for things to settle down */
+       udelay(50);
+       dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
+               RREG32(GRBM_STATUS));
+       dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
+               RREG32(GRBM_STATUS2));
+       dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
+               RREG32(GRBM_STATUS_SE0));
+       dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
+               RREG32(GRBM_STATUS_SE1));
+       dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
+               RREG32(SRBM_STATUS));
+       evergreen_mc_resume(rdev, &save);
+       return 0;
+}
+
+int si_asic_reset(struct radeon_device *rdev)
+{
+       return si_gpu_soft_reset(rdev);
+}
+
index cf06dcc9ba96139b2fcd7117508c8a92c6e34ec5..4c6ff1c8b5ed317293ff975bff33671ef495f04e 100644 (file)
@@ -52,6 +52,8 @@
 
 #define DMIF_ADDR_CONFIG                               0xBD4
 
+#define        SRBM_STATUS                                     0xE50
+
 #define        CC_SYS_RB_BACKEND_DISABLE                       0xe80
 #define        GC_USER_SYS_RB_BACKEND_DISABLE                  0xe84
 
 #define        GRBM_CNTL                                       0x8000
 #define                GRBM_READ_TIMEOUT(x)                            ((x) << 0)
 
+#define        GRBM_STATUS2                                    0x8008
+#define                RLC_RQ_PENDING                                  (1 << 0)
+#define                RLC_BUSY                                        (1 << 8)
+#define                TC_BUSY                                         (1 << 9)
+
+#define        GRBM_STATUS                                     0x8010
+#define                CMDFIFO_AVAIL_MASK                              0x0000000F
+#define                RING2_RQ_PENDING                                (1 << 4)
+#define                SRBM_RQ_PENDING                                 (1 << 5)
+#define                RING1_RQ_PENDING                                (1 << 6)
+#define                CF_RQ_PENDING                                   (1 << 7)
+#define                PF_RQ_PENDING                                   (1 << 8)
+#define                GDS_DMA_RQ_PENDING                              (1 << 9)
+#define                GRBM_EE_BUSY                                    (1 << 10)
+#define                DB_CLEAN                                        (1 << 12)
+#define                CB_CLEAN                                        (1 << 13)
+#define                TA_BUSY                                         (1 << 14)
+#define                GDS_BUSY                                        (1 << 15)
+#define                VGT_BUSY                                        (1 << 17)
+#define                IA_BUSY_NO_DMA                                  (1 << 18)
+#define                IA_BUSY                                         (1 << 19)
+#define                SX_BUSY                                         (1 << 20)
+#define                SPI_BUSY                                        (1 << 22)
+#define                BCI_BUSY                                        (1 << 23)
+#define                SC_BUSY                                         (1 << 24)
+#define                PA_BUSY                                         (1 << 25)
+#define                DB_BUSY                                         (1 << 26)
+#define                CP_COHERENCY_BUSY                               (1 << 28)
+#define                CP_BUSY                                         (1 << 29)
+#define                CB_BUSY                                         (1 << 30)
+#define                GUI_ACTIVE                                      (1 << 31)
+#define        GRBM_STATUS_SE0                                 0x8014
+#define        GRBM_STATUS_SE1                                 0x8018
+#define                SE_DB_CLEAN                                     (1 << 1)
+#define                SE_CB_CLEAN                                     (1 << 2)
+#define                SE_BCI_BUSY                                     (1 << 22)
+#define                SE_VGT_BUSY                                     (1 << 23)
+#define                SE_PA_BUSY                                      (1 << 24)
+#define                SE_TA_BUSY                                      (1 << 25)
+#define                SE_SX_BUSY                                      (1 << 26)
+#define                SE_SPI_BUSY                                     (1 << 27)
+#define                SE_SC_BUSY                                      (1 << 29)
+#define                SE_DB_BUSY                                      (1 << 30)
+#define                SE_CB_BUSY                                      (1 << 31)
+
+#define        GRBM_SOFT_RESET                                 0x8020
+#define                SOFT_RESET_CP                                   (1 << 0)
+#define                SOFT_RESET_CB                                   (1 << 1)
+#define                SOFT_RESET_RLC                                  (1 << 2)
+#define                SOFT_RESET_DB                                   (1 << 3)
+#define                SOFT_RESET_GDS                                  (1 << 4)
+#define                SOFT_RESET_PA                                   (1 << 5)
+#define                SOFT_RESET_SC                                   (1 << 6)
+#define                SOFT_RESET_BCI                                  (1 << 7)
+#define                SOFT_RESET_SPI                                  (1 << 8)
+#define                SOFT_RESET_SX                                   (1 << 10)
+#define                SOFT_RESET_TC                                   (1 << 11)
+#define                SOFT_RESET_TA                                   (1 << 12)
+#define                SOFT_RESET_VGT                                  (1 << 14)
+#define                SOFT_RESET_IA                                   (1 << 15)
+
+#define CP_ME_CNTL                                     0x86D8
+#define                CP_CE_HALT                                      (1 << 24)
+#define                CP_PFP_HALT                                     (1 << 26)
+#define                CP_ME_HALT                                      (1 << 28)
+
+#define        CP_RB0_RPTR                                     0x8700
+
 #define        CP_QUEUE_THRESHOLDS                             0x8760
 #define                ROQ_IB1_START(x)                                ((x) << 0)
 #define                ROQ_IB2_START(x)                                ((x) << 8)