std::map<const MachineInstr*, unsigned> &ignoreInstrs,
DependenceAnalyzer &DA,
std::map<MachineInstr*, Instruction*> &machineTollvm)
- : BB(bb), Target(targ) {
+ : Target(targ) {
//Make sure BB is not null,
- assert(BB != NULL && "Basic Block is null");
-
- //DEBUG(std::cerr << "Constructing graph for " << bb << "\n");
+ assert(bb != NULL && "Basic Block is null");
+ BBs.push_back(bb);
+
//Create nodes and edges for this BB
buildNodesAndEdges(ignoreInstrs, DA, machineTollvm);
//Copies the graph and keeps a map from old to new nodes
MSchedGraph::MSchedGraph(const MSchedGraph &G,
std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes)
- : BB(G.BB), Target(G.Target) {
+ : Target(G.Target) {
+
+ BBs = G.BBs;
std::map<MSchedGraphNode*, MSchedGraphNode*> oldToNew;
//Copy all nodes
std::vector<const MachineInstr*> phiInstrs;
unsigned index = 0;
- //Loop over instructions in MBB and add nodes and edges
- for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end();
- MI != e; ++MI) {
-
- //Ignore indvar instructions
- if(ignoreInstrs.count(MI)) {
- ++index;
- continue;
- }
-
- //Get each instruction of machine basic block, get the delay
- //using the op code, create a new node for it, and add to the
- //graph.
-
- MachineOpCode opCode = MI->getOpcode();
- int delay;
+ for(std::vector<const MachineBasicBlock*>::iterator B = BBs.begin(),
+ BE = BBs.end(); B != BE; ++B) {
+
+ const MachineBasicBlock *BB = *B;
+ //Loop over instructions in MBB and add nodes and edges
+ for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end();
+ MI != e; ++MI) {
+
+ //Ignore indvar instructions
+ if(ignoreInstrs.count(MI)) {
+ ++index;
+ continue;
+ }
+
+ //Get each instruction of machine basic block, get the delay
+ //using the op code, create a new node for it, and add to the
+ //graph.
+
+ MachineOpCode opCode = MI->getOpcode();
+ int delay;
+
#if 0 // FIXME: LOOK INTO THIS
- //Check if subsequent instructions can be issued before
- //the result is ready, if so use min delay.
- if(MTI->hasResultInterlock(MIopCode))
- delay = MTI->minLatency(MIopCode);
- else
+ //Check if subsequent instructions can be issued before
+ //the result is ready, if so use min delay.
+ if(MTI->hasResultInterlock(MIopCode))
+ delay = MTI->minLatency(MIopCode);
+ else
#endif
- //Get delay
- delay = MTI->maxLatency(opCode);
-
- //Create new node for this machine instruction and add to the graph.
- //Create only if not a nop
- if(MTI->isNop(opCode))
- continue;
-
- //Sparc BE does not use PHI opcode, so assert on this case
- assert(opCode != TargetInstrInfo::PHI && "Did not expect PHI opcode");
-
- bool isBranch = false;
-
- //We want to flag the branch node to treat it special
- if(MTI->isBranch(opCode))
- isBranch = true;
-
- //Node is created and added to the graph automatically
- MSchedGraphNode *node = new MSchedGraphNode(MI, this, index, delay,
- isBranch);
-
- DEBUG(std::cerr << "Created Node: " << *node << "\n");
-
- //Check OpCode to keep track of memory operations to add memory
- //dependencies later.
- if(MTI->isLoad(opCode) || MTI->isStore(opCode))
- memInstructions.push_back(node);
-
- //Loop over all operands, and put them into the register number to
- //graph node map for determining dependencies
- //If an operands is a use/def, we have an anti dependence to itself
- for(unsigned i=0; i < MI->getNumOperands(); ++i) {
- //Get Operand
- const MachineOperand &mOp = MI->getOperand(i);
-
- //Check if it has an allocated register
- if(mOp.hasAllocatedReg()) {
- int regNum = mOp.getReg();
-
- if(regNum != SparcV9::g0) {
- //Put into our map
- regNumtoNodeMap[regNum].push_back(std::make_pair(i, node));
- }
+ //Get delay
+ delay = MTI->maxLatency(opCode);
+
+ //Create new node for this machine instruction and add to the graph.
+ //Create only if not a nop
+ if(MTI->isNop(opCode))
continue;
- }
-
-
- //Add virtual registers dependencies
- //Check if any exist in the value map already and create dependencies
- //between them.
- if(mOp.getType() == MachineOperand::MO_VirtualRegister
- || mOp.getType() == MachineOperand::MO_CCRegister) {
-
- //Make sure virtual register value is not null
- assert((mOp.getVRegValue() != NULL) && "Null value is defined");
-
- //Check if this is a read operation in a phi node, if so DO NOT PROCESS
- if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) {
- DEBUG(std::cerr << "Read Operation in a PHI node\n");
+
+ //Sparc BE does not use PHI opcode, so assert on this case
+ assert(opCode != TargetInstrInfo::PHI && "Did not expect PHI opcode");
+
+ bool isBranch = false;
+
+ //We want to flag the branch node to treat it special
+ if(MTI->isBranch(opCode))
+ isBranch = true;
+
+ //Node is created and added to the graph automatically
+ MSchedGraphNode *node = new MSchedGraphNode(MI, this, index, delay,
+ isBranch);
+
+ DEBUG(std::cerr << "Created Node: " << *node << "\n");
+
+ //Check OpCode to keep track of memory operations to add memory
+ //dependencies later.
+ if(MTI->isLoad(opCode) || MTI->isStore(opCode))
+ memInstructions.push_back(node);
+
+ //Loop over all operands, and put them into the register number to
+ //graph node map for determining dependencies
+ //If an operands is a use/def, we have an anti dependence to itself
+ for(unsigned i=0; i < MI->getNumOperands(); ++i) {
+ //Get Operand
+ const MachineOperand &mOp = MI->getOperand(i);
+
+ //Check if it has an allocated register
+ if(mOp.hasAllocatedReg()) {
+ int regNum = mOp.getReg();
+
+ if(regNum != SparcV9::g0) {
+ //Put into our map
+ regNumtoNodeMap[regNum].push_back(std::make_pair(i, node));
+ }
continue;
}
-
- if (const Value* srcI = mOp.getVRegValue()) {
- //Find value in the map
- std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
- = valuetoNodeMap.find(srcI);
- //If there is something in the map already, add edges from
- //those instructions
- //to this one we are processing
- if(V != valuetoNodeMap.end()) {
- addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs);
-
- //Add to value map
- V->second.push_back(std::make_pair(i,node));
+ //Add virtual registers dependencies
+ //Check if any exist in the value map already and create dependencies
+ //between them.
+ if(mOp.getType() == MachineOperand::MO_VirtualRegister
+ || mOp.getType() == MachineOperand::MO_CCRegister) {
+
+ //Make sure virtual register value is not null
+ assert((mOp.getVRegValue() != NULL) && "Null value is defined");
+
+ //Check if this is a read operation in a phi node, if so DO NOT PROCESS
+ if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) {
+ DEBUG(std::cerr << "Read Operation in a PHI node\n");
+ continue;
+ }
+
+ if (const Value* srcI = mOp.getVRegValue()) {
+
+ //Find value in the map
+ std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
+ = valuetoNodeMap.find(srcI);
+
+ //If there is something in the map already, add edges from
+ //those instructions
+ //to this one we are processing
+ if(V != valuetoNodeMap.end()) {
+ addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs);
+
+ //Add to value map
+ V->second.push_back(std::make_pair(i,node));
+ }
+ //Otherwise put it in the map
+ else
+ //Put into value map
+ valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node));
}
- //Otherwise put it in the map
- else
- //Put into value map
- valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node));
}
}
+ ++index;
}
- ++index;
- }
-
- //Loop over LLVM BB, examine phi instructions, and add them to our
- //phiInstr list to process
- const BasicBlock *llvm_bb = BB->getBasicBlock();
- for(BasicBlock::const_iterator I = llvm_bb->begin(), E = llvm_bb->end();
- I != E; ++I) {
- if(const PHINode *PN = dyn_cast<PHINode>(I)) {
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN);
- for (unsigned j = 0; j < tempMvec.size(); j++) {
- if(!ignoreInstrs.count(tempMvec[j])) {
- DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n");
- phiInstrs.push_back((MachineInstr*) tempMvec[j]);
- }
- }
+
+ //Loop over LLVM BB, examine phi instructions, and add them to our
+ //phiInstr list to process
+ const BasicBlock *llvm_bb = BB->getBasicBlock();
+ for(BasicBlock::const_iterator I = llvm_bb->begin(), E = llvm_bb->end();
+ I != E; ++I) {
+ if(const PHINode *PN = dyn_cast<PHINode>(I)) {
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN);
+ for (unsigned j = 0; j < tempMvec.size(); j++) {
+ if(!ignoreInstrs.count(tempMvec[j])) {
+ DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n");
+ phiInstrs.push_back((MachineInstr*) tempMvec[j]);
+ }
+ }
+ }
+
}
-
- }
-
- addMemEdges(memInstructions, DA, machineTollvm);
- addMachRegEdges(regNumtoNodeMap);
-
- //Finally deal with PHI Nodes and Value*
- for(std::vector<const MachineInstr*>::iterator I = phiInstrs.begin(),
- E = phiInstrs.end(); I != E; ++I) {
-
- //Get Node for this instruction
- std::map<const MachineInstr*, MSchedGraphNode*>::iterator X;
- X = find(*I);
-
- if(X == GraphMap.end())
- continue;
-
- MSchedGraphNode *node = X->second;
-
- DEBUG(std::cerr << "Adding ite diff edges for node: " << *node << "\n");
-
- //Loop over operands for this instruction and add value edges
- for(unsigned i=0; i < (*I)->getNumOperands(); ++i) {
- //Get Operand
- const MachineOperand &mOp = (*I)->getOperand(i);
- if((mOp.getType() == MachineOperand::MO_VirtualRegister
- || mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) {
-
- //find the value in the map
- if (const Value* srcI = mOp.getVRegValue()) {
-
- //Find value in the map
- std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
+
+ addMemEdges(memInstructions, DA, machineTollvm);
+ addMachRegEdges(regNumtoNodeMap);
+
+ //Finally deal with PHI Nodes and Value*
+ for(std::vector<const MachineInstr*>::iterator I = phiInstrs.begin(),
+ E = phiInstrs.end(); I != E; ++I) {
+
+ //Get Node for this instruction
+ std::map<const MachineInstr*, MSchedGraphNode*>::iterator X;
+ X = find(*I);
+
+ if(X == GraphMap.end())
+ continue;
+
+ MSchedGraphNode *node = X->second;
+
+ DEBUG(std::cerr << "Adding ite diff edges for node: " << *node << "\n");
+
+ //Loop over operands for this instruction and add value edges
+ for(unsigned i=0; i < (*I)->getNumOperands(); ++i) {
+ //Get Operand
+ const MachineOperand &mOp = (*I)->getOperand(i);
+ if((mOp.getType() == MachineOperand::MO_VirtualRegister
+ || mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) {
+
+ //find the value in the map
+ if (const Value* srcI = mOp.getVRegValue()) {
+
+ //Find value in the map
+ std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
= valuetoNodeMap.find(srcI);
-
- //If there is something in the map already, add edges from
- //those instructions
- //to this one we are processing
- if(V != valuetoNodeMap.end()) {
- addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(),
- phiInstrs, 1);
+
+ //If there is something in the map already, add edges from
+ //those instructions
+ //to this one we are processing
+ if(V != valuetoNodeMap.end()) {
+ addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(),
+ phiInstrs, 1);
+ }
}
}
}
}
}
}
-
//Add dependencies for Value*s
void MSchedGraph::addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
MSchedGraphNode *destNode, bool nodeIsUse,
void ModuloSchedulingPass::searchPath(MSchedGraphNode *node,
std::vector<MSchedGraphNode*> &path,
- std::set<MSchedGraphNode*> &nodesToAdd) {
+ std::set<MSchedGraphNode*> &nodesToAdd,
+ std::set<MSchedGraphNode*> &new_reccurrence) {
//Push node onto the path
path.push_back(node);
for(MSchedGraphNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE;
++S) {
- //If this node exists in a recurrence already in the partial order, then add all
- //nodes in the path to the set of nodes to add
- //Check if its already in our partial order, if not add it to the final vector
+ //Check if we should ignore this edge first
+ if(ignoreEdge(node,*S))
+ continue;
+
+ //check if successor is in this recurrence, we will get to it eventually
+ if(new_reccurrence.count(*S))
+ continue;
+
+ //If this node exists in a recurrence already in the partial
+ //order, then add all nodes in the path to the set of nodes to add
+ //Check if its already in our partial order, if not add it to the
+ //final vector
+ bool found = false;
for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
PE = partialOrder.end(); PO != PE; ++PO) {
- //Check if we should ignore this edge first
- if(ignoreEdge(node,*S))
- continue;
-
if(PO->count(*S)) {
- nodesToAdd.insert(*S);
- }
- //terminate
- else
- searchPath(*S, path, nodesToAdd);
+ found = true;
+ break;
}
+ }
+
+ if(!found) {
+ nodesToAdd.insert(*S);
+ searchPath(*S, path, nodesToAdd, new_reccurrence);
+ }
}
//Pop Node off the path
//Add nodes that connect this recurrence to recurrences in the partial path
for(std::set<MSchedGraphNode*>::iterator N = new_recurrence.begin(),
NE = new_recurrence.end(); N != NE; ++N)
- searchPath(*N, path, nodesToAdd);
+ searchPath(*N, path, nodesToAdd, new_recurrence);
//Add nodes to this recurrence if they are not already in the partial order
for(std::set<MSchedGraphNode*>::iterator N = nodesToAdd.begin(), NE = nodesToAdd.end();
E = FinalNodeOrder.end(); I != E; ++I) {
//CalculateEarly and Late start
- int EarlyStart = -1;
- int LateStart = 99999; //Set to something higher then we would ever expect (FIXME)
+ bool initialLSVal = false;
+ bool initialESVal = false;
+ int EarlyStart = 0;
+ int LateStart = 0;
bool hasSucc = false;
bool hasPred = false;
bool sched;
int ES_Temp = nodesByCycle->first + (*schedNode)->getLatency() - diff * II;
DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n");
- EarlyStart = std::max(EarlyStart, ES_Temp);
+ if(initialESVal)
+ EarlyStart = std::max(EarlyStart, ES_Temp);
+ else {
+ EarlyStart = ES_Temp;
+ initialESVal = true;
+ }
hasPred = true;
}
if((*I)->isSuccessor(*schedNode)) {
int LS_Temp = nodesByCycle->first - (*I)->getLatency() + diff * II;
DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n");
- LateStart = std::min(LateStart, LS_Temp);
+ if(initialLSVal)
+ LateStart = std::min(LateStart, LS_Temp);
+ else {
+ LateStart = LS_Temp;
+ initialLSVal = true;
+ }
hasSucc = true;
}
}
//Check if this node is a pred or succ to a branch, and restrict its placement
//even though the branch is not in the schedule
- int count = branches.size();
+ /*int count = branches.size();
for(std::vector<MSchedGraphNode*>::iterator B = branches.begin(), BE = branches.end();
B != BE; ++B) {
if((*I)->isPredecessor(*B)) {
}
count--;
- }
+ }*/
//Check if the node has no pred or successors and set Early Start to its ASAP
if(!hasSucc && !hasPred)
projects / oota-llvm.git / commitdiff