[ARM] 4331/3: Support for Micrel/Kendin KS8695 processor
authorAndrew Victor <andrew@sanpeople.com>
Fri, 11 May 2007 20:01:28 +0000 (21:01 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Fri, 11 May 2007 21:02:48 +0000 (22:02 +0100)
Add core support for the Kendin/Micrel KS8695 processor family.

It is an ARM922-T based SoC with integrated USART, 4-port Ethernet
Switch, WAN Ethernet port, and optional PCI Host bridge, etc.
 http://www.micrel.com/page.do?page=product-info/sys_on_chip.jsp

This patch is based on earlier patches from Lennert Buytenhek, Ben
Dooks and Greg Ungerer posted to the arm-linux-kernel mailing list in
March 2006;  and Micrel's 2.6.9 port.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
35 files changed:
arch/arm/Kconfig
arch/arm/Makefile
arch/arm/mach-ks8695/Kconfig [new file with mode: 0644]
arch/arm/mach-ks8695/Makefile [new file with mode: 0644]
arch/arm/mach-ks8695/Makefile.boot [new file with mode: 0644]
arch/arm/mach-ks8695/cpu.c [new file with mode: 0644]
arch/arm/mach-ks8695/devices.c [new file with mode: 0644]
arch/arm/mach-ks8695/generic.h [new file with mode: 0644]
arch/arm/mach-ks8695/irq.c [new file with mode: 0644]
arch/arm/mach-ks8695/time.c [new file with mode: 0644]
arch/arm/mm/Kconfig
include/asm-arm/arch-ks8695/debug-macro.S [new file with mode: 0644]
include/asm-arm/arch-ks8695/devices.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/dma.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/entry-macro.S [new file with mode: 0644]
include/asm-arm/arch-ks8695/hardware.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/io.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/irqs.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/memory.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/regs-gpio.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/regs-hpna.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/regs-irq.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/regs-lan.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/regs-mem.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/regs-misc.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/regs-pci.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/regs-switch.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/regs-sys.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/regs-timer.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/regs-uart.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/regs-wan.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/system.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/timex.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/uncompress.h [new file with mode: 0644]
include/asm-arm/arch-ks8695/vmalloc.h [new file with mode: 0644]

index 52c209ef58b887faf98cd10330f6a15baecb481d..638f1d8080a9abbe3af131b91e0f8d40c9f7e0de 100644 (file)
@@ -305,6 +305,12 @@ config ARCH_L7200
          If you have any questions or comments about the Linux kernel port
          to this board, send e-mail to <sjhill@cotw.com>.
 
+config ARCH_KS8695
+       bool "Micrel/Kendin KS8695"
+       help
+         Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
+         System-on-Chip devices.
+
 config ARCH_NS9XXX
        bool "NetSilicon NS9xxx"
        help
@@ -451,6 +457,8 @@ source "arch/arm/mach-ns9xxx/Kconfig"
 
 source "arch/arm/mach-davinci/Kconfig"
 
+source "arch/arm/mach-ks8695/Kconfig"
+
 # Definitions to make life easier
 config ARCH_ACORN
        bool
@@ -511,7 +519,7 @@ config ISA_DMA_API
        bool
 
 config PCI
-       bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX
+       bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695
        help
          Find out whether you have a PCI motherboard. PCI is the name of a
          bus system, i.e. the way the CPU talks to the other stuff inside
@@ -680,7 +688,8 @@ config LEDS
                   ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
                   ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
                   ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
-                  ARCH_AT91 || MACH_TRIZEPS4 || ARCH_DAVINCI
+                  ARCH_AT91 || MACH_TRIZEPS4 || ARCH_DAVINCI || \
+                  ARCH_KS8695
        help
          If you say Y here, the LEDs on your machine will be used
          to provide useful information about your current system status.
index d568d86b072979eb6e7750ad15bd52ec3ba42eb6..cbd5010d3bc3acb5b64dc99ad5ba380e2f97f409 100644 (file)
@@ -136,6 +136,7 @@ endif
  machine-$(CONFIG_ARCH_NS9XXX)    := ns9xxx
  textofs-$(CONFIG_ARCH_NS9XXX)    := 0x00108000
  machine-$(CONFIG_ARCH_DAVINCI)           := davinci
+ machine-$(CONFIG_ARCH_KS8695)     := ks8695
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)
 # This is what happens if you forget the IOCS16 line.
diff --git a/arch/arm/mach-ks8695/Kconfig b/arch/arm/mach-ks8695/Kconfig
new file mode 100644 (file)
index 0000000..44d14aa
--- /dev/null
@@ -0,0 +1,8 @@
+if ARCH_KS8695
+
+menu "Kendin/Micrel KS8695 Implementations"
+
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-ks8695/Makefile b/arch/arm/mach-ks8695/Makefile
new file mode 100644 (file)
index 0000000..0a0f496
--- /dev/null
@@ -0,0 +1,14 @@
+# arch/arm/mach-ks8695/Makefile
+#
+# Makefile for KS8695 architecture support
+#
+
+obj-y                          := cpu.o irq.o time.o devices.o
+obj-m                          :=
+obj-n                          :=
+obj-                           :=
+
+# PCI support is optional
+#obj-$(CONFIG_PCI)             += pci.o
+
+# Board-specific support
diff --git a/arch/arm/mach-ks8695/Makefile.boot b/arch/arm/mach-ks8695/Makefile.boot
new file mode 100644 (file)
index 0000000..48eb2cb
--- /dev/null
@@ -0,0 +1,8 @@
+# Note: the following conditions must always be true:
+#   ZRELADDR == virt_to_phys(TEXTADDR)
+#   PARAMS_PHYS must be within 4MB of ZRELADDR
+#   INITRD_PHYS must be in RAM
+
+   zreladdr-y  := 0x00008000
+params_phys-y  := 0x00000100
+initrd_phys-y  := 0x00800000
diff --git a/arch/arm/mach-ks8695/cpu.c b/arch/arm/mach-ks8695/cpu.c
new file mode 100644 (file)
index 0000000..407d255
--- /dev/null
@@ -0,0 +1,73 @@
+/*
+ * arch/arm/mach-ks8695/cpu.c
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * KS8695 CPU support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/regs-sys.h>
+#include <asm/arch/regs-misc.h>
+
+
+static struct __initdata map_desc ks8695_io_desc[] = {
+       {
+               .virtual        = KS8695_IO_VA,
+               .pfn            = __phys_to_pfn(KS8695_IO_PA),
+               .length         = KS8695_IO_SIZE,
+               .type           = MT_DEVICE,
+       }
+};
+
+static void __init ks8695_processor_info(void)
+{
+       unsigned long id, rev;
+
+       id = __raw_readl(KS8695_MISC_VA + KS8695_DID);
+       rev = __raw_readl(KS8695_MISC_VA + KS8695_RID);
+
+       printk("KS8695 ID=%04lx  SubID=%02lx  Revision=%02lx\n", (id & DID_ID), (rev & RID_SUBID), (rev & RID_REVISION));
+}
+
+static unsigned int sysclk[8] = { 125000000, 100000000, 62500000, 50000000, 41700000, 33300000, 31300000, 25000000 };
+static unsigned int cpuclk[8] = { 166000000, 166000000, 83000000, 83000000, 55300000, 55300000, 41500000, 41500000 };
+
+static void __init ks8695_clock_info(void)
+{
+       unsigned int scdc = __raw_readl(KS8695_SYS_VA + KS8695_CLKCON) & CLKCON_SCDC;
+
+       printk("Clocks: System %u MHz, CPU %u MHz\n",
+                       sysclk[scdc] / 1000000, cpuclk[scdc] / 1000000);
+}
+
+void __init ks8695_map_io(void)
+{
+       iotable_init(ks8695_io_desc, ARRAY_SIZE(ks8695_io_desc));
+
+       ks8695_processor_info();
+       ks8695_clock_info();
+}
diff --git a/arch/arm/mach-ks8695/devices.c b/arch/arm/mach-ks8695/devices.c
new file mode 100644 (file)
index 0000000..386593f
--- /dev/null
@@ -0,0 +1,191 @@
+/*
+ * arch/arm/mach-ks8695/devices.c
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <linux/platform_device.h>
+
+#include <asm/arch/regs-wan.h>
+#include <asm/arch/regs-lan.h>
+#include <asm/arch/regs-hpna.h>
+
+
+/* --------------------------------------------------------------------
+ *  Ethernet
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_ARM_KS8695_ETHER) || defined(CONFIG_ARM_KS8695_ETHER_MODULE)
+static u64 eth_dmamask = 0xffffffffUL;
+
+static struct resource ks8695_wan_resources[] = {
+       [0] = {
+               .start  = KS8695_WAN_VA,
+               .end    = KS8695_WAN_VA + 0x00ff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .name   = "WAN RX",
+               .start  = KS8695_IRQ_WAN_RX_STATUS,
+               .end    = KS8695_IRQ_WAN_RX_STATUS,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               .name   = "WAN TX",
+               .start  = KS8695_IRQ_WAN_TX_STATUS,
+               .end    = KS8695_IRQ_WAN_TX_STATUS,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [3] = {
+               .name   = "WAN Link",
+               .start  = KS8695_IRQ_WAN_LINK,
+               .end    = KS8695_IRQ_WAN_LINK,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device ks8695_wan_device = {
+       .name           = "ks8695_ether",
+       .id             = 0,
+       .dev            = {
+                               .dma_mask               = &eth_dmamask,
+                               .coherent_dma_mask      = 0xffffffff,
+       },
+       .resource       = ks8695_wan_resources,
+       .num_resources  = ARRAY_SIZE(ks8695_wan_resources),
+};
+
+
+static struct resource ks8695_lan_resources[] = {
+       [0] = {
+               .start  = KS8695_LAN_VA,
+               .end    = KS8695_LAN_VA + 0x00ff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .name   = "LAN RX",
+               .start  = KS8695_IRQ_LAN_RX_STATUS,
+               .end    = KS8695_IRQ_LAN_RX_STATUS,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               .name   = "LAN TX",
+               .start  = KS8695_IRQ_LAN_TX_STATUS,
+               .end    = KS8695_IRQ_LAN_TX_STATUS,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device ks8695_lan_device = {
+       .name           = "ks8695_ether",
+       .id             = 1,
+       .dev            = {
+                               .dma_mask               = &eth_dmamask,
+                               .coherent_dma_mask      = 0xffffffff,
+       },
+       .resource       = ks8695_lan_resources,
+       .num_resources  = ARRAY_SIZE(ks8695_lan_resources),
+};
+
+
+static struct resource ks8695_hpna_resources[] = {
+       [0] = {
+               .start  = KS8695_HPNA_VA,
+               .end    = KS8695_HPNA_VA + 0x00ff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .name   = "HPNA RX",
+               .start  = KS8695_IRQ_HPNA_RX_STATUS,
+               .end    = KS8695_IRQ_HPNA_RX_STATUS,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               .name   = "HPNA TX",
+               .start  = KS8695_IRQ_HPNA_TX_STATUS,
+               .end    = KS8695_IRQ_HPNA_TX_STATUS,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device ks8695_hpna_device = {
+       .name           = "ks8695_ether",
+       .id             = 2,
+       .dev            = {
+                               .dma_mask               = &eth_dmamask,
+                               .coherent_dma_mask      = 0xffffffff,
+       },
+       .resource       = ks8695_hpna_resources,
+       .num_resources  = ARRAY_SIZE(ks8695_hpna_resources),
+};
+
+void __init ks8695_add_device_wan(void)
+{
+       platform_device_register(&ks8695_wan_device);
+}
+
+void __init ks8695_add_device_lan(void)
+{
+       platform_device_register(&ks8695_lan_device);
+}
+
+void __init ks8696_add_device_hpna(void)
+{
+       platform_device_register(&ks8695_hpna_device);
+}
+#else
+void __init ks8695_add_device_wan(void) {}
+void __init ks8695_add_device_lan(void) {}
+void __init ks8696_add_device_hpna(void) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  Watchdog
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_KS8695_WATCHDOG) || defined(CONFIG_KS8695_WATCHDOG_MODULE)
+static struct platform_device ks8695_wdt_device = {
+       .name           = "ks8695_wdt",
+       .id             = -1,
+       .num_resources  = 0,
+};
+
+static void __init ks8695_add_device_watchdog(void)
+{
+       platform_device_register(&ks8695_wdt_device);
+}
+#else
+static void __init ks8695_add_device_watchdog(void) {}
+#endif
+
+
+/* -------------------------------------------------------------------- */
+
+/*
+ * These devices are always present and don't need any board-specific
+ * setup.
+ */
+static int __init ks8695_add_standard_devices(void)
+{
+       ks8695_add_device_watchdog();
+       return 0;
+}
+
+arch_initcall(ks8695_add_standard_devices);
diff --git a/arch/arm/mach-ks8695/generic.h b/arch/arm/mach-ks8695/generic.h
new file mode 100644 (file)
index 0000000..2fbfab8
--- /dev/null
@@ -0,0 +1,15 @@
+/*
+ * arch/arm/mach-ks8695/generic.h
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+*/
+
+extern __init void ks8695_map_io(void);
+extern __init void ks8695_init_irq(void);
+extern struct sys_timer ks8695_timer;
diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c
new file mode 100644 (file)
index 0000000..2407bba
--- /dev/null
@@ -0,0 +1,175 @@
+/*
+ * arch/arm/mach-ks8695/irq.c
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/ptrace.h>
+#include <linux/sysdev.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <asm/mach/irq.h>
+
+#include <asm/arch/regs-irq.h>
+#include <asm/arch/regs-gpio.h>
+
+static void ks8695_irq_mask(unsigned int irqno)
+{
+       unsigned long inten;
+
+       inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN);
+       inten &= ~(1 << irqno);
+
+       __raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN);
+}
+
+static void ks8695_irq_unmask(unsigned int irqno)
+{
+       unsigned long inten;
+
+       inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN);
+       inten |= (1 << irqno);
+
+       __raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN);
+}
+
+static void ks8695_irq_ack(unsigned int irqno)
+{
+       __raw_writel((1 << irqno), KS8695_IRQ_VA + KS8695_INTST);
+}
+
+
+static struct irq_chip ks8695_irq_level_chip;
+static struct irq_chip ks8695_irq_edge_chip;
+
+
+static int ks8695_irq_set_type(unsigned int irqno, unsigned int type)
+{
+       unsigned long ctrl, mode;
+       unsigned short level_triggered = 0;
+
+       ctrl = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC);
+
+       switch (type) {
+               case IRQT_HIGH:
+                       mode = IOPC_TM_HIGH;
+                       level_triggered = 1;
+                       break;
+               case IRQT_LOW:
+                       mode = IOPC_TM_LOW;
+                       level_triggered = 1;
+                       break;
+               case IRQT_RISING:
+                       mode = IOPC_TM_RISING;
+                       break;
+               case IRQT_FALLING:
+                       mode = IOPC_TM_FALLING;
+                       break;
+               case IRQT_BOTHEDGE:
+                       mode = IOPC_TM_EDGE;
+                       break;
+               default:
+                       return -EINVAL;
+       }
+
+       switch (irqno) {
+               case KS8695_IRQ_EXTERN0:
+                       ctrl &= ~IOPC_IOEINT0TM;
+                       ctrl |= IOPC_IOEINT0_MODE(mode);
+                       break;
+               case KS8695_IRQ_EXTERN1:
+                       ctrl &= ~IOPC_IOEINT1TM;
+                       ctrl |= IOPC_IOEINT1_MODE(mode);
+                       break;
+               case KS8695_IRQ_EXTERN2:
+                       ctrl &= ~IOPC_IOEINT2TM;
+                       ctrl |= IOPC_IOEINT2_MODE(mode);
+                       break;
+               case KS8695_IRQ_EXTERN3:
+                       ctrl &= ~IOPC_IOEINT3TM;
+                       ctrl |= IOPC_IOEINT3_MODE(mode);
+                       break;
+               default:
+                       return -EINVAL;
+       }
+
+       if (level_triggered) {
+               set_irq_chip(irqno, &ks8695_irq_level_chip);
+               set_irq_handler(irqno, handle_level_irq);
+       }
+       else {
+               set_irq_chip(irqno, &ks8695_irq_edge_chip);
+               set_irq_handler(irqno, handle_edge_irq);
+       }
+
+       __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC);
+       return 0;
+}
+
+static struct irq_chip ks8695_irq_level_chip = {
+       .ack            = ks8695_irq_mask,
+       .mask           = ks8695_irq_mask,
+       .unmask         = ks8695_irq_unmask,
+       .set_type       = ks8695_irq_set_type,
+};
+
+static struct irq_chip ks8695_irq_edge_chip = {
+       .ack            = ks8695_irq_ack,
+       .mask           = ks8695_irq_mask,
+       .unmask         = ks8695_irq_unmask,
+       .set_type       = ks8695_irq_set_type,
+};
+
+void __init ks8695_init_irq(void)
+{
+       unsigned int irq;
+
+       /* Disable all interrupts initially */
+       __raw_writel(0, KS8695_IRQ_VA + KS8695_INTMC);
+       __raw_writel(0, KS8695_IRQ_VA + KS8695_INTEN);
+
+       for (irq = 0; irq < NR_IRQS; irq++) {
+               switch (irq) {
+                       /* Level-triggered interrupts */
+                       case KS8695_IRQ_BUS_ERROR:
+                       case KS8695_IRQ_UART_MODEM_STATUS:
+                       case KS8695_IRQ_UART_LINE_STATUS:
+                       case KS8695_IRQ_UART_RX:
+                       case KS8695_IRQ_COMM_TX:
+                       case KS8695_IRQ_COMM_RX:
+                               set_irq_chip(irq, &ks8695_irq_level_chip);
+                               set_irq_handler(irq, handle_level_irq);
+                               break;
+
+                       /* Edge-triggered interrupts */
+                       default:
+                               ks8695_irq_ack(irq);    /* clear pending bit */
+                               set_irq_chip(irq, &ks8695_irq_edge_chip);
+                               set_irq_handler(irq, handle_edge_irq);
+               }
+
+               set_irq_flags(irq, IRQF_VALID);
+       }
+}
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
new file mode 100644 (file)
index 0000000..d2c86e4
--- /dev/null
@@ -0,0 +1,114 @@
+/*
+ * arch/arm/mach-ks8695/time.c
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+
+#include <asm/io.h>
+#include <asm/mach/time.h>
+
+#include <asm/arch/regs-timer.h>
+#include <asm/arch/regs-irq.h>
+
+#include "generic.h"
+
+/*
+ * Returns number of ms since last clock interrupt.  Note that interrupts
+ * will have been disabled by do_gettimeoffset()
+ */
+static unsigned long ks8695_gettimeoffset (void)
+{
+       unsigned long elapsed, tick2, intpending;
+
+       /*
+        * Get the current number of ticks.  Note that there is a race
+        * condition between us reading the timer and checking for an
+        * interrupt.  We solve this by ensuring that the counter has not
+        * reloaded between our two reads.
+        */
+       elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD);
+       do {
+               tick2 = elapsed;
+               intpending = __raw_readl(KS8695_IRQ_VA + KS8695_INTST) & (1 << KS8695_IRQ_TIMER1);
+               elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD);
+       } while (elapsed > tick2);
+
+       /* Convert to number of ticks expired (not remaining) */
+       elapsed = (CLOCK_TICK_RATE / HZ) - elapsed;
+
+       /* Is interrupt pending?  If so, then timer has been reloaded already. */
+       if (intpending)
+               elapsed += (CLOCK_TICK_RATE / HZ);
+
+       /* Convert ticks to usecs */
+       return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH;
+}
+
+/*
+ * IRQ handler for the timer.
+ */
+static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id)
+{
+       write_seqlock(&xtime_lock);
+       timer_tick();
+       write_sequnlock(&xtime_lock);
+
+       return IRQ_HANDLED;
+}
+
+static struct irqaction ks8695_timer_irq = {
+       .name           = "ks8695_tick",
+       .flags          = IRQF_DISABLED | IRQF_TIMER,
+       .handler        = ks8695_timer_interrupt,
+};
+
+static void ks8695_timer_setup(void)
+{
+       unsigned long tmout = CLOCK_TICK_RATE / HZ;
+       unsigned long tmcon;
+
+       /* disable timer1 */
+       tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
+       __raw_writel(tmcon & ~TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
+
+       __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1TC);
+       __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1PD);
+
+       /* re-enable timer1 */
+       __raw_writel(tmcon | TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
+}
+
+static void __init ks8695_timer_init (void)
+{
+       ks8695_timer_setup();
+
+       /* Enable timer interrupts */
+       setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq);
+}
+
+struct sys_timer ks8695_timer = {
+       .init           = ks8695_timer_init,
+       .offset         = ks8695_gettimeoffset,
+       .resume         = ks8695_timer_setup,
+};
index b8320a12e6b748cf80336883bde977ca4c98d122..15f0284010ca2d0e156ab5f27d532cc2b9afc5bf 100644 (file)
@@ -131,8 +131,8 @@ config CPU_ARM920T
 # ARM922T
 config CPU_ARM922T
        bool "Support ARM922T processor" if ARCH_INTEGRATOR
-       depends on ARCH_LH7A40X || ARCH_INTEGRATOR
-       default y if ARCH_LH7A40X
+       depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695
+       default y if ARCH_LH7A40X || ARCH_KS8695
        select CPU_32v4T
        select CPU_ABRT_EV4T
        select CPU_CACHE_V4WT
@@ -143,7 +143,7 @@ config CPU_ARM922T
        help
          The ARM922T is a version of the ARM920T, but with smaller
          instruction and data caches. It is used in Altera's
-         Excalibur XA device family.
+         Excalibur XA device family and Micrel's KS8695 Centaur.
 
          Say Y if you want support for the ARM922T processor.
          Otherwise, say N.
diff --git a/include/asm-arm/arch-ks8695/debug-macro.S b/include/asm-arm/arch-ks8695/debug-macro.S
new file mode 100644 (file)
index 0000000..cd5f2fb
--- /dev/null
@@ -0,0 +1,38 @@
+/*
+ * include/asm-arm/arch-ks8695/debug-macro.S
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * KS8695 - Debug macros
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/hardware.h>
+#include <asm/arch/regs-uart.h>
+
+       .macro  addruart, rx
+               mrc     p15, 0, \rx, c1, c0
+               tst     \rx, #1                         @ MMU enabled?
+               ldreq   \rx, =KS8695_UART_PA            @ physical base address
+               ldrne   \rx, =KS8695_UART_VA            @ virtual base address
+       .endm
+
+       .macro  senduart, rd, rx
+               str     \rd, [\rx, #KS8695_URTH]        @ Write to Transmit Holding Register
+       .endm
+
+       .macro  busyuart, rd, rx
+1001:          ldr     \rd, [\rx, #KS8695_URLS]        @ Read Line Status Register
+               tst     \rd, #URLS_URTE                 @ Holding & Shift registers empty?
+               beq     1001b
+       .endm
+
+       .macro  waituart, rd, rx
+1001:          ldr     \rd, [\rx, #KS8695_URLS]        @ Read Line Status Register
+               tst     \rd, #URLS_URTHRE               @ Holding Register empty?
+               beq     1001b
+       .endm
diff --git a/include/asm-arm/arch-ks8695/devices.h b/include/asm-arm/arch-ks8695/devices.h
new file mode 100644 (file)
index 0000000..b0364dc
--- /dev/null
@@ -0,0 +1,32 @@
+/*
+ * include/asm-arm/arch-ks8695/devices.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_DEVICES_H
+#define __ASM_ARCH_DEVICES_H
+
+#include <linux/pci.h>
+
+ /* Ethernet */
+extern void __init ks8695_add_device_wan(void);
+extern void __init ks8695_add_device_lan(void);
+extern void __init ks8695_add_device_hpna(void);
+
+ /* PCI */
+#define KS8695_MODE_PCI                0
+#define KS8695_MODE_MINIPCI    1
+#define KS8695_MODE_CARDBUS    2
+
+struct ks8695_pci_cfg {
+       short mode;
+       int (*map_irq)(struct pci_dev *, u8, u8);
+};
+extern __init void ks8695_init_pci(struct ks8695_pci_cfg *);
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/dma.h b/include/asm-arm/arch-ks8695/dma.h
new file mode 100644 (file)
index 0000000..e5159ed
--- /dev/null
@@ -0,0 +1,17 @@
+/*
+ * include/asm-arm/arch-ks8695/dma.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
diff --git a/include/asm-arm/arch-ks8695/entry-macro.S b/include/asm-arm/arch-ks8695/entry-macro.S
new file mode 100644 (file)
index 0000000..e34bdf8
--- /dev/null
@@ -0,0 +1,53 @@
+/*
+ * include/asm-arm/arch-ks8695/entry-macro.S
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * Low-level IRQ helper macros for KS8695
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+*/
+
+#include <asm/hardware.h>
+#include <asm/arch/regs-irq.h>
+
+       .macro  disable_fiq
+       .endm
+
+       .macro  get_irqnr_preamble, base, tmp
+               ldr     \base, =KS8695_IRQ_VA                   @ Base address of interrupt controller
+       .endm
+
+       .macro  arch_ret_to_user, tmp1, tmp2
+       .endm
+
+       .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+               ldr     \irqstat, [\base, #KS8695_INTMS]        @ Mask Status register
+
+               teq     \irqstat, #0
+               beq     1001f
+
+               mov     \irqnr, #0
+
+               tst     \irqstat, #0xff
+               moveq   \irqstat, \irqstat, lsr #8
+               addeq   \irqnr, \irqnr, #8
+               tsteq   \irqstat, #0xff
+               moveq   \irqstat, \irqstat, lsr #8
+               addeq   \irqnr, \irqnr, #8
+               tsteq   \irqstat, #0xff
+               moveq   \irqstat, \irqstat, lsr #8
+               addeq   \irqnr, \irqnr, #8
+               tst     \irqstat, #0x0f
+               moveq   \irqstat, \irqstat, lsr #4
+               addeq   \irqnr, \irqnr, #4
+               tst     \irqstat, #0x03
+               moveq   \irqstat, \irqstat, lsr #2
+               addeq   \irqnr, \irqnr, #2
+               tst     \irqstat, #0x01
+               addeqs  \irqnr, \irqnr, #1
+1001:
+       .endm
diff --git a/include/asm-arm/arch-ks8695/hardware.h b/include/asm-arm/arch-ks8695/hardware.h
new file mode 100644 (file)
index 0000000..cb732bf
--- /dev/null
@@ -0,0 +1,49 @@
+/*
+ * include/asm-arm/arch-ks8695/hardware.h
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * KS8695 - Memory Map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+
+/*
+ * Physical RAM address.
+ */
+#define KS8695_SDRAM_PA                0x00000000
+
+
+/*
+ * We map an entire MiB with the System Configuration Registers in even
+ * though only 64KiB is needed. This makes it easier for use with the
+ * head debug code as the initial MMU setup only deals in L1 sections.
+ */
+#define KS8695_IO_PA           0x03F00000
+#define KS8695_IO_VA           0xF0000000
+#define KS8695_IO_SIZE         SZ_1M
+
+#define KS8695_PCIMEM_PA       0x60000000
+#define KS8695_PCIMEM_SIZE     SZ_512M
+
+#define KS8695_PCIIO_PA                0x80000000
+#define KS8695_PCIIO_SIZE      SZ_64K
+
+
+/*
+ * PCI support
+ */
+#define pcibios_assign_all_busses()    1
+
+#define PCIBIOS_MIN_IO         0
+#define PCIBIOS_MIN_MEM                0
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/io.h b/include/asm-arm/arch-ks8695/io.h
new file mode 100644 (file)
index 0000000..8edc4bd
--- /dev/null
@@ -0,0 +1,19 @@
+/*
+ * include/asm-arm/arch-ks8695/io.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT         0xffffffff
+
+#define __io(a)                        ((void __iomem *)(a))
+#define __mem_pci(a)           (a)
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/irqs.h b/include/asm-arm/arch-ks8695/irqs.h
new file mode 100644 (file)
index 0000000..8b1c4fe
--- /dev/null
@@ -0,0 +1,54 @@
+/*
+ * linux/include/asm-arm/arch-ks8695/irqs.h
+ *
+ * Copyright (C) 2006 Simtec Electronics
+ *   Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+
+#define NR_IRQS                                32
+
+/*
+ * IRQ definitions
+ */
+#define KS8695_IRQ_COMM_RX             0
+#define KS8695_IRQ_COMM_TX             1
+#define KS8695_IRQ_EXTERN0             2
+#define KS8695_IRQ_EXTERN1             3
+#define KS8695_IRQ_EXTERN2             4
+#define KS8695_IRQ_EXTERN3             5
+#define KS8695_IRQ_TIMER0              6
+#define KS8695_IRQ_TIMER1              7
+#define KS8695_IRQ_UART_TX             8
+#define KS8695_IRQ_UART_RX             9
+#define KS8695_IRQ_UART_LINE_STATUS    10
+#define KS8695_IRQ_UART_MODEM_STATUS   11
+#define KS8695_IRQ_LAN_RX_STOP         12
+#define KS8695_IRQ_LAN_TX_STOP         13
+#define KS8695_IRQ_LAN_RX_BUF          14
+#define KS8695_IRQ_LAN_TX_BUF          15
+#define KS8695_IRQ_LAN_RX_STATUS       16
+#define KS8695_IRQ_LAN_TX_STATUS       17
+#define KS8695_IRQ_HPNA_RX_STOP                18
+#define KS8695_IRQ_HPNA_TX_STOP                19
+#define KS8695_IRQ_HPNA_RX_BUF         20
+#define KS8695_IRQ_HPNA_TX_BUF         21
+#define KS8695_IRQ_HPNA_RX_STATUS      22
+#define KS8695_IRQ_HPNA_TX_STATUS      23
+#define KS8695_IRQ_BUS_ERROR           24
+#define KS8695_IRQ_WAN_RX_STOP         25
+#define KS8695_IRQ_WAN_TX_STOP         26
+#define KS8695_IRQ_WAN_RX_BUF          27
+#define KS8695_IRQ_WAN_TX_BUF          28
+#define KS8695_IRQ_WAN_RX_STATUS       29
+#define KS8695_IRQ_WAN_TX_STATUS       30
+#define KS8695_IRQ_WAN_LINK            31
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/memory.h b/include/asm-arm/arch-ks8695/memory.h
new file mode 100644 (file)
index 0000000..24f6a6e
--- /dev/null
@@ -0,0 +1,49 @@
+/*
+ * include/asm-arm/arch-ks8695/memory.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * KS8695 Memory definitions
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <asm/hardware.h>
+
+/*
+ * Physical SRAM offset.
+ */
+#define PHYS_OFFSET            KS8695_SDRAM_PA
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_PCI
+
+/* PCI mappings */
+#define __virt_to_bus(x)       ((x) - PAGE_OFFSET + KS8695_PCIMEM_PA)
+#define __bus_to_virt(x)       ((x) - KS8695_PCIMEM_PA + PAGE_OFFSET)
+
+/* Platform-bus mapping */
+extern struct bus_type platform_bus_type;
+#define is_lbus_device(dev)            (dev && dev->bus == &platform_bus_type)
+#define __arch_dma_to_virt(dev, x)     ({ is_lbus_device(dev) ? \
+                                       __phys_to_virt(x) : __bus_to_virt(x); })
+#define __arch_virt_to_dma(dev, x)     ({ is_lbus_device(dev) ? \
+                                       (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); })
+#define __arch_page_to_dma(dev, x)     __arch_virt_to_dma(dev, page_address(x))
+
+#else
+
+#define __virt_to_bus(x)       __virt_to_phys(x)
+#define __bus_to_virt(x)       __phys_to_virt(x)
+
+#endif
+
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/regs-gpio.h b/include/asm-arm/arch-ks8695/regs-gpio.h
new file mode 100644 (file)
index 0000000..57fcf9f
--- /dev/null
@@ -0,0 +1,53 @@
+/*
+ * include/asm-arm/arch-ks8695/regs-gpio.h
+ *
+ * Copyright (C) 2007 Andrew Victor
+ *
+ * KS8695 - GPIO control registers and bit definitions.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_GPIO_H
+#define KS8695_GPIO_H
+
+#define KS8695_GPIO_OFFSET     (0xF0000 + 0xE600)
+#define KS8695_GPIO_VA         (KS8695_IO_VA + KS8695_GPIO_OFFSET)
+#define KS8695_GPIO_PA         (KS8695_IO_PA + KS8695_GPIO_OFFSET)
+
+
+#define KS8695_IOPM            (0x00)          /* I/O Port Mode Register */
+#define KS8695_IOPC            (0x04)          /* I/O Port Control Register */
+#define KS8695_IOPD            (0x08)          /* I/O Port Data Register */
+
+
+/* Port Mode Register */
+#define IOPM_(x)               (1 << (x))      /* Mode for GPIO Pin x */
+
+/* Port Control Register */
+#define IOPC_IOTIM1EN          (1 << 17)       /* GPIO Pin for Timer1 Enable */
+#define IOPC_IOTIM0EN          (1 << 16)       /* GPIO Pin for Timer0 Enable */
+#define IOPC_IOEINT3EN         (1 << 15)       /* GPIO Pin for External/Soft Interrupt 3 Enable */
+#define IOPC_IOEINT3TM         (7 << 12)       /* GPIO Pin for External/Soft Interrupt 3 Trigger Mode */
+#define IOPC_IOEINT3_MODE(x)   ((x) << 12)
+#define IOPC_IOEINT2EN         (1 << 11)       /* GPIO Pin for External/Soft Interrupt 2 Enable */
+#define IOPC_IOEINT2TM         (7 << 8)        /* GPIO Pin for External/Soft Interrupt 2 Trigger Mode */
+#define IOPC_IOEINT2_MODE(x)   ((x) << 8)
+#define IOPC_IOEINT1EN         (1 << 7)        /* GPIO Pin for External/Soft Interrupt 1 Enable */
+#define IOPC_IOEINT1TM         (7 << 4)        /* GPIO Pin for External/Soft Interrupt 1 Trigger Mode */
+#define IOPC_IOEINT1_MODE(x)   ((x) << 4)
+#define IOPC_IOEINT0EN         (1 << 3)        /* GPIO Pin for External/Soft Interrupt 0 Enable */
+#define IOPC_IOEINT0TM         (7 << 0)        /* GPIO Pin for External/Soft Interrupt 0 Trigger Mode */
+#define IOPC_IOEINT0_MODE(x)   ((x) << 0)
+
+ /* Trigger Modes */
+#define IOPC_TM_LOW            (0)             /* Level Detection (Active Low) */
+#define IOPC_TM_HIGH           (1)             /* Level Detection (Active High) */
+#define IOPC_TM_RISING         (2)             /* Rising Edge Detection */
+#define IOPC_TM_FALLING                (4)             /* Falling Edge Detection */
+#define IOPC_TM_EDGE           (6)             /* Both Edge Detection */
+
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/regs-hpna.h b/include/asm-arm/arch-ks8695/regs-hpna.h
new file mode 100644 (file)
index 0000000..14091cd
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * include/asm-arm/arch-ks8695/regs-wan.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * KS8695 - HPNA Registers and bit definitions.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_HPNA_H
+#define KS8695_HPNA_H
+
+#define KS8695_HPNA_OFFSET     (0xF0000 + 0xA000)
+#define KS8695_HPNA_VA         (KS8695_IO_VA + KS8695_HPNA_OFFSET)
+#define KS8695_HPNA_PA         (KS8695_IO_PA + KS8695_HPNA_OFFSET)
+
+
+/*
+ * HPNA registers
+ */
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/regs-irq.h b/include/asm-arm/arch-ks8695/regs-irq.h
new file mode 100644 (file)
index 0000000..70b193f
--- /dev/null
@@ -0,0 +1,41 @@
+/*
+ * include/asm-arm/arch-ks8695/regs-irq.h
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * KS8695 - IRQ registers and bit definitions
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_IRQ_H
+#define KS8695_IRQ_H
+
+#define KS8695_IRQ_OFFSET      (0xF0000 + 0xE200)
+#define KS8695_IRQ_VA          (KS8695_IO_VA + KS8695_IRQ_OFFSET)
+#define KS8695_IRQ_PA          (KS8695_IO_PA + KS8695_IRQ_OFFSET)
+
+
+/*
+ * Interrupt Controller registers
+ */
+#define KS8695_INTMC           (0x00)          /* Mode Control Register */
+#define KS8695_INTEN           (0x04)          /* Interrupt Enable Register */
+#define KS8695_INTST           (0x08)          /* Interrupt Status Register */
+#define KS8695_INTPW           (0x0c)          /* Interrupt Priority (WAN MAC) */
+#define KS8695_INTPH           (0x10)          /* Interrupt Priority (HPNA) [KS8695 only] */
+#define KS8695_INTPL           (0x14)          /* Interrupt Priority (LAN MAC) */
+#define KS8695_INTPT           (0x18)          /* Interrupt Priority (Timer) */
+#define KS8695_INTPU           (0x1c)          /* Interrupt Priority (UART) */
+#define KS8695_INTPE           (0x20)          /* Interrupt Priority (External Interrupt) */
+#define KS8695_INTPC           (0x24)          /* Interrupt Priority (Communications Channel) */
+#define KS8695_INTPBE          (0x28)          /* Interrupt Priority (Bus Error Response) */
+#define KS8695_INTMS           (0x2c)          /* Interrupt Mask Status Register */
+#define KS8695_INTHPF          (0x30)          /* Interrupt Pending Highest Priority (FIQ) */
+#define KS8695_INTHPI          (0x34)          /* Interrupt Pending Highest Priority (IRQ) */
+
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/regs-lan.h b/include/asm-arm/arch-ks8695/regs-lan.h
new file mode 100644 (file)
index 0000000..a63bd61
--- /dev/null
@@ -0,0 +1,65 @@
+/*
+ * include/asm-arm/arch-ks8695/regs-lan.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * KS8695 - LAN Registers and bit definitions.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_LAN_H
+#define KS8695_LAN_H
+
+#define KS8695_LAN_OFFSET      (0xF0000 + 0x8000)
+#define KS8695_LAN_VA          (KS8695_IO_VA + KS8695_LAN_OFFSET)
+#define KS8695_LAN_PA          (KS8695_IO_PA + KS8695_LAN_OFFSET)
+
+
+/*
+ * LAN registers
+ */
+#define KS8695_LMDTXC          (0x00)          /* DMA Transmit Control */
+#define KS8695_LMDRXC          (0x04)          /* DMA Receive Control */
+#define KS8695_LMDTSC          (0x08)          /* DMA Transmit Start Command */
+#define KS8695_LMDRSC          (0x0c)          /* DMA Receive Start Command */
+#define KS8695_LTDLB           (0x10)          /* Transmit Descriptor List Base Address */
+#define KS8695_LRDLB           (0x14)          /* Receive Descriptor List Base Address */
+#define KS8695_LMAL            (0x18)          /* MAC Station Address Low */
+#define KS8695_LMAH            (0x1c)          /* MAC Station Address High */
+#define KS8695_LMAAL_(n)       (0x80 + ((n)*8))        /* MAC Additional Station Address (0..15) Low */
+#define KS8695_LMAAH_(n)       (0x84 + ((n)*8))        /* MAC Additional Station Address (0..15) High */
+
+
+/* DMA Transmit Control Register */
+#define LMDTXC_LMTRST          (1    << 31)    /* Soft Reset */
+#define LMDTXC_LMTBS           (0x3f << 24)    /* Transmit Burst Size */
+#define LMDTXC_LMTUCG          (1    << 18)    /* Transmit UDP Checksum Generate */
+#define LMDTXC_LMTTCG          (1    << 17)    /* Transmit TCP Checksum Generate */
+#define LMDTXC_LMTICG          (1    << 16)    /* Transmit IP Checksum Generate */
+#define LMDTXC_LMTFCE          (1    <<  9)    /* Transmit Flow Control Enable */
+#define LMDTXC_LMTLB           (1    <<  8)    /* Loopback mode */
+#define LMDTXC_LMTEP           (1    <<  2)    /* Transmit Enable Padding */
+#define LMDTXC_LMTAC           (1    <<  1)    /* Transmit Add CRC */
+#define LMDTXC_LMTE            (1    <<  0)    /* TX Enable */
+
+/* DMA Receive Control Register */
+#define LMDRXC_LMRBS           (0x3f << 24)    /* Receive Burst Size */
+#define LMDRXC_LMRUCC          (1    << 18)    /* Receive UDP Checksum check */
+#define LMDRXC_LMRTCG          (1    << 17)    /* Receive TCP Checksum check */
+#define LMDRXC_LMRICG          (1    << 16)    /* Receive IP Checksum check */
+#define LMDRXC_LMRFCE          (1    <<  9)    /* Receive Flow Control Enable */
+#define LMDRXC_LMRB            (1    <<  6)    /* Receive Broadcast */
+#define LMDRXC_LMRM            (1    <<  5)    /* Receive Multicast */
+#define LMDRXC_LMRU            (1    <<  4)    /* Receive Unicast */
+#define LMDRXC_LMRERR          (1    <<  3)    /* Receive Error Frame */
+#define LMDRXC_LMRA            (1    <<  2)    /* Receive All */
+#define LMDRXC_LMRE            (1    <<  1)    /* RX Enable */
+
+/* Additional Station Address High */
+#define LMAAH_E                        (1    << 31)    /* Address Enabled */
+
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/regs-mem.h b/include/asm-arm/arch-ks8695/regs-mem.h
new file mode 100644 (file)
index 0000000..76b38e0
--- /dev/null
@@ -0,0 +1,89 @@
+/*
+ * include/asm-arm/arch-ks8695/regs-mem.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * KS8695 - Memory Controller registers and bit definitions
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_MEM_H
+#define KS8695_MEM_H
+
+#define KS8695_MEM_OFFSET      (0xF0000 + 0x4000)
+#define KS8695_MEM_VA          (KS8695_IO_VA + KS8695_MEM_OFFSET)
+#define KS8695_MEM_PA          (KS8695_IO_PA + KS8695_MEM_OFFSET)
+
+
+/*
+ * Memory Controller Registers
+ */
+#define KS8695_EXTACON0                (0x00)          /* External I/O 0 Access Control */
+#define KS8695_EXTACON1                (0x04)          /* External I/O 1 Access Control */
+#define KS8695_EXTACON2                (0x08)          /* External I/O 2 Access Control */
+#define KS8695_ROMCON0         (0x10)          /* ROM/SRAM/Flash 1 Control Register */
+#define KS8695_ROMCON1         (0x14)          /* ROM/SRAM/Flash 2 Control Register */
+#define KS8695_ERGCON          (0x20)          /* External I/O and ROM/SRAM/Flash General Register */
+#define KS8695_SDCON0          (0x30)          /* SDRAM Control Register 0 */
+#define KS8695_SDCON1          (0x34)          /* SDRAM Control Register 1 */
+#define KS8695_SDGCON          (0x38)          /* SDRAM General Control */
+#define KS8695_SDBCON          (0x3c)          /* SDRAM Buffer Control */
+#define KS8695_REFTIM          (0x40)          /* SDRAM Refresh Timer */
+
+
+/* External I/O Access Control Registers */
+#define EXTACON_EBNPTR         (0x3ff << 22)           /* Last Address Pointer */
+#define EXTACON_EBBPTR         (0x3ff << 12)           /* Base Pointer */
+#define EXTACON_EBTACT         (7     <<  9)           /* Write Enable/Output Enable Active Time */
+#define EXTACON_EBTCOH         (7     <<  6)           /* Chip Select Hold Time */
+#define EXTACON_EBTACS         (7     <<  3)           /* Address Setup Time before ECSN */
+#define EXTACON_EBTCOS         (7     <<  0)           /* Chip Select Time before OEN */
+
+/* ROM/SRAM/Flash Control Register */
+#define ROMCON_RBNPTR          (0x3ff << 22)           /* Next Pointer */
+#define ROMCON_RBBPTR          (0x3ff << 12)           /* Base Pointer */
+#define ROMCON_RBTACC          (7     <<  4)           /* Access Cycle Time */
+#define ROMCON_RBTPA           (3     <<  2)           /* Page Address Access Time */
+#define ROMCON_PMC             (3     <<  0)           /* Page Mode Configuration */
+#define                PMC_NORMAL              (0 << 0)
+#define                PMC_4WORD               (1 << 0)
+#define                PMC_8WORD               (2 << 0)
+#define                PMC_16WORD              (3 << 0)
+
+/* External I/O and ROM/SRAM/Flash General Register */
+#define ERGCON_TMULT           (3 << 28)               /* Time Multiplier */
+#define ERGCON_DSX2            (3 << 20)               /* Data Width (External I/O Bank 2) */
+#define ERGCON_DSX1            (3 << 18)               /* Data Width (External I/O Bank 1) */
+#define ERGCON_DSX0            (3 << 16)               /* Data Width (External I/O Bank 0) */
+#define ERGCON_DSR1            (3 <<  2)               /* Data Width (ROM/SRAM/Flash Bank 1) */
+#define ERGCON_DSR0            (3 <<  0)               /* Data Width (ROM/SRAM/Flash Bank 0) */
+
+/* SDRAM Control Register */
+#define SDCON_DBNPTR           (0x3ff << 22)           /* Last Address Pointer */
+#define SDCON_DBBPTR           (0x3ff << 12)           /* Base Pointer */
+#define SDCON_DBCAB            (3     <<  8)           /* Column Address Bits */
+#define SDCON_DBBNUM           (1     <<  3)           /* Number of Banks */
+#define SDCON_DBDBW            (3     <<  1)           /* Data Bus Width */
+
+/* SDRAM General Control Register */
+#define SDGCON_SDTRC           (3 << 2)                /* RAS to CAS latency */
+#define SDGCON_SDCAS           (3 << 0)                /* CAS latency */
+
+/* SDRAM Buffer Control Register */
+#define SDBCON_SDESTA          (1 << 31)               /* SDRAM Engine Status */
+#define SDBCON_RBUFBDIS                (1 << 24)               /* Read Buffer Burst Enable */
+#define SDBCON_WFIFOEN         (1 << 23)               /* Write FIFO Enable */
+#define SDBCON_RBUFEN          (1 << 22)               /* Read Buffer Enable */
+#define SDBCON_FLUSHWFIFO      (1 << 21)               /* Flush Write FIFO */
+#define SDBCON_RBUFINV         (1 << 20)               /* Read Buffer Invalidate */
+#define SDBCON_SDINI           (3 << 16)               /* SDRAM Initialization Control */
+#define SDBCON_SDMODE          (0x3fff << 0)           /* SDRAM Mode Register Value Program */
+
+/* SDRAM Refresh Timer Register */
+#define REFTIM_REFTIM          (0xffff << 0)           /* Refresh Timer Value */
+
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/regs-misc.h b/include/asm-arm/arch-ks8695/regs-misc.h
new file mode 100644 (file)
index 0000000..632ca66
--- /dev/null
@@ -0,0 +1,97 @@
+/*
+ * include/asm-arm/arch-ks8695/regs-misc.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * KS8695 - Miscellaneous Registers
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_MISC_H
+#define KS8695_MISC_H
+
+#define KS8695_MISC_OFFSET     (0xF0000 + 0xEA00)
+#define KS8695_MISC_VA         (KS8695_IO_VA + KS8695_MISC_OFFSET)
+#define KS8695_MISC_PA         (KS8695_IO_PA + KS8695_MISC_OFFSET)
+
+
+/*
+ * Miscellaneous registers
+ */
+#define KS8695_DID             (0x00)          /* Device ID */
+#define KS8695_RID             (0x04)          /* Revision ID */
+#define KS8695_HMC             (0x08)          /* HPNA Miscellaneous Control [KS8695 only] */
+#define KS8695_WMC             (0x0c)          /* WAN Miscellaneous Control */
+#define KS8695_WPPM            (0x10)          /* WAN PHY Power Management */
+#define KS8695_PPS             (0x1c)          /* PHY PowerSave */
+
+/* Device ID Register */
+#define DID_ID                 (0xffff << 0)   /* Device ID */
+
+/* Revision ID Register */
+#define RID_SUBID              (0xf << 4)      /* Sub-Device ID */
+#define RID_REVISION           (0xf << 0)      /* Revision ID */
+
+/* HPNA Miscellaneous Control Register */
+#define HMC_HSS                        (1 << 1)        /* Speed */
+#define HMC_HDS                        (1 << 0)        /* Duplex */
+
+/* WAN Miscellaneous Control Register */
+#define WMC_WANC               (1 << 30)       /* Auto-negotiation complete */
+#define WMC_WANR               (1 << 29)       /* Auto-negotiation restart */
+#define WMC_WANAP              (1 << 28)       /* Advertise Pause */
+#define WMC_WANA100F           (1 << 27)       /* Advertise 100 FDX */
+#define WMC_WANA100H           (1 << 26)       /* Advertise 100 HDX */
+#define WMC_WANA10F            (1 << 25)       /* Advertise 10 FDX */
+#define WMC_WANA10H            (1 << 24)       /* Advertise 10 HDX */
+#define WMC_WLS                        (1 << 23)       /* Link status */
+#define WMC_WDS                        (1 << 22)       /* Duplex status */
+#define WMC_WSS                        (1 << 21)       /* Speed status */
+#define WMC_WLPP               (1 << 20)       /* Link Partner Pause */
+#define WMC_WLP100F            (1 << 19)       /* Link Partner 100 FDX */
+#define WMC_WLP100H            (1 << 18)       /* Link Partner 100 HDX */
+#define WMC_WLP10F             (1 << 17)       /* Link Partner 10 FDX */
+#define WMC_WLP10H             (1 << 16)       /* Link Partner 10 HDX */
+#define WMC_WAND               (1 << 15)       /* Auto-negotiation disable */
+#define WMC_WANF100            (1 << 14)       /* Force 100 */
+#define WMC_WANFF              (1 << 13)       /* Force FDX */
+#define WMC_WLED1S             (7 <<  4)       /* LED1 Select */
+#define                WLED1S_SPEED            (0 << 4)
+#define                WLED1S_LINK             (1 << 4)
+#define                WLED1S_DUPLEX           (2 << 4)
+#define                WLED1S_COLLISION        (3 << 4)
+#define                WLED1S_ACTIVITY         (4 << 4)
+#define                WLED1S_FDX_COLLISION    (5 << 4)
+#define                WLED1S_LINK_ACTIVITY    (6 << 4)
+#define WMC_WLED0S             (7 << 0)        /* LED0 Select */
+#define                WLED0S_SPEED            (0 << 0)
+#define                WLED0S_LINK             (1 << 0)
+#define                WLED0S_DUPLEX           (2 << 0)
+#define                WLED0S_COLLISION        (3 << 0)
+#define                WLED0S_ACTIVITY         (4 << 0)
+#define                WLED0S_FDX_COLLISION    (5 << 0)
+#define                WLED0S_LINK_ACTIVITY    (6 << 0)
+
+/* WAN PHY Power Management Register */
+#define WPPM_WLPBK             (1 << 14)       /* Local Loopback */
+#define WPPM_WRLPKB            (1 << 13)       /* Remove Loopback */
+#define WPPM_WPI               (1 << 12)       /* PHY isolate */
+#define WPPM_WFL               (1 << 10)       /* Force link */
+#define WPPM_MDIXS             (1 << 9)        /* MDIX Status */
+#define WPPM_FEF               (1 << 8)        /* Far End Fault */
+#define WPPM_AMDIXP            (1 << 7)        /* Auto MDIX Parameter */
+#define WPPM_TXDIS             (1 << 6)        /* Disable transmitter */
+#define WPPM_DFEF              (1 << 5)        /* Disable Far End Fault */
+#define WPPM_PD                        (1 << 4)        /* Power Down */
+#define WPPM_DMDX              (1 << 3)        /* Disable Auto MDI/MDIX */
+#define WPPM_FMDX              (1 << 2)        /* Force MDIX */
+#define WPPM_LPBK              (1 << 1)        /* MAX Loopback */
+
+/* PHY Power Save Register */
+#define PPS_PPSM               (1 << 0)        /* PHY Power Save Mode */
+
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/regs-pci.h b/include/asm-arm/arch-ks8695/regs-pci.h
new file mode 100644 (file)
index 0000000..286d6d4
--- /dev/null
@@ -0,0 +1,53 @@
+/*
+ * include/asm-arm/arch-ks8695/regs-pci.h
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * KS8695 - PCI bridge registers and bit definitions.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define KS8695_PCI_OFFSET      (0xF0000 + 0x2000)
+#define KS8695_PCI_VA          (KS8695_IO_VA + KS8695_PCI_OFFSET)
+#define KS8695_PCI_PA          (KS8695_IO_PA + KS8695_PCI_OFFSET)
+
+
+#define KS8695_CRCFID          (0x000)         /* Configuration: Identification */
+#define KS8695_CRCFCS          (0x004)         /* Configuration: Command and Status */
+#define KS8695_CRCFRV          (0x008)         /* Configuration: Revision */
+#define KS8695_CRCFLT          (0x00C)         /* Configuration: Latency Timer */
+#define KS8695_CRCBMA          (0x010)         /* Configuration: Base Memory Address */
+#define KS8695_CRCSID          (0x02C)         /* Configuration: Subsystem ID */
+#define KS8695_CRCFIT          (0x03C)         /* Configuration: Interrupt */
+#define KS8695_PBCA            (0x100)         /* Bridge Configuration Address */
+#define KS8695_PBCD            (0x104)         /* Bridge Configuration Data */
+#define KS8695_PBM             (0x200)         /* Bridge Mode */
+#define KS8695_PBCS            (0x204)         /* Bridge Control and Status */
+#define KS8695_PMBA            (0x208)         /* Bridge Memory Base Address */
+#define KS8695_PMBAC           (0x20C)         /* Bridge Memory Base Address Control */
+#define KS8695_PMBAM           (0x210)         /* Bridge Memory Base Address Mask */
+#define KS8695_PMBAT           (0x214)         /* Bridge Memory Base Address Translation */
+#define KS8695_PIOBA           (0x218)         /* Bridge I/O Base Address */
+#define KS8695_PIOBAC          (0x21C)         /* Bridge I/O Base Address Control */
+#define KS8695_PIOBAM          (0x220)         /* Bridge I/O Base Address Mask */
+#define KS8695_PIOBAT          (0x224)         /* Bridge I/O Base Address Translation */
+
+
+/* Configuration: Identification */
+
+/* Configuration: Command and Status */
+
+/* Configuration: Revision */
+
+
+
+#define CFRV_GUEST             (1 << 23)
+
+#define PBCA_TYPE1             (1)
+#define PBCA_ENABLE            (1 << 31)
+
+
diff --git a/include/asm-arm/arch-ks8695/regs-switch.h b/include/asm-arm/arch-ks8695/regs-switch.h
new file mode 100644 (file)
index 0000000..5f37be3
--- /dev/null
@@ -0,0 +1,66 @@
+/*
+ * include/asm-arm/arch-ks8695/regs-switch.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * KS8695 - Switch Registers and bit definitions.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_SWITCH_H
+#define KS8695_SWITCH_H
+
+#define KS8695_SWITCH_OFFSET   (0xF0000 + 0xe800)
+#define KS8695_SWITCH_VA       (KS8695_IO_VA + KS8695_SWITCH_OFFSET)
+#define KS8695_SWITCH_PA       (KS8695_IO_PA + KS8695_SWITCH_OFFSET)
+
+
+/*
+ * Switch registers
+ */
+#define KS8695_SEC0            (0x00)          /* Switch Engine Control 0 */
+#define KS8695_SEC1            (0x04)          /* Switch Engine Control 1 */
+#define KS8695_SEC2            (0x08)          /* Switch Engine Control 2 */
+
+#define KS8695_P(x)_C(z)       (0xc0 + (((x)-1)*3 + ((z)-1))*4)        /* Port Configuration Registers */
+
+#define KS8695_SEP12AN         (0x48)          /* Port 1 & 2 Auto-Negotiation */
+#define KS8695_SEP34AN         (0x4c)          /* Port 3 & 4 Auto-Negotiation */
+#define KS8695_SEIAC           (0x50)          /* Indirect Access Control */
+#define KS8695_SEIADH2         (0x54)          /* Indirect Access Data High 2 */
+#define KS8695_SEIADH1         (0x58)          /* Indirect Access Data High 1 */
+#define KS8695_SEIADL          (0x5c)          /* Indirect Access Data Low */
+#define KS8695_SEAFC           (0x60)          /* Advance Feature Control */
+#define KS8695_SEDSCPH         (0x64)          /* TOS Priority High */
+#define KS8695_SEDSCPL         (0x68)          /* TOS Priority Low */
+#define KS8695_SEMAH           (0x6c)          /* Switch Engine MAC Address High */
+#define KS8695_SEMAL           (0x70)          /* Switch Engine MAC Address Low */
+#define KS8695_LPPM12          (0x74)          /* Port 1 & 2 PHY Power Management */
+#define KS8695_LPPM34          (0x78)          /* Port 3 & 4 PHY Power Management */
+
+
+/* Switch Engine Control 0 */
+#define SEC0_LLED1S            (7 << 25)       /* LED1 Select */
+#define                LLED1S_SPEED            (0 << 25)
+#define                LLED1S_LINK             (1 << 25)
+#define                LLED1S_DUPLEX           (2 << 25)
+#define                LLED1S_COLLISION        (3 << 25)
+#define                LLED1S_ACTIVITY         (4 << 25)
+#define                LLED1S_FDX_COLLISION    (5 << 25)
+#define                LLED1S_LINK_ACTIVITY    (6 << 25)
+#define SEC0_LLED0S            (7 << 22)       /* LED0 Select */
+#define                LLED0S_SPEED            (0 << 22)
+#define                LLED0S_LINK             (1 << 22)
+#define                LLED0S_DUPLEX           (2 << 22)
+#define                LLED0S_COLLISION        (3 << 22)
+#define                LLED0S_ACTIVITY         (4 << 22)
+#define                LLED0S_FDX_COLLISION    (5 << 22)
+#define                LLED0S_LINK_ACTIVITY    (6 << 22)
+#define SEC0_ENABLE            (1 << 0)        /* Enable Switch */
+
+
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/regs-sys.h b/include/asm-arm/arch-ks8695/regs-sys.h
new file mode 100644 (file)
index 0000000..f317981
--- /dev/null
@@ -0,0 +1,34 @@
+/*
+ * include/asm-arm/arch-ks8695/regs-sys.h
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * KS8695 - System control registers and bit definitions
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_SYS_H
+#define KS8695_SYS_H
+
+#define KS8695_SYS_OFFSET      (0xF0000 + 0x0000)
+#define KS8695_SYS_VA          (KS8695_IO_VA + KS8695_SYS_OFFSET)
+#define KS8695_SYS_PA          (KS8695_IO_PA + KS8695_SYS_OFFSET)
+
+
+#define KS8695_SYSCFG          (0x00)          /* System Configuration Register */
+#define KS8695_CLKCON          (0x04)          /* System Clock and Bus Control Register */
+
+
+/* System Configuration Register */
+#define SYSCFG_SPRBP           (0x3ff << 16)   /* Register Bank Base Pointer */
+
+/* System Clock and Bus Control Register */
+#define CLKCON_SFMODE          (1 << 8)        /* System Fast Mode for Simulation */
+#define CLKCON_SCDC            (7 << 0)        /* System Clock Divider Select */
+
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/regs-timer.h b/include/asm-arm/arch-ks8695/regs-timer.h
new file mode 100644 (file)
index 0000000..0a9f7f9
--- /dev/null
@@ -0,0 +1,40 @@
+/*
+ * include/asm-arm/arch-ks8695/regs-timer.h
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * KS8695 - Timer registers and bit definitions.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_TIMER_H
+#define KS8695_TIMER_H
+
+#define KS8695_TMR_OFFSET      (0xF0000 + 0xE400)
+#define KS8695_TMR_VA          (KS8695_IO_VA + KS8695_TMR_OFFSET)
+#define KS8695_TMR_PA          (KS8695_IO_PA + KS8695_TMR_OFFSET)
+
+
+/*
+ * Timer registers
+ */
+#define KS8695_TMCON           (0x00)          /* Timer Control Register */
+#define KS8695_T1TC            (0x04)          /* Timer 1 Timeout Count Register */
+#define KS8695_T0TC            (0x08)          /* Timer 0 Timeout Count Register */
+#define KS8695_T1PD            (0x0C)          /* Timer 1 Pulse Count Register */
+#define KS8695_T0PD            (0x10)          /* Timer 0 Pulse Count Register */
+
+
+/* Timer Control Register */
+#define TMCON_T1EN             (1 << 1)        /* Timer 1 Enable */
+#define TMCON_T0EN             (1 << 0)        /* Timer 0 Enable */
+
+/* Timer0 Timeout Counter Register */
+#define T0TC_WATCHDOG          (0xff)          /* Enable watchdog mode */
+
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/regs-uart.h b/include/asm-arm/arch-ks8695/regs-uart.h
new file mode 100644 (file)
index 0000000..a27cb20
--- /dev/null
@@ -0,0 +1,92 @@
+/*
+ * linux/include/asm-arm/arch-ks8695/regs-uart.h
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * KS8695 - UART register and bit definitions.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef KS8695_UART_H
+#define KS8695_UART_H
+
+#define KS8695_UART_OFFSET     (0xF0000 + 0xE000)
+#define KS8695_UART_VA         (KS8695_IO_VA + KS8695_UART_OFFSET)
+#define KS8695_UART_PA         (KS8695_IO_PA + KS8695_UART_OFFSET)
+
+
+/*
+ * UART registers
+ */
+#define KS8695_URRB    (0x00)          /* Receive Buffer Register */
+#define KS8695_URTH    (0x04)          /* Transmit Holding Register */
+#define KS8695_URFC    (0x08)          /* FIFO Control Register */
+#define KS8695_URLC    (0x0C)          /* Line Control Register */
+#define KS8695_URMC    (0x10)          /* Modem Control Register */
+#define KS8695_URLS    (0x14)          /* Line Status Register */
+#define KS8695_URMS    (0x18)          /* Modem Status Register */
+#define KS8695_URBD    (0x1C)          /* Baud Rate Divisor Register */
+#define KS8695_USR     (0x20)          /* Status Register */
+
+
+/* FIFO Control Register */
+#define URFC_URFRT     (3 << 6)        /* Receive FIFO Trigger Level */
+#define                URFC_URFRT_1    (0 << 6)
+#define                URFC_URFRT_4    (1 << 6)
+#define                URFC_URFRT_8    (2 << 6)
+#define                URFC_URFRT_14   (3 << 6)
+#define URFC_URTFR     (1 << 2)        /* Transmit FIFO Reset */
+#define URFC_URRFR     (1 << 1)        /* Receive FIFO Reset */
+#define URFC_URFE      (1 << 0)        /* FIFO Enable */
+
+/* Line Control Register */
+#define URLC_URSBC     (1 << 6)        /* Set Break Condition */
+#define URLC_PARITY    (7 << 3)        /* Parity */
+#define                URPE_NONE       (0 << 3)
+#define                URPE_ODD        (1 << 3)
+#define                URPE_EVEN       (3 << 3)
+#define                URPE_MARK       (5 << 3)
+#define                URPE_SPACE      (7 << 3)
+#define URLC_URSB      (1 << 2)        /* Stop Bits */
+#define URLC_URCL      (3 << 0)        /* Character Length */
+#define                URCL_5          (0 << 0)
+#define                URCL_6          (1 << 0)
+#define                URCL_7          (2 << 0)
+#define                URCL_8          (3 << 0)
+
+/* Modem Control Register */
+#define URMC_URLB      (1 << 4)        /* Loop-back mode */
+#define URMC_UROUT2    (1 << 3)        /* OUT2 signal */
+#define URMC_UROUT1    (1 << 2)        /* OUT1 signal */
+#define URMC_URRTS     (1 << 1)        /* Request to Send */
+#define URMC_URDTR     (1 << 0)        /* Data Terminal Ready */
+
+/* Line Status Register */
+#define URLS_URRFE     (1 << 7)        /* Receive FIFO Error */
+#define URLS_URTE      (1 << 6)        /* Transmit Empty */
+#define URLS_URTHRE    (1 << 5)        /* Transmit Holding Register Empty */
+#define URLS_URBI      (1 << 4)        /* Break Interrupt */
+#define URLS_URFE      (1 << 3)        /* Framing Error */
+#define URLS_URPE      (1 << 2)        /* Parity Error */
+#define URLS_URROE     (1 << 1)        /* Receive Overrun Error */
+#define URLS_URDR      (1 << 0)        /* Receive Data Ready */
+
+/* Modem Status Register */
+#define URMS_URDCD     (1 << 7)        /* Data Carrier Detect */
+#define URMS_URRI      (1 << 6)        /* Ring Indicator */
+#define URMS_URDSR     (1 << 5)        /* Data Set Ready */
+#define URMS_URCTS     (1 << 4)        /* Clear to Send */
+#define URMS_URDDCD    (1 << 3)        /* Delta Data Carrier Detect */
+#define URMS_URTERI    (1 << 2)        /* Trailing Edge Ring Indicator */
+#define URMS_URDDST    (1 << 1)        /* Delta Data Set Ready */
+#define URMS_URDCTS    (1 << 0)        /* Delta Clear to Send */
+
+/* Status Register */
+#define USR_UTI                (1 << 0)        /* Timeout Indication */
+
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/regs-wan.h b/include/asm-arm/arch-ks8695/regs-wan.h
new file mode 100644 (file)
index 0000000..52e35b0
--- /dev/null
@@ -0,0 +1,65 @@
+/*
+ * include/asm-arm/arch-ks8695/regs-wan.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * KS8695 - WAN Registers and bit definitions.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_WAN_H
+#define KS8695_WAN_H
+
+#define KS8695_WAN_OFFSET      (0xF0000 + 0x6000)
+#define KS8695_WAN_VA          (KS8695_IO_VA + KS8695_WAN_OFFSET)
+#define KS8695_WAN_PA          (KS8695_IO_PA + KS8695_WAN_OFFSET)
+
+
+/*
+ * WAN registers
+ */
+#define KS8695_WMDTXC          (0x00)          /* DMA Transmit Control */
+#define KS8695_WMDRXC          (0x04)          /* DMA Receive Control */
+#define KS8695_WMDTSC          (0x08)          /* DMA Transmit Start Command */
+#define KS8695_WMDRSC          (0x0c)          /* DMA Receive Start Command */
+#define KS8695_WTDLB           (0x10)          /* Transmit Descriptor List Base Address */
+#define KS8695_WRDLB           (0x14)          /* Receive Descriptor List Base Address */
+#define KS8695_WMAL            (0x18)          /* MAC Station Address Low */
+#define KS8695_WMAH            (0x1c)          /* MAC Station Address High */
+#define KS8695_WMAAL_(n)       (0x80 + ((n)*8))        /* MAC Additional Station Address (0..15) Low */
+#define KS8695_WMAAH_(n)       (0x84 + ((n)*8))        /* MAC Additional Station Address (0..15) High */
+
+
+/* DMA Transmit Control Register */
+#define WMDTXC_WMTRST          (1    << 31)    /* Soft Reset */
+#define WMDTXC_WMTBS           (0x3f << 24)    /* Transmit Burst Size */
+#define WMDTXC_WMTUCG          (1    << 18)    /* Transmit UDP Checksum Generate */
+#define WMDTXC_WMTTCG          (1    << 17)    /* Transmit TCP Checksum Generate */
+#define WMDTXC_WMTICG          (1    << 16)    /* Transmit IP Checksum Generate */
+#define WMDTXC_WMTFCE          (1    <<  9)    /* Transmit Flow Control Enable */
+#define WMDTXC_WMTLB           (1    <<  8)    /* Loopback mode */
+#define WMDTXC_WMTEP           (1    <<  2)    /* Transmit Enable Padding */
+#define WMDTXC_WMTAC           (1    <<  1)    /* Transmit Add CRC */
+#define WMDTXC_WMTE            (1    <<  0)    /* TX Enable */
+
+/* DMA Receive Control Register */
+#define WMDRXC_WMRBS           (0x3f << 24)    /* Receive Burst Size */
+#define WMDRXC_WMRUCC          (1    << 18)    /* Receive UDP Checksum check */
+#define WMDRXC_WMRTCG          (1    << 17)    /* Receive TCP Checksum check */
+#define WMDRXC_WMRICG          (1    << 16)    /* Receive IP Checksum check */
+#define WMDRXC_WMRFCE          (1    <<  9)    /* Receive Flow Control Enable */
+#define WMDRXC_WMRB            (1    <<  6)    /* Receive Broadcast */
+#define WMDRXC_WMRM            (1    <<  5)    /* Receive Multicast */
+#define WMDRXC_WMRU            (1    <<  4)    /* Receive Unicast */
+#define WMDRXC_WMRERR          (1    <<  3)    /* Receive Error Frame */
+#define WMDRXC_WMRA            (1    <<  2)    /* Receive All */
+#define WMDRXC_WMRE            (1    <<  0)    /* RX Enable */
+
+/* Additional Station Address High */
+#define WMAAH_E                        (1    << 31)    /* Address Enabled */
+
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/system.h b/include/asm-arm/arch-ks8695/system.h
new file mode 100644 (file)
index 0000000..3bc2810
--- /dev/null
@@ -0,0 +1,48 @@
+/*
+ * include/asm-arm/arch-s3c2410/system.h
+ *
+ * Copyright (C) 2006 Simtec Electronics
+ *     Ben Dooks <ben@simtec.co.uk>
+ *
+ * KS8695 - System function defines and includes
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/io.h>
+#include <asm/arch/regs-timer.h>
+
+static void arch_idle(void)
+{
+       /*
+        * This should do all the clock switching
+        * and wait for interrupt tricks,
+        */
+       cpu_do_idle();
+
+}
+
+static void arch_reset(char mode)
+{
+       unsigned int reg;
+
+       if (mode == 's')
+               cpu_reset(0);
+
+       /* disable timer0 */
+       reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
+       __raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
+
+       /* enable watchdog mode */
+       __raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
+
+       /* re-enable timer0 */
+       __raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
+}
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/timex.h b/include/asm-arm/arch-ks8695/timex.h
new file mode 100644 (file)
index 0000000..8320d52
--- /dev/null
@@ -0,0 +1,20 @@
+/*
+ * include/asm-arm/arch-ks8695/timex.h
+ *
+ * Copyright (C) 2006 Simtec Electronics
+ *     Ben Dooks <ben@simtec.co.uk>
+ *
+ * KS8695 - Time Parameters
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+/* timers are derived from MCLK, which is 25MHz */
+#define CLOCK_TICK_RATE 25000000
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/uncompress.h b/include/asm-arm/arch-ks8695/uncompress.h
new file mode 100644 (file)
index 0000000..733a508
--- /dev/null
@@ -0,0 +1,37 @@
+/*
+ * include/asm-arm/arch-ks8695/uncompress.h
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * KS8695 - Kernel uncompressor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <asm/io.h>
+#include <asm/arch/regs-uart.h>
+
+static void putc(char c)
+{
+       while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE))
+               barrier();
+
+       __raw_writel(c, KS8695_UART_PA + KS8695_URTH);
+}
+
+static inline void flush(void)
+{
+       while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTE))
+               barrier();
+}
+
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/vmalloc.h b/include/asm-arm/arch-ks8695/vmalloc.h
new file mode 100644 (file)
index 0000000..d1d88e5
--- /dev/null
@@ -0,0 +1,19 @@
+/*
+ * include/asm-arm/arch-ks8695/vmalloc.h
+ *
+ * Copyright (C) 2006 Ben Dooks
+ * Copyright (C) 2006 Simtec Electronics <linux@simtec.co.uk>
+ *
+ * KS8695 vmalloc definition
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END      (KS8695_IO_VA & PGDIR_MASK)
+
+#endif