clk: tegra: Implement locking for super clock

Although tegra_clk_register_super_mux() has a lock parameter, the lock is not
actually used by the code. Fixed with this patch.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
index 7ad48a832334c88dff1d7d7059e4763d03525edd..2fd924d38606920ce011cb51edf4adb0ab544720 100644 (file)
--- a/drivers/clk/tegra/clk-super.c
+++ b/drivers/clk/tegra/clk-super.c
@@ -73,7 +73,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
 {
        struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
        u32 val, state;
+       int err = 0;
        u8 parent_index, shift;
+       unsigned long flags = 0;
+
+       if (mux->lock)
+               spin_lock_irqsave(mux->lock, flags);
 
        val = readl_relaxed(mux->reg);
        state = val & SUPER_STATE_MASK;
@@ -92,8 +97,10 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
                                               (index == mux->pllx_index))) {
                parent_index = clk_super_get_parent(hw);
                if ((parent_index == mux->div2_index) ||
-                   (parent_index == mux->pllx_index))
-                       return -EINVAL;
+                   (parent_index == mux->pllx_index)) {
+                       err = -EINVAL;
+                       goto out;
+               }
 
                val ^= SUPER_LP_DIV2_BYPASS;
                writel_relaxed(val, mux->reg);
@@ -107,7 +114,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
 
        writel_relaxed(val, mux->reg);
        udelay(2);
-       return 0;
+
+out:
+       if (mux->lock)
+               spin_unlock_irqrestore(mux->lock, flags);
+
+       return err;
 }
 
 const struct clk_ops tegra_clk_super_ops = {