arm64: dts: rockchip: add the 4th cell for u2phy1_otg interrupts for rk3399

The ARM GICv3 #interrupt-cells need 4 cells to encode an interrupt source.
According to Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt,
the 4th cell is a phandle to a node describing a set of CPUs this interrupt
is affine to. The interrupt must be a PPI, and the node pointed must be a
subnode of the "ppi-partitions" subnode. For interrupt types other than PPI
or PPIs that are not partitionned, this cell must be zero. So we just add
0 for the 4th cell of u2phy1_otg interrupts.

Change-Id: I16ff4e4296064716fe4f7ea35946085e0473f049
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 6023e7fe46f0ece0253e1d8246fc89afa1a18562..1d9ca4d20406a94965187dca49af0955ed4b8e6e 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1401,9 +1401,9 @@
 
                        u2phy1_otg: otg-port {
                                #phy-cells = <0>;
-                               interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
-                                            <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
-                                            <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
+                                            <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
+                                            <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
                                interrupt-names = "otg-bvalid", "otg-id",
                                                  "linestate";
                                status = "disabled";