*
* Called with IRQs disabled
*/
-void rockchip_cpu_die(unsigned int cpu)
+void rockchip_cpu_die_a9(unsigned int cpu)
{
unsigned int v;
}
}
+void rockchip_cpu_die(unsigned int cpu)
+{
+ /* notify platform_cpu_kill() that hardware shutdown is finished */
+ cpumask_set_cpu(cpu, &dead_cpus);
+ flush_cache_louis();
+
+ v7_exit_coherency_flush(louis);
+
+ while (1) {
+ dsb();
+ wfi();
+ }
+}
+
int rockchip_cpu_disable(unsigned int cpu)
{
cpumask_clear_cpu(cpu, &dead_cpus);
SAVE_QOS(hevc_w_qos, HEVC_W);
rk3288_pmu_set_idle_request(IDLE_REQ_HEVC, true);
} else if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
- goto out;
+ writel_relaxed(0x20002 << (pd - PD_CPU_1), RK_CRU_VIRT + RK3288_CRU_SOFTRSTS_CON(0));
+ dsb();
}
}
RESTORE_QOS(hevc_r_qos, HEVC_R);
RESTORE_QOS(hevc_w_qos, HEVC_W);
} else if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
+ writel_relaxed(0x20000 << (pd - PD_CPU_1), RK_CRU_VIRT + RK3288_CRU_SOFTRSTS_CON(0));
+ dsb();
udelay(10);
writel_relaxed(virt_to_phys(secondary_startup), RK3288_IMEM_VIRT + 8);
writel_relaxed(0xDEADBEAF, RK3288_IMEM_VIRT + 4);
#define RK3288_CRU_GLB_SRST_FST_VALUE 0x1b0
#define RK3288_CRU_GLB_SRST_SND_VALUE 0x1b4
+#define RK3288_CRU_SOFTRST_CON 0x1b8
#define RK3288_CRU_MISC_CON 0x1e8
#define RK3288_CRU_GLB_CNT_TH 0x1ec
#define RK3288_CRU_GLB_RST_CON 0x1f0
#define RK3288_CRU_EMMC_CON0 0x218
#define RK3288_CRU_EMMC_CON1 0x21c
+#define RK3288_CRU_SOFTRSTS_CON_CNT (12)
+#define RK3288_CRU_SOFTRSTS_CON(i) (RK3288_CRU_SOFTRST_CON + ((i) * 4))
+
#endif