Staging: comedi: Move trailing statements to next line as requested by checkpatch

Signed-off-by: Bill Pemberton <wfp5p@virginia.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

diff --git a/drivers/staging/comedi/drivers/s626.c b/drivers/staging/comedi/drivers/s626.c
index 9110ae3c7fecf2d2d639c79ed6761c3f6147ff43..26cc41073b0bc2506dce375466d588eb48c89681 100644 (file)
--- a/drivers/staging/comedi/drivers/s626.c
+++ b/drivers/staging/comedi/drivers/s626.c
@@ -749,7 +749,8 @@ static int s626_attach(comedi_device *dev, comedi_devconfig *it)
                /*  Write I2C control: abort any I2C activity. */
                MC_ENABLE(P_MC2, MC2_UPLD_IIC);
                /*  Invoke command  upload */
-               while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0);
+               while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0)
+                       ;
                /*  and wait for upload to complete. */
 
                /* Per SAA7146 data sheet, write to STATUS reg twice to
@@ -758,7 +759,8 @@ static int s626_attach(comedi_device *dev, comedi_devconfig *it)
                        WR7146(P_I2CSTAT, I2C_CLKSEL);
                        /*  Write I2C control: reset  error flags. */
                        MC_ENABLE(P_MC2, MC2_UPLD_IIC); /*  Invoke command upload */
-                       while (!MC_TEST(P_MC2, MC2_UPLD_IIC));
+                       while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
+                               ;
                        /* and wait for upload to complete. */
                }
 
@@ -1592,7 +1594,8 @@ static int s626_ai_insn_read(comedi_device *dev, comedi_subdevice *s,
                /*  shift into FB BUFFER 1 register. */
 
                /*  Wait for ADC done. */
-               while (!(RR7146(P_PSR) & PSR_GPIO2)) ;
+               while (!(RR7146(P_PSR) & PSR_GPIO2))
+                       ;
 
                /*  Fetch ADC data. */
                if (n != 0)
@@ -1624,7 +1627,8 @@ static int s626_ai_insn_read(comedi_device *dev, comedi_subdevice *s,
        /*  Wait for the data to arrive in FB BUFFER 1 register. */
 
        /*  Wait for ADC done. */
-       while (!(RR7146(P_PSR) & PSR_GPIO2)) ;
+       while (!(RR7146(P_PSR) & PSR_GPIO2))
+               ;
 
        /*  Fetch ADC data from audio interface's input shift register. */
 
@@ -2462,10 +2466,12 @@ static uint32_t I2Chandshake(comedi_device *dev, uint32_t val)
        /*  upload confirmation. */
 
        MC_ENABLE(P_MC2, MC2_UPLD_IIC);
-       while (!MC_TEST(P_MC2, MC2_UPLD_IIC)) ;
+       while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
+               ;
 
        /*  Wait until I2C bus transfer is finished or an error occurs. */
-       while ((RR7146(P_I2CCTRL) & (I2C_BUSY | I2C_ERR)) == I2C_BUSY) ;
+       while ((RR7146(P_I2CCTRL) & (I2C_BUSY | I2C_ERR)) == I2C_BUSY)
+               ;
 
        /*  Return non-zero if I2C error occured. */
        return RR7146(P_I2CCTRL) & I2C_ERR;
@@ -2579,7 +2585,8 @@ static void SendDAC(comedi_device *dev, uint32_t val)
         * Done by polling the DMAC enable flag; this flag is automatically
         * cleared when the transfer has finished.
         */
-       while ((RR7146(P_MC1) & MC1_A2OUT) != 0) ;
+       while ((RR7146(P_MC1) & MC1_A2OUT) != 0)
+               ;
 
        /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
 
@@ -2596,7 +2603,8 @@ static void SendDAC(comedi_device *dev, uint32_t val)
         * finished transferring the DAC's data DWORD from the output FIFO
         * to the output buffer register.
         */
-       while ((RR7146(P_SSR) & SSR_AF2_OUT) == 0) ;
+       while ((RR7146(P_SSR) & SSR_AF2_OUT) == 0)
+               ;
 
        /* Set up to trap execution at slot 0 when the TSL sequencer cycles
         * back to slot 0 after executing the EOS in slot 5.  Also,
@@ -2632,7 +2640,8 @@ static void SendDAC(comedi_device *dev, uint32_t val)
                 * from 0xFF to 0x00, which slot 0 causes to happen by shifting
                 * out/in on SD2 the 0x00 that is always referenced by slot 5.
                 */
-                while ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0) ;
+                while ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0)
+                       ;
        }
        /* Either (1) we were too late setting the slot 0 trap; the TSL
         * sequencer restarted slot 0 before we could set the EOS trap flag,
@@ -2648,7 +2657,8 @@ static void SendDAC(comedi_device *dev, uint32_t val)
         * the next DAC write.  This is detected when FB_BUFFER2 MSB changes
         * from 0x00 to 0xFF.
         */
-       while ((RR7146(P_FB_BUFFER2) & 0xFF000000) == 0) ;
+       while ((RR7146(P_FB_BUFFER2) & 0xFF000000) == 0)
+               ;
 }
 
 static void WriteMISC2(comedi_device *dev, uint16_t NewImage)
@@ -2687,10 +2697,12 @@ static void DEBItransfer(comedi_device *dev)
 
        /*  Wait for completion of upload from shadow RAM to DEBI control */
        /*  register. */
-       while (!MC_TEST(P_MC2, MC2_UPLD_DEBI)) ;
+       while (!MC_TEST(P_MC2, MC2_UPLD_DEBI))
+               ;
 
        /*  Wait until DEBI transfer is done. */
-       while (RR7146(P_PSR) & PSR_DEBI_S) ;
+       while (RR7146(P_PSR) & PSR_DEBI_S)
+               ;
 }
 
 /*  Write a value to a gate array register. */

diff --git a/drivers/staging/comedi/proc.c b/drivers/staging/comedi/proc.c
index 1008773625772860c3876a808786054fa8d03a89..3f61828294fdeb03143310b41902c9fdc15e8e84 100644 (file)
--- a/drivers/staging/comedi/proc.c
+++ b/drivers/staging/comedi/proc.c
@@ -55,7 +55,8 @@ int comedi_read_procmem(char *buf, char **start, off_t offset, int len,
                struct comedi_device_file_info *dev_file_info = comedi_get_device_file_info(i);
                comedi_device *dev;
 
-               if (dev_file_info == NULL) continue;
+               if (dev_file_info == NULL)
+                       continue;
                dev = dev_file_info->device;
 
                if (dev->attached) {