In FastISel mode, the scheduler may be invoked multiple times

in the same block. Fix the entry-block handling to only run at
at the beginning of the entry block, and not any other times.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55817 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
index 21c12d3993f0af3c1689cbe8b2036e6abb7754da..fff444087a8f2bb8f83fdcb4c42a8aa6a9d6e594 100644 (file)
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
@@ -731,7 +731,9 @@ void ScheduleDAG::EmitLiveInCopies(MachineBasicBlock *MBB) {
 
 /// EmitSchedule - Emit the machine code in scheduled order.
 MachineBasicBlock *ScheduleDAG::EmitSchedule() {
-  bool isEntryBB = &MF->front() == BB;
+  // If we're emitting the first code into the entry block, we
+  // have additional work to do.
+  bool isEntryBB = &MF->front() == BB && BB->empty();
 
   if (isEntryBB && !SchedLiveInCopies) {
     // If this is the first basic block in the function, and if it has live ins