Fix a comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64328 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 0b7f99f42ada53bc7856dabd4029fcfeedf18e2e..a0652a72c942fa5f180acbd75e46eeb926154f8a 100644 (file)
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1252,8 +1252,8 @@ void RegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
           if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI))
             continue;
         }
-        // Don't constraint extract_subreg / insert_subreg these may be
-        // coalesced away. We don't them close to their uses.
+        // Don't constrain extract_subreg / insert_subreg; these may be
+        // coalesced away. We want them close to their uses.
         unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode();
         if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG ||
             SuccOpc == TargetInstrInfo::INSERT_SUBREG)