ARM: OMAP4: hsmmc: configure SDMMC1_DR0 properly
authorBalaji T K <balajitk@ti.com>
Mon, 3 Oct 2011 12:22:51 +0000 (17:52 +0530)
committerTony Lindgren <tony@atomide.com>
Sat, 5 Nov 2011 00:41:07 +0000 (17:41 -0700)
Fix the typo, instead it should be SDMMC1
USBC1 is not related to MMC1 I/Os

Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/mach-omap2/hsmmc.c

index d663649f69230ac96d2c275e24188d6d4db61df7..f4a1020559a7b84529f3f6f22e8ffec9ec41c6e3 100644 (file)
@@ -479,7 +479,7 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
                        OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
                reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
                        OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
-               reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
+               reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
                        OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
                        OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
                omap4_ctrl_pad_writel(reg, control_mmc1);