compatible = "rockchip-spdif";
reg = <0xff8b0000 0x10000>; //8channel
//reg = <ff880000 0x10000>;//2channel
- clocks = <&clk_spdif>, <&clk_spdif_8ch>;
- clock-names = "spdif_mclk","spdif_8ch_mclk";
+ clocks = <&clk_spdif>, <&clk_spdif_8ch>,<&clk_gates10 11>;
+ clock-names = "spdif_mclk","spdif_8ch_mclk","spdif_hclk";
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 3>;
//dmas = <&pdma0 2>; //2channel
{
struct resource *mem_res;
struct rockchip_spdif_info *spdif;
+ struct clk *spdif_hclk;
int ret;
RK_SPDIF_DBG("Entered %s\n", __func__);
return -ENXIO;
}
- spdif->clk = clk_get(&pdev->dev, "spdif_mclk");
+ spdif->clk = clk_get(&pdev->dev, "spdif_8ch_mclk");
if (IS_ERR(spdif->clk)) {
dev_err(&pdev->dev, "Can't retrieve spdif clock\n");
return PTR_ERR(spdif->clk);
clk_set_rate(spdif->clk, 11289600);
clk_prepare_enable(spdif->clk);
+ spdif_hclk = clk_get(&pdev->dev, "spdif_hclk");
+ if(IS_ERR(spdif_hclk) ) {
+ dev_err(&pdev->dev, "get spdif_hclk failed.\n");
+ } else {
+ clk_prepare_enable(spdif_hclk);
+ }
/* Request S/PDIF Register's memory region */
if (!request_mem_region(mem_res->start,