rearrange things a bit so that instructions can use subtarget features in the

future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23902 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td
index 166a98fc13a039fe942932dae1c9a08f914817f2..da63511bf1bd37b011e25259f6c5827b8690fcb3 100644 (file)
--- a/lib/Target/PowerPC/PPC.td
+++ b/lib/Target/PowerPC/PPC.td
@@ -15,16 +15,6 @@
 //
 include "../Target.td"
 
-//===----------------------------------------------------------------------===//
-// Register File Description
-//===----------------------------------------------------------------------===//
-
-include "PPCRegisterInfo.td"
-include "PPCSchedule.td"
-include "PPCInstrInfo.td"
-
-
-
 //===----------------------------------------------------------------------===//
 // PowerPC Subtarget features.
 //
@@ -41,7 +31,15 @@ def FeatureFSqrt     : SubtargetFeature<"fsqrt",
                                         "Enable the fsqrt instruction">; 
 
 //===----------------------------------------------------------------------===//
-// PowerPC chips sets supported.
+// Register File Description
+//===----------------------------------------------------------------------===//
+
+include "PPCRegisterInfo.td"
+include "PPCSchedule.td"
+include "PPCInstrInfo.td"
+
+//===----------------------------------------------------------------------===//
+// PowerPC processors supported.
 //
 
 def : Processor<"generic", G3Itineraries, []>;