FROMLIST: drm/rockchip: dw_hdmi: Set cur_ctr to 0 always
authorDouglas Anderson <dianders@chromium.org>
Wed, 26 Aug 2015 20:35:48 +0000 (13:35 -0700)
committerGerrit Code Review <gerrit@rock-chips.com>
Thu, 14 Jul 2016 06:01:43 +0000 (14:01 +0800)
Jitter was improved by lowering the MPLL bandwidth to account for high
frequency noise in the rk3288 PLL.  In each case MPLL bandwidth was
lowered only enough to get us a comfortable margin.  We believe that
lowering the bandwidth like this is safe given sufficient testing.

Change-Id: Ife266747f0e6ed46f914f4868362fefc481440f9
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9223301/)

drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

index 801110f65a63896004aea13587b39edec4ceaab4..a621118316d8fbb475e8a5d154df555bc9ce4cb0 100644 (file)
@@ -115,20 +115,8 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
        /*      pixelclk    bpp8    bpp10   bpp12 */
        {
-               40000000,  { 0x0018, 0x0018, 0x0018 },
-       }, {
-               65000000,  { 0x0028, 0x0028, 0x0028 },
-       }, {
-               66000000,  { 0x0038, 0x0038, 0x0038 },
-       }, {
-               74250000,  { 0x0028, 0x0038, 0x0038 },
-       }, {
-               83500000,  { 0x0028, 0x0038, 0x0038 },
-       }, {
-               146250000, { 0x0038, 0x0038, 0x0038 },
-       }, {
-               148500000, { 0x0000, 0x0038, 0x0038 },
-       }, {
+               600000000, { 0x0000, 0x0000, 0x0000 },
+       },  {
                ~0UL,      { 0x0000, 0x0000, 0x0000},
        }
 };