Do not codegen 'xor bool, true' as 'not reg'. not reg inverts the upper bits

of the bytereg.  This fixes yacr2, 300.twolf and probably others.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19622 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index 005433b0516342b31404f39359b3c2aa6196559e..38745076e5cb2090aef74aad1b95d35cd1b4e938 100644 (file)
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -1585,16 +1585,19 @@ unsigned ISel::SelectExpr(SDOperand N) {
 
     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1)) {
       if (CN->isAllOnesValue() && Node->getOpcode() == ISD::XOR) {
+        Opc = 0;
         switch (N.getValueType()) {
         default: assert(0 && "Cannot add this type!");
-        case MVT::i1:
+        case MVT::i1:  break;  // Not supported, don't invert upper bits!
         case MVT::i8:  Opc = X86::NOT8r;  break;
         case MVT::i16: Opc = X86::NOT16r; break;
         case MVT::i32: Opc = X86::NOT32r; break;
         }
-        Tmp1 = SelectExpr(Op0);
-        BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
-        return Result;
+        if (Opc) {
+          Tmp1 = SelectExpr(Op0);
+          BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
+          return Result;
+        }
       }
 
       switch (N.getValueType()) {