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Fix the A9 machine model. VTRN writes two registers.
author
Andrew Trick
<atrick@apple.com>
Thu, 5 Dec 2013 17:55:49 +0000
(17:55 +0000)
committer
Andrew Trick
<atrick@apple.com>
Thu, 5 Dec 2013 17:55:49 +0000
(17:55 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196514
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/ARM/ARMScheduleA9.td
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diff --git
a/lib/Target/ARM/ARMScheduleA9.td
b/lib/Target/ARM/ARMScheduleA9.td
index f34c0b0abf39fb840ae92218f2da1c1bf40e3f6a..6276cfc200dd405c52ff6dd9a0724cc14254a3f1 100644
(file)
--- a/
lib/Target/ARM/ARMScheduleA9.td
+++ b/
lib/Target/ARM/ARMScheduleA9.td
@@
-2431,7
+2431,7
@@
def :ItinRW<[A9WriteV3], [IIC_VSHLiD, IIC_VSHLiQ]>;
def :ItinRW<[A9WriteV4], [IIC_VSHLi4D, IIC_VSHLi4Q]>;
// NEON permute
-def :ItinRW<[A9WriteV2], [IIC_VPERMD, IIC_VPERMQ, IIC_VEXTD]>;
+def :ItinRW<[A9WriteV2
, A9WriteV2
], [IIC_VPERMD, IIC_VPERMQ, IIC_VEXTD]>;
def :ItinRW<[A9WriteV3, A9WriteV4, ReadDefault, A9Read2],
[IIC_VPERMQ3, IIC_VEXTQ]>;
def :ItinRW<[A9WriteV3, A9Read2], [IIC_VTB1]>;