stop emitting IDEFs for args - change to using liveIn/liveOut

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21247 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index 7ccf5cac87f710d107dd3fc94616cd8f084bbf07..5a743996ae749c12d86d9af2527bfe6bd1ba0a84 100644 (file)
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -183,7 +183,8 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
            // fixme? (well, will need to for weird FP structy stuff, 
            // see intel ABI docs)
          case MVT::f64:
-           BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
+//XXX      BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
+           MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn
            // floating point args go into f8..f15 as-needed, the increment
            argVreg[count] =                              // is below..:
            MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64));
@@ -199,7 +200,8 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
          case MVT::i16:
          case MVT::i32:
          case MVT::i64:
-           BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
+//XXX      BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
+           MF.addLiveIn(args_int[count]); // mark this register as liveIn
            argVreg[count] = 
            MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
            argPreg[count] = args_int[count];
@@ -271,6 +273,24 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
     }
   }
 
+  // Finally, inform the code generator which regs we return values in.
+  // (see the ISD::RET: case down below)
+  switch (getValueType(F.getReturnType())) {
+  default: assert(0 && "i have no idea where to return this type!");
+  case MVT::isVoid: break;
+  case MVT::i1:
+  case MVT::i8:
+  case MVT::i16:
+  case MVT::i32:
+  case MVT::i64:
+    MF.addLiveOut(IA64::r8);
+    break;
+  case MVT::f32:
+  case MVT::f64:
+    MF.addLiveOut(IA64::F8);
+    break;
+  }
+  
   return ArgValues;
 }
   
@@ -1769,10 +1789,15 @@ void ISel::Select(SDOperand N) {
       default: assert(0 && "All other types should have been promoted!!");
               // FIXME: do I need to add support for bools here?
               // (return '0' or '1' r8, basically...)
+              //
+              // FIXME: need to round floats - 80 bits is bad, the tester
+              // told me so
       case MVT::i64:
+       // we mark r8 as live on exit up above in LowerArguments() 
        BuildMI(BB, IA64::MOV, 1, IA64::r8).addReg(Tmp1);
        break;
       case MVT::f64:
+       // we mark F8 as live on exit up above in LowerArguments()
        BuildMI(BB, IA64::FMOV, 1, IA64::F8).addReg(Tmp1);
       }
       break;

diff --git a/lib/Target/IA64/IA64RegisterInfo.td b/lib/Target/IA64/IA64RegisterInfo.td
index 8a9032c548e2c81d03b99902e793d7791386e2ea..f67bc00e23f1b3a2dec498a2869a63f607cdf109 100644 (file)
--- a/lib/Target/IA64/IA64RegisterInfo.td
+++ b/lib/Target/IA64/IA64RegisterInfo.td
@@ -249,12 +249,14 @@ def GR : RegisterClass<i64, 64,
         r104, r105, r106, r107, r108, r109, r110, r111,
         r112, r113, r114, r115, r116, r117, r118, r119,
         r120, r121, r122, r123, r124, r125, r126, r127,
-       r0, r1, r2, r12, r13, r15, r22]> // these last 7 are special (look down)
+       r0, r1, r2, r12, r13, r15, r22, 
+       out0, out1, out2, out3,
+       out4, out5, out6, out7]> // these last 15 are special (look down)
 
   {
     let Methods = [{
       iterator allocation_order_end(MachineFunction &MF) const {
-       int numReservedRegs=7; // the 7 special registers r0,r1,r2,r12,r13 etc
+       int numReservedRegs=15; // the 15 special registers r0,r1,r2,r12,r13 etc
        // we also can't allocate registers for use as locals if they're
        // already required as 'out' registers
        numReservedRegs+=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;