Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do

64-bit vector shuffle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26964 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 5083e86046d1420ea5dd9f1744418e76c6fb904f..0615531a21ba3a8a894f958246246a68b7d65edf 100644 (file)
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -202,7 +202,7 @@ public:
   /// support and the code generator is tasked with not creating illegal masks.
   bool isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const {
     return isOperationLegal(ISD::VECTOR_SHUFFLE, VT) && 
-           isShuffleMaskLegal(Mask);
+           isShuffleMaskLegal(Mask, VT);
   }
 
   /// getTypeToPromoteTo - If the action for this operation is to promote, this
@@ -489,7 +489,7 @@ protected:
   /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
   /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
   /// are assumed to be legal.
-  virtual bool isShuffleMaskLegal(SDOperand Mask) const {
+  virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
     return true;
   }
   

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 73225b62d0dacabae7dbb132eca356ad638d7c85..ea3832f70c1814c9ae6d90b14265ce6001eac705 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -2371,7 +2371,10 @@ bool X86TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
 /// are assumed to be legal.
-bool X86TargetLowering::isShuffleMaskLegal(SDOperand Mask) const {
+bool
+X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
+  // Only do shuffles on 128-bit vector types for now.
+  if (MVT::getSizeInBits(VT) == 64) return false;
   return (X86::isSplatMask(Mask.Val) ||
           (Subtarget->hasSSE2() && X86::isPSHUFDMask(Mask.Val)));
 }

diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h
index e9ff015b5af5cbd4b8c05567ca34db5e1f1091b8..4a3f7a65cb25c600be461aacb713b5deafb937bd 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.h
+++ b/lib/Target/X86/X86ISelLowering.h
@@ -267,7 +267,7 @@ namespace llvm {
     /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
     /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
     /// are assumed to be legal.
-    virtual bool isShuffleMaskLegal(SDOperand Mask) const;
+    virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
   private:
     // C Calling Convention implementation.
     std::vector<SDOperand> LowerCCCArguments(Function &F, SelectionDAG &DAG);