//¶¨ÒåGPIOÏà¹Ø¼Ä´æÆ÷Æ«ÒƵØÖ·
#define GPIO_SWPORT_DR 0x00
#define GPIO_SWPORT_DDR 0x04
-#define GPIO_INTEN 0x30
+#define GPIO_INTEN 0x30
#define GPIO_INTMASK 0x34
#define GPIO_INTTYPE_LEVEL 0x38
#define GPIO_INT_POLARITY 0x3c
#define RK30_PIN6_PA5 (6*NUM_GROUP + PIN_BASE + 5)
#define RK30_PIN6_PA6 (6*NUM_GROUP + PIN_BASE + 6)
#define RK30_PIN6_PA7 (6*NUM_GROUP + PIN_BASE + 7)
-
#define RK30_PIN6_PB0 (6*NUM_GROUP + PIN_BASE + 8)
#define RK30_PIN6_PB1 (6*NUM_GROUP + PIN_BASE + 9)
#define RK30_PIN6_PB2 (6*NUM_GROUP + PIN_BASE + 10)
#define RK30_PIN6_PB6 (6*NUM_GROUP + PIN_BASE + 14)
#define RK30_PIN6_PB7 (6*NUM_GROUP + PIN_BASE + 15)
-#define RK30_PIN6_PD7 (6*NUM_GROUP + PIN_BASE + 31)
-
#if defined(CONFIG_SPI_FPGA_GPIO)
#define FPGA_PIO0_00 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 0)
#define FPGA_PIO0_01 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 1)
#ifdef CONFIG_I2C3_RK30
rk30_mux_api_set(GPIO3A3_I2C3SCL_NAME, GPIO3A_I2C3_SCL);
- rk30_mux_api_set(GPIO3A2_I2C3SDA_NAME, GPIO3A_I2C2_SDA);
+ rk30_mux_api_set(GPIO3A2_I2C3SDA_NAME, GPIO3A_I2C3_SDA);
#endif
#ifdef CONFIG_I2C4_RK30
- rk30_mux_api_set(GPIO3A5_I2C4SCL_NAME, GPIO3A_I2C3_SCL);
- rk30_mux_api_set(GPIO3A4_I2C4SDA_NAME, GPIO3A_I2C2_SDA);
+ rk30_mux_api_set(GPIO3A5_I2C4SCL_NAME, GPIO3A_I2C4_SCL);
+ rk30_mux_api_set(GPIO3A4_I2C4SDA_NAME, GPIO3A_I2C4_SDA);
#endif
#ifdef CONFIG_RK30_VMAC
#include <asm/gpio.h>
#include <asm/mach/irq.h>
-#define MAX_PIN RK30_PIN6_PD7
+#define MAX_PIN RK30_PIN6_PB7
#define to_rk30_gpio_bank(c) container_of(c, struct rk30_gpio_bank, chip)
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
- rk30_gpio_bit_op((void *__iomem) RK30_GRF_BASE, 0x78 + bank->id * 4, offset_to_bit(offset), !enable);
+ if(offset>=16)
+ rk30_gpio_bit_op((void *__iomem) RK30_GRF_BASE, GRF_GPIO0H_PULL + bank->id * 8, offset_to_bit(offset-16), !enable);
+ else
+ rk30_gpio_bit_op((void *__iomem) RK30_GRF_BASE, GRF_GPIO0L_PULL + bank->id * 8, offset_to_bit(offset), !enable);
spin_unlock_irqrestore(&bank->lock, flags);
return 0;