#define INT_QUAD_RES_30 (INT_QUAD_BASE + 30)
#define INT_QUAD_RES_31 (INT_QUAD_BASE + 31)
-#define INT_MAIN_NR (INT_QUAD_BASE + 32 - INT_PRI_BASE)
-
+/* Tegra30 has 5 banks of 32 IRQs */
+#define INT_MAIN_NR (32 * 5)
#define INT_GPIO_BASE (INT_PRI_BASE + INT_MAIN_NR)
-#define INT_GPIO_NR (28 * 8)
+/* Tegra30 has 8 banks of 32 GPIOs */
+#define INT_GPIO_NR (32 * 8)
#define TEGRA_NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR)
#define ICTLR_COP_IER_CLR 0x38
#define ICTLR_COP_IEP_CLASS 0x3c
-#define NUM_ICTLRS 4
#define FIRST_LEGACY_IRQ 32
+static int num_ictlrs;
+
static void __iomem *ictlr_reg_base[] = {
IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
+ IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
};
static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
u32 mask;
BUG_ON(irq < FIRST_LEGACY_IRQ ||
- irq >= FIRST_LEGACY_IRQ + NUM_ICTLRS * 32);
+ irq >= FIRST_LEGACY_IRQ + num_ictlrs * 32);
base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
void __init tegra_init_irq(void)
{
int i;
+ void __iomem *distbase;
+
+ distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
+ num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) & 0x1f;
+
+ if (num_ictlrs > ARRAY_SIZE(ictlr_reg_base)) {
+ WARN(1, "Too many (%d) interrupt controllers found. Maximum is %d.",
+ num_ictlrs, ARRAY_SIZE(ictlr_reg_base));
+ num_ictlrs = ARRAY_SIZE(ictlr_reg_base);
+ }
- for (i = 0; i < NUM_ICTLRS; i++) {
+ for (i = 0; i < num_ictlrs; i++) {
void __iomem *ictlr = ictlr_reg_base[i];
writel(~0, ictlr + ICTLR_CPU_IER_CLR);
writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
* initialized elsewhere under DT.
*/
if (!of_have_populated_dt())
- gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
+ gic_init(0, 29, distbase,
IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
}