Add instruction encoding for DMB/DSB

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91053 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 5e8eae59af252058f4869455db480e588fa42562..ccb3a8684a4cb43f25d04036e04052ba57ad9487 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1574,18 +1574,26 @@ def MOVCCi : AI1<0b1101, (outs GPR:$dst),
 //
 
 // memory barriers protect the atomic sequences
-let isBarrier = 1 in {
+let isBarrier = 1, isPredicable = 0 in {
 def Int_MemBarrierV7 : AI<(outs), (ins),
                         Pseudo, NoItinerary,
                         "dmb", "",
                         [(ARMMemBarrier)]>,
-                        Requires<[HasV7]>;
+                        Requires<[HasV7]> {
+  let Inst{31-4} = 0xf57ff05;
+  // FIXME: add support for options other than a full system DMB
+  let Inst{3-0} = 0b1111;
+}
 
 def Int_SyncBarrierV7 : AI<(outs), (ins),
                         Pseudo, NoItinerary,
                         "dsb", "",
                         [(ARMSyncBarrier)]>,
-                        Requires<[HasV7]>;
+                        Requires<[HasV7]> {
+  let Inst{31-4} = 0xf57ff04;
+  // FIXME: add support for options other than a full system DSB
+  let Inst{3-0} = 0b1111;
+}
 }
 
 //===----------------------------------------------------------------------===//