don't lie to the register allocator

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20784 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index d25c36eb7fa88121fd1f6bfb0896387ada9b7ec2..abf9934f56e2ffa7da66314a673ab2ab174e8cb2 100644 (file)
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1068,7 +1068,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
         unsigned Tmp9 = MakeReg(MVT::f64);
         
         BuildMI(BB, Alpha::STQ, 3).addReg(Tmp1).addFrameIndex(FrameIdxL).addReg(Alpha::F31);
-        BuildMI(BB, Alpha::STQ, 3).addReg(Tmp1).addFrameIndex(FrameIdxR).addReg(Alpha::F31);
+        BuildMI(BB, Alpha::STQ, 3).addReg(Tmp2).addFrameIndex(FrameIdxR).addReg(Alpha::F31);
         BuildMI(BB, Alpha::LDT, 2, Tmp4).addFrameIndex(FrameIdxL).addReg(Alpha::F31);
         BuildMI(BB, Alpha::LDT, 2, Tmp5).addFrameIndex(FrameIdxR).addReg(Alpha::F31);
         BuildMI(BB, Alpha::CVTQT, 1, Tmp6).addReg(Tmp4);
@@ -1076,7 +1076,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
         BuildMI(BB, Alpha::DIVT, 2, Tmp8).addReg(Tmp6).addReg(Tmp7);
         BuildMI(BB, Alpha::CVTTQ, 1, Tmp9).addReg(Tmp8);
         BuildMI(BB, Alpha::STT, 3).addReg(Tmp9).addFrameIndex(FrameIdxF).addReg(Alpha::F31);
-        BuildMI(BB, Alpha::LDQ, 3).addReg(Result).addFrameIndex(FrameIdxF).addReg(Alpha::F31);
+        BuildMI(BB, Alpha::LDQ, 2, Result).addFrameIndex(FrameIdxF).addReg(Alpha::F31);
         return Result;
       }