Fix broken CHECK lines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199016 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/Analysis/TypeBasedAliasAnalysis/memcpyopt.ll b/test/Analysis/TypeBasedAliasAnalysis/memcpyopt.ll
index 6fd6eaca012e9bbbc0253d7454fce23e6e6e9237..cdf72811ce5f6d71f62327d56228ce4f0d75dd7b 100644 (file)
--- a/test/Analysis/TypeBasedAliasAnalysis/memcpyopt.ll
+++ b/test/Analysis/TypeBasedAliasAnalysis/memcpyopt.ll
@@ -18,8 +18,8 @@ define void @foo(i8* nocapture %p, i8* nocapture %q, i8* nocapture %s) nounwind
 
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
 
-; CHECK [[TAGA]] = metadata !{metadata [[TYPEA:!.*]], metadata [[TYPEA]], i64 0}
-; CHECK [[TYPEA]] = metadata !{metadata !"A", metadata !{{.*}}}
+; CHECK: [[TAGA]] = metadata !{metadata [[TYPEA:!.*]], metadata [[TYPEA]], i64 0}
+; CHECK: [[TYPEA]] = metadata !{metadata !"A", metadata !{{.*}}}
 !0 = metadata !{metadata !"tbaa root", null}
 !1 = metadata !{metadata !3, metadata !3, i64 0}
 !2 = metadata !{metadata !4, metadata !4, i64 0}

diff --git a/test/Assembler/functionlocal-metadata.ll b/test/Assembler/functionlocal-metadata.ll
index 0d93bfdb275da71419a14abec5d7b07ded7ae71b..f9b1d74037964ff2613975027e3c69304e27e51a 100644 (file)
--- a/test/Assembler/functionlocal-metadata.ll
+++ b/test/Assembler/functionlocal-metadata.ll
@@ -53,4 +53,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 ; CHECK: ![[ID0]] = metadata !{i32 662302, i32 26, metadata ![[ID1]], null}
 ; CHECK: ![[ID1]] = metadata !{i32 4, metadata !"foo"}
 ; CHECK: ![[ID2]] = metadata !{metadata !"bar"}
-; CHECK; ![[ID3]] = metadata !{metadata !"foo"}
+; CHECK: ![[ID3]] = metadata !{metadata !"foo"}

diff --git a/test/CodeGen/ARM/atomic-load-store.ll b/test/CodeGen/ARM/atomic-load-store.ll
index 53c7184d2a84b75695f267ad206ceb508d489e0b..45a263d323b3d00983cdd491160da8e624d24bd4 100644 (file)
--- a/test/CodeGen/ARM/atomic-load-store.ll
+++ b/test/CodeGen/ARM/atomic-load-store.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=ARM
 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s -check-prefix=THUMBTWO
 ; RUN: llc < %s -mtriple=thumbv6-apple-ios | FileCheck %s -check-prefix=THUMBONE
-; RUN  llc < %s -mtriple=armv4-apple-ios | FileCheck %s -check-prefix=ARMV4
+; RUN: llc < %s -mtriple=armv4-apple-ios | FileCheck %s -check-prefix=ARMV4
 
 define void @test1(i32* %ptr, i32 %val1) {
 ; ARM: test1

diff --git a/test/CodeGen/ARM/divmod-eabi.ll b/test/CodeGen/ARM/divmod-eabi.ll
index 7a46af1e6742b67ee0299e87fdd3092f4ff9c615..7f72048d391eba70084db64d145905ac4736d089 100644 (file)
--- a/test/CodeGen/ARM/divmod-eabi.ll
+++ b/test/CodeGen/ARM/divmod-eabi.ll
@@ -189,7 +189,7 @@ entry:
   %div = sdiv i32 %a, %b
 ; EABI: __aeabi_idivmod
 ; EABI: mov [[div:r[0-9]+]], r0
-; GNU __aeabi_idiv
+; GNU: __aeabi_idiv
 ; GNU: mov [[sum:r[0-9]+]], r0
 ; DARWIN: ___divsi3
 ; DARWIN: mov [[sum:r[0-9]+]], r0

diff --git a/test/CodeGen/Mips/blockaddr.ll b/test/CodeGen/Mips/blockaddr.ll
index 41c5c8f75f5cbc51490adb4249424933e070c8ac..d0319cab2db728a2bc9f67441ff7dd6b819c9a14 100644 (file)
--- a/test/CodeGen/Mips/blockaddr.ll
+++ b/test/CodeGen/Mips/blockaddr.ll
@@ -43,8 +43,8 @@ entry:
 ; STATIC-MIPS16-1: li  $[[R1_16:[0-9]+]], %hi($tmp[[TI_16:[0-9]+]])
 ; STATIC-MIPS16-1: sll ${{[0-9]+}},  $[[R1_16]], 16
 ; STATIC-MIPS16-2: li  ${{[0-9]+}}, %lo($tmp{{[0-9]+}})
-; STATIC-MIPS16-1 jal  dummy
-; STATIC-MIPS16-2 jal  dummy
+; STATIC-MIPS16-1: jal dummy
+; STATIC-MIPS16-2: jal dummy
 
 define void @f() nounwind {
 entry:

diff --git a/test/CodeGen/Mips/const4a.ll b/test/CodeGen/Mips/const4a.ll
index bec61cfc5f49ffcc70ca2c0ec56fa05211acccc8..b4c509fcd8c03158b3acfc042d4b58386ba43ce8 100644 (file)
--- a/test/CodeGen/Mips/const4a.ll
+++ b/test/CodeGen/Mips/const4a.ll
@@ -15,7 +15,7 @@ define void @t() #0 {
 entry:
   store i32 -559023410, i32* @i, align 4
   %0 = load i32* @b, align 4
-; no-load-relax        lw      ${{[0-9]+}}, $CPI0_1    # 16 bit inst
+; no-load-relax:       lw      ${{[0-9]+}}, $CPI0_1    # 16 bit inst
   %tobool = icmp ne i32 %0, 0
   br i1 %tobool, label %if.then, label %if.else
 ; no-load-relax:       beqz    ${{[0-9]+}}, $BB0_3

diff --git a/test/CodeGen/R600/gep-address-space.ll b/test/CodeGen/R600/gep-address-space.ll
index 4ea21dde8a059aa17d79612b5adb1019864a4bf5..494b815674c63447a8ec7818c9ca88471a0bef63 100644 (file)
--- a/test/CodeGen/R600/gep-address-space.ll
+++ b/test/CodeGen/R600/gep-address-space.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck %s
 
 define void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind {
-; CHECK-LABEL @use_gep_address_space:
+; CHECK-LABEL: @use_gep_address_space:
 ; CHECK: S_ADD_I32
   %p = getelementptr [1024 x i32] addrspace(3)* %array, i16 0, i16 16
   store i32 99, i32 addrspace(3)* %p

diff --git a/test/CodeGen/R600/lds-output-queue.ll b/test/CodeGen/R600/lds-output-queue.ll
index 63a4332d3c410c8e8b093cebb32b07cf7c5d1b94..af0db0d65666d5ae7de61eea10b577616b19b365 100644 (file)
--- a/test/CodeGen/R600/lds-output-queue.ll
+++ b/test/CodeGen/R600/lds-output-queue.ll
@@ -87,7 +87,7 @@ declare void @llvm.AMDGPU.barrier.local()
 ; CHECK-LABEL: @local_global_alias
 ; CHECK: LDS_READ_RET
 ; CHECK-NOT: ALU clause
-; CHECK MOV * T{{[0-9]\.[XYZW]}}, OQAP
+; CHECK: MOV * T{{[0-9]\.[XYZW]}}, OQAP
 define void @local_global_alias(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 entry:
   %0 = getelementptr inbounds [2 x i32] addrspace(3)* @local_mem, i32 0, i32 0

diff --git a/test/CodeGen/R600/llvm.SI.tbuffer.store.ll b/test/CodeGen/R600/llvm.SI.tbuffer.store.ll
index fa7c3cabadc5cd44c0417854e59f4eb2f86cdfa1..33f663b3a6d50cfc04cebe960c0990f63409b000 100644 (file)
--- a/test/CodeGen/R600/llvm.SI.tbuffer.store.ll
+++ b/test/CodeGen/R600/llvm.SI.tbuffer.store.ll
@@ -1,6 +1,6 @@
 ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
 
-;CHECK_LABEL: @test1
+;CHECK-LABEL: @test1
 ;CHECK: TBUFFER_STORE_FORMAT_XYZW {{v\[[0-9]+:[0-9]+\]}}, 32, -1, 0, -1, 0, 14, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
 define void @test1(i32 %a1, i32 %vaddr) {
     %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0
@@ -10,7 +10,7 @@ define void @test1(i32 %a1, i32 %vaddr) {
     ret void
 }
 
-;CHECK_LABEL: @test2
+;CHECK-LABEL: @test2
 ;CHECK: TBUFFER_STORE_FORMAT_XYZ {{v\[[0-9]+:[0-9]+\]}}, 24, -1, 0, -1, 0, 13, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
 define void @test2(i32 %a1, i32 %vaddr) {
     %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0
@@ -20,7 +20,7 @@ define void @test2(i32 %a1, i32 %vaddr) {
     ret void
 }
 
-;CHECK_LABEL: @test3
+;CHECK-LABEL: @test3
 ;CHECK: TBUFFER_STORE_FORMAT_XY {{v\[[0-9]+:[0-9]+\]}}, 16, -1, 0, -1, 0, 11, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
 define void @test3(i32 %a1, i32 %vaddr) {
     %vdata = insertelement <2 x i32> undef, i32 %a1, i32 0
@@ -30,7 +30,7 @@ define void @test3(i32 %a1, i32 %vaddr) {
     ret void
 }
 
-;CHECK_LABEL: @test4
+;CHECK-LABEL: @test4
 ;CHECK: TBUFFER_STORE_FORMAT_X {{v[0-9]+}}, 8, -1, 0, -1, 0, 4, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
 define void @test4(i32 %vdata, i32 %vaddr) {
     call void @llvm.SI.tbuffer.store.i32(<16 x i8> undef, i32 %vdata,

diff --git a/test/CodeGen/R600/local-memory.ll b/test/CodeGen/R600/local-memory.ll
index 2168a3d0bd2759ed596722cd2ed5727aa420764c..8db78ad46a6146918f1437f724a03c8a2847676e 100644 (file)
--- a/test/CodeGen/R600/local-memory.ll
+++ b/test/CodeGen/R600/local-memory.ll
@@ -17,7 +17,7 @@
 ; CI-CHECK-NEXT: .long 32768
 
 ; EG-CHECK: LDS_WRITE
-; SI-CHECK_NOT: S_WQM_B64
+; SI-CHECK-NOT: S_WQM_B64
 ; SI-CHECK: DS_WRITE_B32 0
 
 ; GROUP_BARRIER must be the last instruction in a clause

diff --git a/test/CodeGen/R600/private-memory.ll b/test/CodeGen/R600/private-memory.ll
index 48a013c8e5498f4c9348b2dafd5755a3cbe69053..848d164eebd0c251830bd05330b7d4d991b47db1 100644 (file)
--- a/test/CodeGen/R600/private-memory.ll
+++ b/test/CodeGen/R600/private-memory.ll
@@ -77,7 +77,7 @@ entry:
 ; loads and stores should be lowered to copies, so there shouldn't be any
 ; MOVA instructions.
 
-; R600-CHECK-LABLE: @direct_loop
+; R600-CHECK-LABEL: @direct_loop
 ; R600-CHECK-NOT: MOVA_INT
 ; SI-CHECK-LABEL: @direct_loop
 ; SI-CHECK-NOT: V_MOVREL

diff --git a/test/CodeGen/R600/vtx-schedule.ll b/test/CodeGen/R600/vtx-schedule.ll
index 97d37ed84ce2afeb3a98a275986abc629374a909..ce852c5efeffffa7bddc216306efa862fab3cae4 100644 (file)
--- a/test/CodeGen/R600/vtx-schedule.ll
+++ b/test/CodeGen/R600/vtx-schedule.ll
@@ -6,9 +6,9 @@
 
 ; CHECK: @test
 ; CHECK: Fetch clause
-; CHECK_VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 0
+; CHECK: VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 0
 ; CHECK: Fetch clause
-; CHECK_VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 0
+; CHECK: VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 0
 define void @test(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* addrspace(1)* nocapture %in0) {
 entry:
   %0 = load i32 addrspace(1)* addrspace(1)* %in0

diff --git a/test/CodeGen/SPARC/ctpop.ll b/test/CodeGen/SPARC/ctpop.ll
index 280ed29703a21a5764a201359333150b93671faf..89c95ede4d1bc56783b8d5222e67322b02dcab57 100644 (file)
--- a/test/CodeGen/SPARC/ctpop.ll
+++ b/test/CodeGen/SPARC/ctpop.ll
@@ -5,7 +5,7 @@
 declare i32 @llvm.ctpop.i32(i32)
 
 ; V8-LABEL: test
-; V8-NOT  : popc
+; V8-NOT: popc
 
 ; V9-LABEL: test
 ; V9:       srl %o0, 0, %o0

diff --git a/test/CodeGen/Thumb/unord.ll b/test/CodeGen/Thumb/unord.ll
index 41a002efd651a5207aa0b42b6f9e6478290dc3d1..3cf9ebfa0373c4863a8a6712514bb9bef980cac5 100644 (file)
--- a/test/CodeGen/Thumb/unord.ll
+++ b/test/CodeGen/Thumb/unord.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s
 
 define i32 @f1(float %X, float %Y) {
-; CHECK-LABEL _f1:
+; CHECK-LABEL: _f1:
 ; CHECK: bne
 ; CHECK: .data_region
 ; CHECK: .long   ___unordsf2
@@ -11,7 +11,7 @@ define i32 @f1(float %X, float %Y) {
 }
 
 define i32 @f2(float %X, float %Y) {
-; CHECK-LABEL _f2:
+; CHECK-LABEL: _f2:
 ; CHECK: beq
 ; CHECK: .data_region
 ; CHECK: .long   ___unordsf2

diff --git a/test/CodeGen/Thumb2/tail-call-r9.ll b/test/CodeGen/Thumb2/tail-call-r9.ll
index 24c76c98c03ac78d1caba08b15729d4a27389578..673aa7c12ebc4131222ec90f2f3da3761df1440e 100644 (file)
--- a/test/CodeGen/Thumb2/tail-call-r9.ll
+++ b/test/CodeGen/Thumb2/tail-call-r9.ll
@@ -6,7 +6,7 @@
 ; the destination address. It's callee-saved in AAPCS.
 define arm_aapcscc void @test(i32 %a) nounwind {
 ; CHECK-LABEL: test:
-; CHECK-NOT bx r9
+; CHECK-NOT: bx r9
   %tmp = load void ()** @foo, align 4
   tail call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r12}"() nounwind
   tail call arm_aapcscc void %tmp() nounwind

diff --git a/test/CodeGen/X86/avx512-cvt.ll b/test/CodeGen/X86/avx512-cvt.ll
index 89a69e7b982436455101089913b7cf0d2b933fb8..1d83485adecab3e6fe52b811fd43dd9c1d369434 100644 (file)
--- a/test/CodeGen/X86/avx512-cvt.ll
+++ b/test/CodeGen/X86/avx512-cvt.ll
@@ -185,7 +185,7 @@ define <16 x float> @uitof32(<16 x i32> %a) nounwind {
 }
 
 ; CHECK-LABEL: @fptosi02
-; CHECK vcvttss2si {{.*}} encoding: [0x62
+; CHECK: vcvttss2si {{.*}} encoding: [0x62
 ; CHECK: ret
 define i32 @fptosi02(float %a) nounwind {
   %b = fptosi float %a to i32
@@ -193,7 +193,7 @@ define i32 @fptosi02(float %a) nounwind {
 }
 
 ; CHECK-LABEL: @fptoui02
-; CHECK vcvttss2usi {{.*}} encoding: [0x62
+; CHECK: vcvttss2usi {{.*}} encoding: [0x62
 ; CHECK: ret
 define i32 @fptoui02(float %a) nounwind {
   %b = fptoui float %a to i32
@@ -201,7 +201,7 @@ define i32 @fptoui02(float %a) nounwind {
 }
 
 ; CHECK-LABEL: @uitofp02
-; CHECK vcvtusi2ss
+; CHECK: vcvtusi2ss
 ; CHECK: ret
 define float @uitofp02(i32 %a) nounwind {
   %b = uitofp i32 %a to float
@@ -209,7 +209,7 @@ define float @uitofp02(i32 %a) nounwind {
 }
 
 ; CHECK-LABEL: @uitofp03
-; CHECK vcvtusi2sd
+; CHECK: vcvtusi2sd
 ; CHECK: ret
 define double @uitofp03(i32 %a) nounwind {
   %b = uitofp i32 %a to double

diff --git a/test/CodeGen/X86/avx512-trunc-ext.ll b/test/CodeGen/X86/avx512-trunc-ext.ll
index 9be981c71ce7bdf7331daaf9a3eede9fe5c3eb43..86822a6853bae1f03f659e65e3bcd6672183f710 100644 (file)
--- a/test/CodeGen/X86/avx512-trunc-ext.ll
+++ b/test/CodeGen/X86/avx512-trunc-ext.ll
@@ -18,7 +18,7 @@ define <8 x i16> @trunc_8x64_to_8x16(<8 x i64> %i) nounwind readnone {
 
 
 ; CHECK-LABEL: zext_16x8_to_16x32
-; CHECK; vpmovzxbd {{.*}}%zmm
+; CHECK: vpmovzxbd {{.*}}%zmm
 ; CHECK: ret
 define <16 x i32> @zext_16x8_to_16x32(<16 x i8> %i) nounwind readnone {
   %x = zext <16 x i8> %i to <16 x i32>
@@ -26,7 +26,7 @@ define <16 x i32> @zext_16x8_to_16x32(<16 x i8> %i) nounwind readnone {
 }
 
 ; CHECK-LABEL: sext_16x8_to_16x32
-; CHECK; vpmovsxbd {{.*}}%zmm
+; CHECK: vpmovsxbd {{.*}}%zmm
 ; CHECK: ret
 define <16 x i32> @sext_16x8_to_16x32(<16 x i8> %i) nounwind readnone {
   %x = sext <16 x i8> %i to <16 x i32>
@@ -35,7 +35,7 @@ define <16 x i32> @sext_16x8_to_16x32(<16 x i8> %i) nounwind readnone {
 
 
 ; CHECK-LABEL: zext_16x16_to_16x32
-; CHECK; vpmovzxwd {{.*}}%zmm
+; CHECK: vpmovzxwd {{.*}}%zmm
 ; CHECK: ret
 define <16 x i32> @zext_16x16_to_16x32(<16 x i16> %i) nounwind readnone {
   %x = zext <16 x i16> %i to <16 x i32>
@@ -43,7 +43,7 @@ define <16 x i32> @zext_16x16_to_16x32(<16 x i16> %i) nounwind readnone {
 }
 
 ; CHECK-LABEL: zext_8x16_to_8x64
-; CHECK; vpmovzxwq
+; CHECK: vpmovzxwq
 ; CHECK: ret
 define <8 x i64> @zext_8x16_to_8x64(<8 x i16> %i) nounwind readnone {
   %x = zext <8 x i16> %i to <8 x i64>
@@ -132,4 +132,4 @@ define <8 x i32> @sext_8i1_8i32(<8 x i32> %a1, <8 x i32> %a2) nounwind {
 define <16 x i16> @trunc_v16i32_to_v16i16(<16 x i32> %x) {
   %1 = trunc <16 x i32> %x to <16 x i16>
   ret <16 x i16> %1
-}
\ No newline at end of file
+}

diff --git a/test/CodeGen/X86/vec_round.ll b/test/CodeGen/X86/vec_round.ll
index baa2f58631d4b1540013c79ab01266b49f4a8507..9258f9ee522eb08bea70dc0d472b974706cf1444 100644 (file)
--- a/test/CodeGen/X86/vec_round.ll
+++ b/test/CodeGen/X86/vec_round.ll
@@ -5,7 +5,7 @@ target triple = "x86_64-unknown-linux-gnu"
 declare void @use(<2 x double>)
 
 ; CHECK-LABEL: @test
-; CHECK callq round
+; CHECK: callq round
 
 ; Function Attrs: nounwind uwtable
 define void @test() {

diff --git a/test/CodeGen/XCore/llvm-intrinsics.ll b/test/CodeGen/XCore/llvm-intrinsics.ll
index 5650f9d8bda78dd70a25c72acb246d8d9c07611d..be5fd78cd21665ccb15e50b99224c465b8386461 100644 (file)
--- a/test/CodeGen/XCore/llvm-intrinsics.ll
+++ b/test/CodeGen/XCore/llvm-intrinsics.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -march=xcore | FileCheck %s
+; RUN: llc < %s -march=xcore -disable-fp-elim | FileCheck %s -check-prefix=CHECKFP
 
 declare i8* @llvm.frameaddress(i32) nounwind readnone
 declare i8* @llvm.returnaddress(i32) nounwind
@@ -141,7 +142,7 @@ entry:
 ; CHECKFP: ldaw r10, sp[0]
 ; CHECKFP: stw r4, r10[7]
 ; CHECKFP: stw r5, r10[6]
-; CHECKFP: stw r6, r10[5]`
+; CHECKFP: stw r6, r10[5]
 ; CHECKFP: stw r7, r10[4]
 ; CHECKFP: stw r8, r10[3]
 ; CHECKFP: stw r9, r10[2]

diff --git a/test/Transforms/GVN/unreachable_block_infinite_loop.ll b/test/Transforms/GVN/unreachable_block_infinite_loop.ll
index fe335ced5c370ccf7c209d359aa1ceabc4410eb4..fca5a28b38dd63b09023038bdefc2a49e12d6d51 100644 (file)
--- a/test/Transforms/GVN/unreachable_block_infinite_loop.ll
+++ b/test/Transforms/GVN/unreachable_block_infinite_loop.ll
@@ -1,4 +1,4 @@
-; RUN: opt -memdep -gvn -disable-output
+; RUN: opt -memdep -gvn -disable-output < %s
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin10.0"

diff --git a/test/Transforms/IndVarSimplify/lftr-extend-const.ll b/test/Transforms/IndVarSimplify/lftr-extend-const.ll
index 2fac4a797e29d573dea746855742cf5e1ab90f33..4736f857bcceb6348ed9bd52b27c6084c10d12cb 100644 (file)
--- a/test/Transforms/IndVarSimplify/lftr-extend-const.ll
+++ b/test/Transforms/IndVarSimplify/lftr-extend-const.ll
@@ -1,6 +1,6 @@
 ;RUN: opt -S %s -indvars | FileCheck %s
 
-; CHECK-LABEL-LABEL: @foo(
+; CHECK-LABEL: @foo(
 ; CHECK-NOT: %lftr.wideiv = trunc i32 %indvars.iv.next to i16
 ; CHECK: %exitcond = icmp ne i32 %indvars.iv.next, 512
 define void @foo() #0 {
@@ -20,7 +20,7 @@ for.end:                                          ; preds = %for.body
 }
 
 ; Check that post-incrementing the backedge taken count does not overflow.
-; CHECK-LABEL-LABEL: @postinc(
+; CHECK-LABEL: @postinc(
 ; CHECK: icmp eq i32 %indvars.iv.next, 256
 define i32 @postinc() #0 {
 entry:

diff --git a/test/Transforms/InstCombine/vec_phi_extract.ll b/test/Transforms/InstCombine/vec_phi_extract.ll
index 73ec1f1bb04f3f4301a7c2ee7adbd8a72eb5b2da..b0f365ba79648d06dddd530fc8e691e528799ef6 100644 (file)
--- a/test/Transforms/InstCombine/vec_phi_extract.ll
+++ b/test/Transforms/InstCombine/vec_phi_extract.ll
@@ -36,7 +36,7 @@ for.cond:
   %input_1.addr.1 = phi <3 x i32> [ undef, %entry ], [ %dec43, %for.body ]
   br i1 undef, label %for.end, label %for.body
 
-; CHECK extractelement
+; CHECK: extractelement
 for.body:
   %dec43 = add <3 x i32> %input_1.addr.1, <i32 -1, i32 -1, i32 -1>
   %sub44 = sub <3 x i32> zeroinitializer, %dec43

diff --git a/test/Transforms/LICM/volatile-alias.ll b/test/Transforms/LICM/volatile-alias.ll
index 886d7f2f807462e870009c39583b863e727a13df..df7f0a931eb87ed366c6c7b229955d59950a4a9c 100644 (file)
--- a/test/Transforms/LICM/volatile-alias.ll
+++ b/test/Transforms/LICM/volatile-alias.ll
@@ -4,7 +4,7 @@
 ; out of the loop.
 ; CHECK: load i32* %p
 ; CHECK: for.body:
-; CHECK; load volatile i32* %q
+; CHECK: load volatile i32* %q
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 

diff --git a/test/Transforms/LoopStrengthReduce/lsr-expand-quadratic.ll b/test/Transforms/LoopStrengthReduce/lsr-expand-quadratic.ll
index 255cf41a817461bccaa6e54f170ec124b4912592..aa688d999e6048c9c6404407130cf7cb09ba8ef7 100644 (file)
--- a/test/Transforms/LoopStrengthReduce/lsr-expand-quadratic.ll
+++ b/test/Transforms/LoopStrengthReduce/lsr-expand-quadratic.ll
@@ -13,7 +13,7 @@ target triple = "x86_64-apple-macosx"
 ; CHECK: %lsr.iv = phi i32 [ %lsr.iv.next, %test2.loop ], [ -16777216, %entry ]
 ; CHECK: %lsr.iv.next = add nsw i32 %lsr.iv, 16777216
 ;
-; CHECK=LABEL: for.end:
+; CHECK-LABEL: for.end:
 ; CHECK: %sub.cond.us = sub nsw i32 %inc1115.us, %sub.us
 ; CHECK: %sext.us = mul i32 %lsr.iv.next, %sub.cond.us
 ; CHECK: %f = ashr i32 %sext.us, 24

diff --git a/test/Transforms/LoopVectorize/induction.ll b/test/Transforms/LoopVectorize/induction.ll
index 50c3b6b6e79b250c1aa6771618af8d61a7e423e2..ad2c663ce461bcb0d02e4c8c71b2cf72278c05a0 100644 (file)
--- a/test/Transforms/LoopVectorize/induction.ll
+++ b/test/Transforms/LoopVectorize/induction.ll
@@ -75,7 +75,7 @@ loopexit:
 ; PR17532
 
 ; CHECK-LABEL: i8_loop
-; CHECK; icmp eq i32 {{.*}}, 256
+; CHECK: icmp eq i32 {{.*}}, 256
 define i32 @i8_loop() nounwind readnone ssp uwtable {
   br label %1
 
@@ -92,7 +92,7 @@ define i32 @i8_loop() nounwind readnone ssp uwtable {
 }
 
 ; CHECK-LABEL: i16_loop
-; CHECK; icmp eq i32 {{.*}}, 65536
+; CHECK: icmp eq i32 {{.*}}, 65536
 
 define i32 @i16_loop() nounwind readnone ssp uwtable {
   br label %1

diff --git a/test/Transforms/SLPVectorizer/X86/phi.ll b/test/Transforms/SLPVectorizer/X86/phi.ll
index 964e0e4efee7ef7804ba61d0d2590b1217f56647..0c53b60f3df15c317806bebc59e1f84314c80084 100644 (file)
--- a/test/Transforms/SLPVectorizer/X86/phi.ll
+++ b/test/Transforms/SLPVectorizer/X86/phi.ll
@@ -221,7 +221,7 @@ entry:
 ; CHECK: load x86_fp80*
 ; CHECK: load x86_fp80*
 ; CHECK-NOT: insertelement <2 x x86_fp80>
-; CHECK_NOT: insertelement <2 x x86_fp80>
+; CHECK-NOT: insertelement <2 x x86_fp80>
   br i1 undef, label %then, label %end
 
 then: