/// Performs a bitwise complement operation on APInt.
inline APInt Not(const APInt &APIVal) { return ~APIVal; }
-} // namespace APIntOps
+} // End of APIntOps namespace
// See friend declaration above. This additional declaration is required in
// order to compile LLVM with IBM xlC compiler.
hash_code hash_value(const APInt &Arg);
-} // namespace llvm
+} // End of llvm namespace
#endif
template <typename T> struct isPodLike<ArrayRef<T> > {
static const bool value = true;
};
-} // namespace llvm
+}
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
namespace std {
/// Implement std::swap in terms of BitVector swap.
ValueT &getSecond() { return std::pair<KeyT, ValueT>::second; }
const ValueT &getSecond() const { return std::pair<KeyT, ValueT>::second; }
};
-} // namespace detail
+}
template <
typename KeyT, typename ValueT, typename KeyInfoT = DenseMapInfo<KeyT>,
DenseSetEmpty &getSecond() { return *this; }
const DenseSetEmpty &getSecond() const { return *this; }
};
-} // namespace detail
+}
/// DenseSet - This implements a dense probed hash-table based set.
template<typename ValueT, typename ValueInfoT = DenseMapInfo<ValueT> >
return make_range(idf_ext_begin(G, S), idf_ext_end(G, S));
}
-} // namespace llvm
+} // End llvm namespace
#endif
};
};
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
void uncompress();
};
-} // namespace llvm
+} // End llvm namespace
#endif
template<typename T, typename U>
void operator>(const Optional<T> &X, const Optional<U> &Y);
-} // namespace llvm
+} // end llvm namespace
#endif
RHS.template get<U>()));
}
};
-} // namespace llvm
+}
#endif
rpo_iterator end() { return Blocks.rend(); }
};
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
return scc_iterator<Inverse<T> >::end(G);
}
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
S1.erase(*SI);
}
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
// vim: sw=2 ai
#endif
return Result;
}
-} // namespace llvm
+} // End llvm namespace
namespace std {
/// Implement std::swap in terms of BitVector swap.
}
};
-} // namespace llvm
+}
namespace std {
/// Implement std::swap in terms of SmallPtrSet swap.
}
};
-} // namespace llvm
+}
#endif
return X.capacity_in_bytes();
}
-} // namespace llvm
+} // End llvm namespace
namespace std {
/// Implement std::swap in terms of SmallVector swap.
swap(llvm::SmallVector<T, N> &LHS, llvm::SmallVector<T, N> &RHS) {
LHS.swap(RHS);
}
-} // namespace std
+}
#endif
/// \brief Print statistics to the given output stream.
void PrintStatistics(raw_ostream &OS);
-} // namespace llvm
+} // End llvm namespace
#endif
return join_impl(Begin, End, Separator, tag());
}
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+}
#endif
// StringRefs can be treated like a POD type.
template <typename T> struct isPodLike;
template <> struct isPodLike<StringRef> { static const bool value = true; };
-} // namespace llvm
+}
#endif
return base::insert(std::make_pair(Key, '\0'));
}
};
-} // namespace llvm
+}
#endif // LLVM_ADT_STRINGSET_H
/// @}
};
-} // namespace llvm
+} // End llvm namespace
#endif
}
/// @}
-} // namespace llvm
+}
#endif
return Result;
}
-} // namespace llvm
+} // End llvm namespace
#endif
void resize(size_type newsize) { resize(newsize, NodeTy()); }
};
-} // namespace llvm
+} // End llvm namespace
namespace std {
// Ensure that swap uses the fast list swap...
/// @}
};
-} // namespace llvm
+} // End llvm namespace
#endif
T &operator*() const { return **this->I; }
};
-} // namespace llvm
+}
#endif
template <typename T> iterator_range<T> make_range(std::pair<T, T> p) {
return iterator_range<T>(std::move(p.first), std::move(p.second));
}
-} // namespace llvm
+}
#endif
/// IdentifiedObjects.
bool isIdentifiedFunctionLocal(const Value *V);
-} // namespace llvm
+} // End llvm namespace
#endif
return OS;
}
-} // namespace llvm
+} // End llvm namespace
#endif
};
-} // namespace llvm
+}
#endif
else
addBlockEdges(*this, Irr, OuterLoop);
}
-} // namespace bfi_detail
+}
/// \brief Shared implementation for block frequency analysis.
///
G.addEdge(Irr, BFI.getNode(*I), OuterLoop);
}
};
-} // namespace bfi_detail
+}
template <class BT>
void BlockFrequencyInfoImpl<BT>::computeIrreducibleMass(
LoopData *OuterLoop, std::list<LoopData>::iterator Insert) {
bool calcInvokeHeuristics(BasicBlock *BB);
};
-} // namespace llvm
+}
#endif
const DominatorTree *DT = nullptr,
const LoopInfo *LI = nullptr);
-} // namespace llvm
+} // End llvm namespace
#endif
return "";
}
};
-} // namespace llvm
+} // End llvm namespace
namespace llvm {
class FunctionPass;
createCGSCCToFunctionPassAdaptor(FunctionPassT Pass) {
return CGSCCToFunctionPassAdaptor<FunctionPassT>(std::move(Pass));
}
-} // namespace llvm
+}
#endif
static const CallGraphNode &CGdereference(PairTy P) { return *P.second; }
};
-} // namespace llvm
+} // End llvm namespace
#endif
iterator end() const { return Nodes.end(); }
};
-} // namespace llvm
+} // End llvm namespace
#endif
SmallPtrSetImpl<const Value *> &EphValues);
};
-} // namespace llvm
+}
#endif
/// with the specified arguments, returning null if unsuccessful.
Constant *ConstantFoldCall(Function *F, ArrayRef<Constant *> Operands,
const TargetLibraryInfo *TLI = nullptr);
-} // namespace llvm
+}
#endif
FunctionPass *createPostDomOnlyPrinterPass();
FunctionPass *createPostDomViewerPass();
FunctionPass *createPostDomOnlyViewerPass();
-} // namespace llvm
+} // End llvm namespace
#endif
EXTERN_TEMPLATE_INSTANTIATION(class DominanceFrontierBase<BasicBlock>);
EXTERN_TEMPLATE_INSTANTIATION(class ForwardDominanceFrontierBase<BasicBlock>);
-} // namespace llvm
+} // End llvm namespace
#endif
return *Result;
}
-} // namespace llvm
+} // End llvm namespace
#endif
Pass *createIVUsersPass();
-} // namespace llvm
+}
#endif
/// Do not inline functions which allocate this many bytes on the stack
/// when the caller is recursive.
const unsigned TotalAllocaSizeRecursiveCaller = 1024;
-} // namespace InlineConstants
+}
/// \brief Represents the cost of inlining a function.
///
bool isInlineViable(Function &Callee);
};
-} // namespace llvm
+}
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
return interval_part_interval_iterator();
}
-} // namespace llvm
+} // End llvm namespace
#endif
void updatePredecessors(Interval *Int);
};
-} // namespace llvm
+} // End llvm namespace
#endif
const SmallPtrSetImpl<BasicBlock *> *DefBlocks;
SmallVector<BasicBlock *, 32> PHIBlocks;
};
-} // namespace llvm
+}
#endif
/// bound specifies the maximum number of bytes needed to represent an
/// unconditional jump or a trap instruction in the back end currently in use.
ModulePass *createJumpInstrTableInfoPass(unsigned Bound);
-} // namespace llvm
+}
#endif /* LLVM_ANALYSIS_JUMPINSTRTABLEINFO_H */
static StringRef name() { return "LazyCallGraphPrinterPass"; }
};
-} // namespace llvm
+}
#endif
ImmutableCallSite CS,
const MemoryLocation &Loc);
};
-} // namespace llvm
+} // End of llvm namespace
#endif
const Function &F ///< The function to be checked
);
-} // namespace llvm
+} // End llvm namespace
#endif
AliasAnalysis *AA = nullptr,
AAMDNodes *AATags = nullptr);
-} // namespace llvm
+}
#endif
DominatorTree *DT;
LoopInfo *LI;
};
-} // namespace llvm
+} // End llvm namespace
#endif
void getAnalysisUsage(AnalysisUsage &AU) const override;
};
-} // namespace llvm
+} // End llvm namespace
#endif
#endif
}
-} // namespace llvm
+} // End llvm namespace
#endif
Loop *CurrentLoop;
};
-} // namespace llvm
+} // End llvm namespace
#endif
SizeOffsetEvalType visitInstruction(Instruction &I);
};
-} // namespace llvm
+} // End llvm namespace
#endif
};
-} // namespace llvm
+} // End llvm namespace
#endif
return LHS == RHS;
}
};
-} // namespace llvm
+}
#endif
//
FunctionPass *createMemDerefPrinter();
-} // namespace llvm
+}
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+}
#endif
EXTERN_TEMPLATE_INSTANTIATION(class RegionNodeBase<RegionTraits<Function>>);
EXTERN_TEMPLATE_INSTANTIATION(class RegionInfoBase<RegionTraits<Function>>);
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
/// to locate them all and call their destructors.
SCEVUnknown *FirstUnknown;
};
-} // namespace llvm
+}
#endif
Value *expandIVInc(PHINode *PN, Value *StepV, const Loop *L,
Type *ExpandTy, Type *IntTy, bool useSubtract);
};
-} // namespace llvm
+}
#endif
return SCEVApplyRewriter::rewrite(Scev, Map, SE);
}
-} // namespace llvm
+}
#endif
ScalarEvolution &SE,
DominatorTree &DT);
-} // namespace llvm
+}
#endif
}
};
-} // namespace llvm
+}
#endif
/// clients.
ImmutablePass *createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA);
-} // namespace llvm
+} // End llvm namespace
#endif
U->getNumOperands() == 1 ? U->getOperand(0)->getType() : nullptr);
}
};
-} // namespace llvm
+}
#endif
/// @return true on error.
bool parseAssemblyInto(MemoryBufferRef F, Module &M, SMDiagnostic &Err);
-} // namespace llvm
+} // End llvm namespace
#endif
// [id, name]
};
-} // namespace bitc
+} // End bitc namespace
/// BitCodeAbbrevOp - This describes one or more operands in an abbreviation.
/// This is actually a union of two different things:
OperandList.push_back(OpInfo);
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
static StringRef name() { return "BitcodeWriterPass"; }
};
-} // namespace llvm
+}
#endif
bool ReadBlockInfoBlock();
};
-} // namespace llvm
+} // End llvm namespace
#endif
};
-} // namespace llvm
+} // End llvm namespace
#endif
COMDAT_SELECTION_KIND_SAME_SIZE = 5,
};
-} // namespace bitc
-} // namespace llvm
+} // End bitc namespace
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
namespace std {
template <> struct is_error_code_enum<llvm::BitcodeError> : std::true_type {};
// or we are in LTO.
bool canBeOmittedFromSymbolTable(const GlobalValue *GV);
-} // namespace llvm
+} // End llvm namespace
#endif
void EmitXXStructorList(const Constant *List, bool isCtor);
GCMetadataPrinter *GetOrCreateGCPrinter(GCStrategy &C);
};
-} // namespace llvm
+}
#endif
}
};
-} // namespace llvm
+}
#endif
const MachineBlockFrequencyInfo &MBFI,
VirtRegAuxInfo::NormalizingFn norm =
normalizeSpillWeight);
-} // namespace llvm
+}
#endif // LLVM_CODEGEN_CALCSPILLWEIGHTS_H
}
};
-} // namespace llvm
+}
#endif
#endif
};
-} // namespace llvm
+} // end llvm namespace
#endif
void emitFunctionInfo(const MCSymbol *FnLabel, const FunctionFaultInfos &FFI);
};
-} // namespace llvm
+}
#endif
/// will soon change.
GCFunctionInfo &getFunctionInfo(const Function &F);
};
-} // namespace llvm
+}
#endif
virtual ~GCMetadataPrinter();
};
-} // namespace llvm
+}
#endif
/// register your GCMetadataPrinter subclass with the
/// GCMetadataPrinterRegistery as well.
typedef Registry<GCStrategy> GCRegistry;
-} // namespace llvm
+}
#endif
void linkShadowStackGC();
void linkStatepointExampleGC();
-} // namespace llvm
+}
#endif
CVT_INVALID /// Marker - Invalid opcode
};
-} // namespace ISD
+} // end llvm::ISD namespace
-} // namespace llvm
+} // end llvm namespace
#endif
/// simple integer bswap.
static bool LowerToByteSwap(CallInst *CI);
};
-} // namespace llvm
+}
#endif
void AdjustPriorityOfUnscheduledPreds(SUnit *SU);
SUnit *getSingleUnscheduledPred(SUnit *SU);
};
-} // namespace llvm
+}
#endif
LexicalScope *CurrentFnLexicalScope;
};
-} // namespace llvm
+} // end llvm namespace
#endif
};
-} // namespace llvm
+}
#endif
class HMEditor;
};
-} // namespace llvm
+} // End llvm namespace
#endif
const MachineBlockFrequencyInfo&);
};
-} // namespace llvm
+}
#endif
/// print - Implement the dump method.
void print(raw_ostream &O, const Module* = nullptr) const override;
};
-} // namespace llvm
+}
#endif /* LLVM_CODEGEN_LIVESTACK_ANALYSIS_H */
void setPHIJoin(unsigned Reg) { PHIJoins.set(Reg); }
};
-} // namespace llvm
+} // End llvm namespace
#endif
MachineBasicBlock::iterator getInitial() { return I; }
};
-} // namespace llvm
+} // End llvm namespace
#endif
};
-} // namespace llvm
+}
#endif
const MachineBasicBlock *Dst) const;
};
-} // namespace llvm
+}
#endif
void dump() const;
};
-} // namespace llvm
+} // End llvm namespace
#endif
void getAnalysisUsage(AnalysisUsage &AU) const override;
};
-} // namespace llvm
+}
#endif
}
};
-} // namespace llvm
+}
#endif
void dump(const MachineFunction &MF) const;
};
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
void getAnalysisUsage(AnalysisUsage &AU) const override;
};
-} // namespace llvm
+} // End llvm namespace
#endif
bool runOnFunction(Function &F) override;
};
-} // namespace llvm
+} // End llvm namespace
#endif
return OS;
}
-} // namespace llvm
+} // End llvm namespace
#endif
ImplicitDefine = Implicit | Define,
ImplicitKill = Implicit | Kill
};
-} // namespace RegState
+}
class MachineInstrBuilder {
MachineFunction *MF;
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
const MachineOperand *operator->() const { return &deref(); }
};
-} // namespace llvm
+} // End llvm namespace
#endif
void dump() const;
};
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
raw_ostream &operator<<(raw_ostream &OS, const MachineMemOperand &MRO);
-} // namespace llvm
+} // End llvm namespace
#endif
}; // End class MachineModuleInfo
-} // namespace llvm
+} // End llvm namespace
#endif
// See friend declaration above. This additional declaration is required in
// order to compile LLVM with IBM xlC compiler.
hash_code hash_value(const MachineOperand &MO);
-} // namespace llvm
+} // End llvm namespace
#endif
EXTERN_TEMPLATE_INSTANTIATION(class RegionNodeBase<RegionTraits<MachineFunction>>);
EXTERN_TEMPLATE_INSTANTIATION(class RegionInfoBase<RegionTraits<MachineFunction>>);
-} // namespace llvm
+}
#endif
return PSetIterator(RegUnit, this);
}
-} // namespace llvm
+} // End llvm namespace
#endif
MachineSSAUpdater(const MachineSSAUpdater&) = delete;
};
-} // namespace llvm
+} // End llvm namespace
#endif
/// @}
};
-} // namespace llvm
+} // End llvm namespace
#endif
void anchor() override;
};
-} // namespace llvm
+}
#endif /* LLVM_CODEGEN_PBQPRACONSTRAINT_H */
/// createForwardControlFlowIntegrityPass - This pass adds control-flow
/// integrity.
ModulePass *createForwardControlFlowIntegrityPass();
-} // namespace llvm
+} // End llvm namespace
/// Target machine pass initializer for passes with dependencies. Use with
/// INITIALIZE_TM_PASS_END.
int getFrameIndex() const { return FI; }
};
-} // namespace llvm
+} // End llvm namespace
#endif
};
-} // namespace llvm
+} // End llvm namespace
#endif
unsigned numberRCValPredInSU (SUnit *SU, unsigned RCId);
unsigned numberRCValSuccInSU (SUnit *SU, unsigned RCId);
};
-} // namespace llvm
+}
#endif
/// Return the SYNC_FETCH_AND_* value for the given opcode and type, or
/// UNKNOWN_LIBCALL if there is none.
Libcall getATOMIC(unsigned Opc, MVT VT);
-} // namespace RTLIB
-} // namespace llvm
+}
+}
#endif
reverse_iterator rend() { return Index2Node.rend(); }
const_reverse_iterator rend() const { return Index2Node.rend(); }
};
-} // namespace llvm
+}
#endif
}
};
-} // namespace llvm
+}
#endif
void RecedeCycle() override;
};
-} // namespace llvm
+}
#endif //!LLVM_CODEGEN_SCOREBOARDHAZARDRECOGNIZER_H
};
-} // namespace llvm
+}
#endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */
/// Return true if the node has at least one operand
/// and all operands of the specified node are ISD::UNDEF.
bool allOperandsUndef(const SDNode *N);
-} // namespace ISD
+} // end llvm:ISD namespace
//===----------------------------------------------------------------------===//
/// Unlike LLVM values, Selection DAG nodes may return multiple
return isa<StoreSDNode>(N) &&
cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
}
-} // namespace ISD
+}
-} // namespace llvm
+} // end llvm namespace
#endif
struct IntervalMapInfo<SlotIndex> : IntervalMapHalfOpenInfo<SlotIndex> {
};
-} // namespace llvm
+}
#endif // LLVM_CODEGEN_SLOTINDEXES_H
void debug() { print(dbgs()); }
};
-} // namespace llvm
+}
#endif
unsigned getExtendedSizeInBits() const;
};
-} // namespace llvm
+} // End llvm namespace
#endif
VRM.print(OS);
return OS;
}
-} // namespace llvm
+} // End llvm namespace
#endif
void calculateWinCXXEHStateNumbers(const Function *ParentFn,
WinEHFuncInfo &FuncInfo);
-} // namespace llvm
+}
#endif // LLVM_CODEGEN_WINEHFUNCINFO_H
virtual std::unique_ptr<LoadedObjectInfo> clone() const = 0;
};
-} // namespace llvm
+}
#endif
AttributeSpecVector AttributeSpecs;
};
-} // namespace llvm
+}
#endif
void dump(raw_ostream &OS) const;
};
-} // namespace llvm
+}
#endif
~DWARFCompileUnit() override;
};
-} // namespace llvm
+}
#endif
}
};
-} // namespace llvm
+}
#endif
void clear();
};
-} // namespace llvm
+}
#endif
}
};
-} // namespace llvm
+}
#endif
DenseSet<uint32_t> ParsedCUOffsets;
};
-} // namespace llvm
+}
#endif
const DWARFUnit *U;
};
-} // namespace llvm
+}
#endif
LineTableMapTy LineTableMap;
};
-} // namespace llvm
+}
#endif
void parse(DataExtractor data);
void dump(raw_ostream &OS) const;
};
-} // namespace llvm
+}
#endif
void dumpString(raw_ostream &OS, const DWARFUnit *U) const;
};
-} // namespace llvm
+}
#endif
bool extractImpl(DataExtractor debug_info, uint32_t *offset_ptr) override;
};
-} // namespace llvm
+}
#endif
const DWARFDebugInfoEntryMinimal *getSubprogramForAddress(uint64_t Address);
};
-} // namespace llvm
+}
#endif
std::unique_ptr<IPDBEnumSymbols> Enumerator;
};
-} // namespace llvm
+}
#endif
virtual void reset() = 0;
virtual IPDBDataStream *clone() const = 0;
};
-} // namespace llvm
+}
#endif
virtual void reset() = 0;
virtual MyType *clone() const = 0;
};
-} // namespace llvm
+}
#endif
virtual uint32_t getCompilandId() const = 0;
virtual bool isStatement() const = 0;
};
-} // namespace llvm
+}
#endif
virtual std::unique_ptr<IPDBEnumDataStreams> getDebugStreams() const = 0;
};
-} // namespace llvm
+}
#endif
virtual PDB_Checksum getChecksumType() const = 0;
virtual std::unique_ptr<IPDBEnumSymbols> getCompilands() const = 0;
};
-} // namespace llvm
+}
#endif
std::string getFunctionName(uint64_t Address, DINameKind NameKind) const;
std::unique_ptr<IPDBSession> Session;
};
-} // namespace llvm
+}
#endif
raw_ostream &operator<<(raw_ostream &OS, const Variant &Value);
raw_ostream &operator<<(raw_ostream &OS, const VersionInfo &Version);
raw_ostream &operator<<(raw_ostream &OS, const TagStats &Stats);
-} // namespace llvm
+}
#endif
private:
bool RequireImpl;
};
-} // namespace llvm
+}
#endif
// FORWARD_SYMBOL_METHOD(getValue)
FORWARD_SYMBOL_METHOD(getVirtualAddress)
};
-} // namespace llvm
+}
#endif // LLVM_DEBUGINFO_PDB_PDBSYMBOLANNOTATION_H
FORWARD_SYMBOL_METHOD(getSymIndexId)
FORWARD_SYMBOL_METHOD(getVirtualAddress)
};
-} // namespace llvm
+}
#endif // LLVM_DEBUGINFO_PDB_PDBSYMBOLBLOCK_H
FORWARD_SYMBOL_METHOD(getSourceFileName)
FORWARD_SYMBOL_METHOD(getSymIndexId)
};
-} // namespace llvm
+}
#endif // LLVM_DEBUGINFO_PDB_PDBSYMBOLCOMPILAND_H
// Create wrappers for C Binding types (see CBindingWrapping.h).
DEFINE_SIMPLE_CONVERSION_FUNCTIONS(ExecutionEngine, LLVMExecutionEngineRef)
-} // namespace llvm
+} // End llvm namespace
#endif
inline GenericValue PTOGV(void *P) { return GenericValue(P); }
inline void* GVTOP(const GenericValue &GV) { return GV.PointerVal; }
-} // namespace llvm
+} // End llvm namespace.
#endif
LLVMLinkInMCJIT();
}
} ForceMCJITLinking;
-} // namespace
+}
#endif
virtual std::unique_ptr<MemoryBuffer> getObject(const Module* M) = 0;
};
-} // namespace llvm
+}
#endif
MemoryGroup RODataMem;
};
-} // namespace llvm
+}
#endif // LLVM_EXECUTION_ENGINE_SECTION_MEMORY_MANAGER_H
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
virtual void printInfoComment(const Value &, formatted_raw_ostream &) {}
};
-} // namespace llvm
+} // End llvm namespace
#endif
} // end AttributeFuncs namespace
-} // namespace llvm
+} // end llvm namespace
#endif
/// Upgrade a metadata string constant in place.
void UpgradeMDStringConstant(std::string &String);
-} // namespace llvm
+} // End llvm namespace
#endif
// Create wrappers for C Binding types (see CBindingWrapping.h).
DEFINE_SIMPLE_CONVERSION_FUNCTIONS(BasicBlock, LLVMBasicBlockRef)
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
ImmutableCallSite(CallSite CS) : CallSiteBase(CS.getInstruction()) {}
};
-} // namespace llvm
+} // End llvm namespace
#endif
/// in SSE registers.
X86_VectorCall = 80
};
-} // namespace CallingConv
+} // End CallingConv namespace
-} // namespace llvm
+} // End llvm namespace
#endif
return OS;
}
-} // namespace llvm
+} // end llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+}
#endif
return OS;
}
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
}
}
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
void print(raw_ostream &OS, const Module *M = nullptr) const override;
};
-} // namespace llvm
+} // End llvm namespace
#endif
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(Function, Value)
-} // namespace llvm
+} // End llvm namespace
#endif
virtual std::vector<StructType *> getIdentifiedStructTypes() const = 0;
};
-} // namespace llvm
+} // End llvm namespace
#endif
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(GlobalAlias, Constant)
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(GlobalVariable, Value)
-} // namespace llvm
+} // End llvm namespace
#endif
// Create wrappers for C Binding types (see CBindingWrapping.h).
DEFINE_SIMPLE_CONVERSION_FUNCTIONS(IRBuilder<>, LLVMBuilderRef)
-} // namespace llvm
+}
#endif
static StringRef name() { return "PrintFunctionPass"; }
};
-} // namespace llvm
+} // End llvm namespace
#endif
};
-} // namespace llvm
+} // End llvm namespace
#endif
return iterator_range<const_inst_iterator>(inst_begin(F), inst_end(F));
}
-} // namespace llvm
+} // End llvm namespace
#endif
#undef DELEGATE
-} // namespace llvm
+} // End llvm namespace
#endif
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(CmpInst, Value)
-} // namespace llvm
+} // End llvm namespace
#endif
enum { NumLowBitsAvailable = 2 };
};
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
return cast<ConstantInt>(const_cast<Value *>(getArgOperand(3)));
}
};
-} // namespace llvm
+}
#endif
/// of IITDescriptors.
void getIntrinsicInfoTableEntries(ID id, SmallVectorImpl<IITDescriptor> &T);
-} // namespace Intrinsic
+} // End Intrinsic namespace
-} // namespace llvm
+} // End llvm namespace
#endif
return reinterpret_cast<LLVMContextRef*>(const_cast<LLVMContext**>(Tys));
}
-} // namespace llvm
+}
#endif
Module *M;
};
-} // namespace legacy
+} // End legacy namespace
// Create wrappers for C Binding types (see CBindingWrapping.h).
DEFINE_STDCXX_CONVERSION_FUNCTIONS(legacy::PassManagerBase, LLVMPassManagerRef)
-} // namespace llvm
+} // End llvm namespace
#endif
Timer *getPassTimer(Pass *);
-} // namespace llvm
+}
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
ManglerPrefixTy PrefixTy = Mangler::Default) const;
};
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // end llvm namespace
#endif
return reinterpret_cast<Module*>(MP);
}
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+}
#endif
}
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
static StringRef name() { return "InvalidateAllAnalysesPass"; }
};
-} // namespace llvm
+}
#endif
};
} // End namespace detail
-} // namespace llvm
+}
#endif
}
return Result;
}
-} // namespace llvm
+}
#endif
static ValueSymbolTable *toPtr(ValueSymbolTable &R) { return &R; }
};
-} // namespace llvm
+} // End llvm namespace
#endif
return reinterpret_cast<LLVMTypeRef*>(const_cast<Type**>(Tys));
}
-} // namespace llvm
+} // End llvm namespace
#endif
void incorporateMDNode(const MDNode *V);
};
-} // namespace llvm
+} // end llvm namespace
#endif
// Create wrappers for C Binding types (see CBindingWrapping.h).
DEFINE_SIMPLE_CONVERSION_FUNCTIONS(Use, LLVMUseRef)
-} // namespace llvm
+}
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
return reinterpret_cast<LLVMValueRef*>(const_cast<Value**>(Vals));
}
-} // namespace llvm
+} // End llvm namespace
#endif
virtual void allUsesReplacedWith(Value *) {}
};
-} // namespace llvm
+} // End llvm namespace
#endif
/// @}
};
-} // namespace llvm
+} // End llvm namespace
#endif
static StringRef name() { return "VerifierPass"; }
};
-} // namespace llvm
+} // End llvm namespace
#endif
/// for it.
std::unique_ptr<Module> parseIRFile(StringRef Filename, SMDiagnostic &Err,
LLVMContext &Context);
-} // namespace llvm
+}
#endif
void initializeDwarfEHPreparePass(PassRegistry&);
void initializeFloat2IntPass(PassRegistry&);
void initializeLoopDistributePass(PassRegistry&);
-} // namespace llvm
+}
#endif
bool ShouldInternalize = true;
bool ShouldEmbedUselists = false;
};
-} // namespace llvm
+}
#endif
static LTOModule *makeLTOModule(MemoryBufferRef Buffer, TargetOptions options,
std::string &errMsg, LLVMContext *Context);
};
-} // namespace llvm
+}
#endif
std::unique_ptr<const CompleterConcept> Completer;
};
-} // namespace llvm
+}
#endif
DiagnosticHandlerFunction DiagnosticHandler;
};
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
X86, /// Windows x86, uses no CFI, just EH tables
MIPS = Alpha,
};
-} // namespace WinEH
+}
enum class ExceptionHandling {
None, /// No exception support
bool shouldUseLogicalShr() const { return UseLogicalShr; }
};
-} // namespace llvm
+}
#endif
protected:
explicit MCAsmInfoGNUCOFF();
};
-} // namespace llvm
+}
#endif // LLVM_MC_MCASMINFOCOFF_H
const MCSubtargetInfo &STI) const = 0;
};
-} // namespace llvm
+} // End llvm namespace
#endif
MCObjectWriter *createELFObjectWriter(MCELFObjectTargetWriter *MOTW,
raw_pwrite_stream &OS,
bool IsLittleEndian);
-} // namespace llvm
+} // End llvm namespace
#endif
uint64_t Address) override;
};
-} // namespace llvm
+}
#endif
OPC_Fail // OPC_Fail()
};
-} // namespace MCD
+} // namespace MCDecode
} // namespace llvm
#endif
SMLoc getLoc() const { return Loc; }
};
-} // namespace llvm
+} // End llvm namespace
#endif
unsigned Flags;
};
-} // namespace llvm
+} // End llvm namespace
#endif
uint64_t &Target) const;
};
-} // namespace llvm
+} // End llvm namespace
#endif
OPERAND_PCREL = 4,
OPERAND_FIRST_TARGET = 5
};
-} // namespace MCOI
+}
/// \brief This holds information about one operand of a machine instruction,
/// indicating the register class for register operands, etc.
InsertSubreg,
Convergent
};
-} // namespace MCID
+}
/// \brief Describe properties that are true of each instruction in the target
/// description file. This captures information about side effects, register
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
raw_pwrite_stream &OS,
bool IsLittleEndian);
-} // namespace llvm
+} // End llvm namespace
#endif
/// @}
};
-} // namespace llvm
+} // End llvm namespace
#endif
void setAllowAtInIdentifier(bool v) { AllowAtInIdentifier = v; }
};
-} // namespace llvm
+} // End llvm namespace
#endif
MCAsmParser *createMCAsmParser(SourceMgr &, MCContext &, MCStreamer &,
const MCAsmInfo &);
-} // namespace llvm
+} // End llvm namespace
#endif
/// @}
};
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
unsigned VariantKind);
};
-} // namespace llvm
+}
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
static bool classof(const MCSymbol *S) { return S->isCOFF(); }
};
-} // namespace llvm
+}
#endif
private:
void setIsBindingSet() const;
};
-} // namespace llvm
+}
#endif
static bool classof(const MCSymbol *S) { return S->isMachO(); }
};
-} // namespace llvm
+}
#endif
uint64_t Address) = 0;
};
-} // namespace llvm
+}
#endif
virtual void onLabelParsed(MCSymbol *Symbol) { };
};
-} // namespace llvm
+} // End llvm namespace
#endif
void Emit(MCStreamer &Streamer) const override;
void EmitUnwindInfo(MCStreamer &Streamer, WinEH::FrameInfo *FI) const override;
};
-} // namespace Win64EH
+}
} // end namespace llvm
#endif
/// \returns The constructed object writer.
MCObjectWriter *createWinCOFFObjectWriter(MCWinCOFFObjectTargetWriter *MOTW,
raw_pwrite_stream &OS);
-} // namespace llvm
+} // End llvm namespace
#endif
private:
LLVM_ATTRIBUTE_NORETURN void FatalError(const Twine &Msg) const;
};
-} // namespace llvm
+}
#endif
virtual void Emit(MCStreamer &Streamer) const = 0;
virtual void EmitUnwindInfo(MCStreamer &Streamer, FrameInfo *FI) const = 0;
};
-} // namespace WinEH
-} // namespace llvm
+}
+}
#endif
return !(LHS == RHS);
}
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // end llvm namespace
#endif
static StringRef input(StringRef, void *, BinaryRef &);
static bool mustQuote(StringRef S) { return needsQuotes(S); }
};
-} // namespace yaml
-} // namespace llvm
+}
+}
#endif
unsigned IsThin : 1;
};
-} // namespace object
-} // namespace llvm
+}
+}
#endif
writeArchive(StringRef ArcName, std::vector<NewArchiveIterator> &NewMembers,
bool WriteSymtab);
-} // namespace llvm
+}
#endif
}
ErrorOr<OwningBinary<Binary>> createBinary(StringRef Path);
-} // namespace object
-} // namespace llvm
+}
+}
#endif
uint16_t Ret = static_cast<uint16_t>(a) | static_cast<uint16_t>(b);
return static_cast<DLLCharacteristics>(Ret);
}
-} // namespace COFF
+}
// The structure of the yaml files is not an exact 1:1 match to COFF. In order
// to use yaml::IO, we use these structures which are closer to the source.
std::vector<Symbol> Symbols;
Object();
};
-} // namespace COFFYAML
-} // namespace llvm
+}
+}
LLVM_YAML_IS_SEQUENCE_VECTOR(COFFYAML::Section)
LLVM_YAML_IS_SEQUENCE_VECTOR(COFFYAML::Symbol)
return cast<ELFObjectFileBase>(Obj)->getELFDynamicSymbolIterators();
}
-} // namespace object
-} // namespace llvm
+}
+}
#endif
static ErrorOr<std::unique_ptr<IRObjectFile>> create(MemoryBufferRef Object,
LLVMContext &Context);
};
-} // namespace object
-} // namespace llvm
+}
+}
#endif
return OwningObject;
}
-} // namespace object
-} // namespace llvm
+}
+}
#endif
getObjectForArch(StringRef ArchName) const;
};
-} // namespace object
-} // namespace llvm
+}
+}
#endif
}
};
-} // namespace object
-} // namespace llvm
+}
+}
#endif
return OwningObject;
}
-} // namespace object
-} // namespace llvm
+}
+}
#endif
bool operator==(OptSpecifier Opt) const { return ID == Opt.getID(); }
bool operator!=(OptSpecifier Opt) const { return !(*this == Opt); }
};
-} // namespace opt
-} // namespace llvm
+}
+}
#endif
/// @brief This is the storage for the -time-passes option.
extern bool TimePassesIsEnabled;
-} // namespace llvm
+} // End llvm namespace
// Include support files that contain important APIs commonly used by Passes,
// but that we want to separate out to make it easier to read the header files.
return *(AnalysisType*)ResultPass->getAdjustedAnalysisPointer(PI);
}
-} // namespace llvm
+} // End llvm namespace
#endif
PassInfo(const PassInfo &) = delete;
};
-} // namespace llvm
+}
#endif
// Create wrappers for C Binding types (see CBindingWrapping.h).
DEFINE_STDCXX_CONVERSION_FUNCTIONS(PassRegistry, LLVMPassRegistryRef)
-} // namespace llvm
+}
#endif
};
-} // namespace llvm
+} // End llvm namespace
#endif
bool VerifyEachPass, bool DebugLogging);
};
-} // namespace llvm
+}
#endif
NUM_PERSONALITY_INDEX
};
-} // namespace EHABI
-} // namespace ARM
-} // namespace llvm
+}
+}
+}
#endif
inline size_t HeaderWords(const ExceptionDataRecord &XR) {
return (XR.Data[0] & 0xff800000) ? 1 : 2;
}
-} // namespace WinEH
-} // namespace ARM
-} // namespace llvm
+}
+}
+}
#endif
}
};
-} // namespace llvm
+} // end llvm namespace
#endif
cas_flag AtomicAdd(volatile cas_flag* ptr, cas_flag val);
cas_flag AtomicMul(volatile cas_flag* ptr, cas_flag val);
cas_flag AtomicDiv(volatile cas_flag* ptr, cas_flag val);
- } // namespace sys
-} // namespace llvm
+ }
+}
#endif
}
};
-} // namespace llvm
+}
#endif
return Prob.print(OS);
}
-} // namespace llvm
+}
#endif
InitializeCOMRAII(const InitializeCOMRAII &) = delete;
void operator=(const InitializeCOMRAII &) = delete;
};
-} // namespace sys
-} // namespace llvm
+}
+}
#endif
return (Val && isa<X>(Val)) ? cast<X>(Val) : nullptr;
}
-} // namespace llvm
+} // End llvm namespace
#endif
}
llvm_unreachable("Bad CodeModel!");
}
-} // namespace llvm
+} // end llvm namespace
#endif
cleanup = 0;
}
};
-} // namespace llvm
+}
#endif
DOTGraphTraits (bool simple=false) : DefaultDOTGraphTraits (simple) {}
};
-} // namespace llvm
+} // End llvm namespace
#endif
std::unique_ptr<DataStreamer> getDataFileStreamer(const std::string &Filename,
std::string *Err);
-} // namespace llvm
+}
#endif // LLVM_SUPPORT_DATASTREAM_H_
//
#define DEBUG(X) DEBUG_WITH_TYPE(DEBUG_TYPE, X)
-} // namespace llvm
+} // End llvm namespace
#endif
static void AddSymbol(StringRef symbolName, void *symbolValue);
};
-} // namespace sys
-} // namespace llvm
+} // End sys namespace
+} // End llvm namespace
#endif
inline std::error_code make_error_code(errc E) {
return std::error_code(static_cast<int>(E), std::generic_category());
}
-} // namespace llvm
+}
namespace std {
template <> struct is_error_code_enum<llvm::errc> : std::true_type {};
LLVM_ATTRIBUTE_NORETURN void
llvm_unreachable_internal(const char *msg=nullptr, const char *file=nullptr,
unsigned line=0);
-} // namespace llvm
+}
/// Marks that the current location is not supposed to be reachable.
/// In !NDEBUG builds, prints the message and location info to stderr.
intptr_t IterationHandle;
directory_entry CurrentEntry;
};
-} // namespace detail
+}
/// directory_iterator - Iterates through the entries in path. There is no
/// operator++ because we need an error_code. If it's really needed we can make
uint16_t Level;
bool HasNoPushRequest;
};
-} // namespace detail
+}
/// recursive_directory_iterator - Same as directory_iterator except for it
/// recurses down into child directories.
/// will not be removed when the object is destroyed.
void releaseFile() { DeleteIt = false; }
};
-} // namespace llvm
+} // End llvm namespace
#endif
/// debug output. Use it like: fdbgs() << "foo" << "bar";
formatted_raw_ostream &fdbgs();
-} // namespace llvm
+} // end llvm namespace
#endif
FileCoverageList FileCoverages;
FuncCoverageMap FuncCoverages;
};
-} // namespace llvm
+}
#endif
getNode(const_cast<NodeT *>(B)));
}
-} // namespace llvm
+}
#endif
DT.updateDFSNumbers();
}
-} // namespace llvm
+}
#endif
DisplayGraph(Filename, true, Program);
}
-} // namespace llvm
+} // End llvm namespace
#endif
///
/// \return - True on success.
bool getHostCPUFeatures(StringMap<bool> &Features);
-} // namespace sys
-} // namespace llvm
+}
+}
#endif
/// \brief Advance the iterator to the next line.
void advance();
};
-} // namespace llvm
+}
#endif
const uint8_t *body(ArrayRef<uint8_t> Data);
};
-} // namespace llvm
+}
#endif
~llvm_shutdown_obj() { llvm_shutdown(); }
};
-} // namespace llvm
+}
#endif
}
extern const float huge_valf;
-} // namespace llvm
+} // End llvm namespace
#endif
/// as writable.
static bool setRangeWritable(const void *Addr, size_t Size);
};
-} // namespace sys
-} // namespace llvm
+}
+}
#endif
virtual bool isValidAddress(uint64_t address) const = 0;
};
-} // namespace llvm
+}
#endif
Val_GNU_MIPS_ABI_MSA_ANY = 0, // not tagged
Val_GNU_MIPS_ABI_MSA_128 = 1 // 128-bit MSA
};
-} // namespace Mips
-} // namespace llvm
+}
+}
#endif
};
typedef SmartScopedLock<false> ScopedLock;
- } // namespace sys
-} // namespace llvm
+ }
+}
#endif
/// is held.
bool holds(const sys::Mutex& lock) const { return &M == &lock; }
};
-} // namespace llvm
+}
#endif // LLVM_SUPPORT_MUTEXGUARD_H
LoadOpt("load", cl::ZeroOrMore, cl::value_desc("pluginfilename"),
cl::desc("Load the specified plugin"));
#endif
-} // namespace llvm
+}
#endif
static unsigned GetRandomNumber();
};
-} // namespace sys
-} // namespace llvm
+}
+}
#endif
///< string is non-empty upon return an error occurred while invoking the
///< program.
);
- } // namespace sys
-} // namespace llvm
+ }
+}
#endif
}
};
typedef SmartScopedWriter<false> ScopedWriter;
- } // namespace sys
-} // namespace llvm
+ }
+}
#endif
friend class Module;
};
-} // namespace llvm
+}
#endif
}
};
-} // namespace llvm
+}
#endif
}
};
-} // namespace llvm
+}
template<class AllocatorType, class T, size_t Size, size_t Align>
inline void *operator new(size_t size,
struct llvm_regex *preg;
int error;
};
-} // namespace llvm
+}
#endif // LLVM_SUPPORT_REGEX_H
template <typename T, typename U>
typename Registry<T,U>::listener *Registry<T,U>::ListenerTail;
-} // namespace llvm
+}
#endif
/// different thread on some platforms.
/// @brief Register a function to be called when ctrl-c is pressed.
void SetInterruptFunction(void (*IF)());
-} // namespace sys
-} // namespace llvm
+} // End sys namespace
+} // End llvm namespace
#endif
bool ShowKindLabel = true) const;
};
-} // namespace llvm
+} // end llvm namespace
#endif
MemoryObject *getNonStreamedMemoryObject(
const unsigned char *Start, const unsigned char *End);
-} // namespace llvm
+}
#endif // STREAMINGMEMORYOBJECT_H_
inline bool operator!=(const PooledStringPtr &That) const { return S != That.S; }
};
-} // namespace llvm
+} // End llvm namespace
#endif
public:
BumpPtrStringSaver(BumpPtrAllocator &Alloc) : StringSaver(Alloc) {}
};
-} // namespace llvm
+}
#endif
bool print_warning = true ///< Control whether warnings are printed
);
-} // namespace llvm
+} // End llvm namespace
#endif
return new MCCodeEmitterImpl();
}
};
-} // namespace llvm
+}
#endif
#endif
}
-} // namespace llvm
+}
#endif
// erase - Removes the pointer associated with the current thread.
void erase() { removeInstance(); }
};
- } // namespace sys
-} // namespace llvm
+ }
+}
#endif
/// the thread stack.
void llvm_execute_on_thread(void (*UserFn)(void*), void *UserData,
unsigned RequestedStackSize = 0);
-} // namespace llvm
+}
#endif
return difference;
}
-} // namespace sys
-} // namespace llvm
+}
+}
#endif
void PrintQueuedTimers(raw_ostream &OS);
};
-} // namespace llvm
+} // End llvm namespace
#endif
void keep() { Installer.Keep = true; }
};
-} // namespace llvm
+} // end llvm namespace
#endif
bool owns_lock() { return locked; }
};
-} // namespace llvm
+}
#endif // LLVM_SUPPORT_UNIQUE_LOCK_H
#define TsanIgnoreWritesBegin()
#define TsanIgnoreWritesEnd()
#endif
-} // namespace sys
-} // namespace llvm
+}
+}
#endif
Watchdog(const Watchdog &other) = delete;
Watchdog &operator=(const Watchdog &other) = delete;
};
- } // namespace sys
-} // namespace llvm
+ }
+}
#endif
delete TheStream;
}
};
-} // namespace llvm
+} // end llvm namespace
#endif
~raw_os_ostream() override;
};
-} // namespace llvm
+} // end llvm namespace
#endif
~buffer_ostream() { OS << str(); }
};
-} // namespace llvm
+} // end llvm namespace
#endif
typedef const typename std::remove_pointer<T>::type *type;
};
-} // namespace llvm
+}
#ifdef LLVM_DEFINED_HAS_FEATURE
#undef __has_feature
extern SourceMgr SrcMgr;
extern unsigned ErrorsPrinted;
-} // namespace llvm
+} // end namespace "llvm"
#endif
Init *QualifyName(Record &CurRec, MultiClass *CurMultiClass,
const std::string &Name, const std::string &Scoper);
-} // namespace llvm
+} // End llvm namespace
#endif
unsigned CharNo, unsigned IndentCount) const;
};
-} // namespace llvm
+} // end llvm namespace.
#endif
ArgVT = argvt;
}
};
-} // namespace ISD
+}
-} // namespace llvm
+} // end llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
};
-} // namespace llvm
+} // End llvm namespace
#endif
unsigned numTys = 0) const = 0;
};
-} // namespace llvm
+} // End llvm namespace
#endif
SmallVectorImpl<ISD::OutputArg> &Outs,
const TargetLowering &TLI);
-} // namespace llvm
+} // end llvm namespace
#endif
bool DisableVerify = true) override;
};
-} // namespace llvm
+} // End llvm namespace
#endif
return !(LHS == RHS);
}
-} // namespace llvm
+} // End llvm namespace
#endif
void parseIndividualParams(const std::vector<std::string> &Args);
};
-} // namespace llvm
+} // End llvm namespace
#endif
return OS;
}
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // end llvm namespace
#endif
virtual bool enableSubRegLiveness() const { return false; }
};
-} // namespace llvm
+} // End llvm namespace
#endif
/// to bitsets.
ModulePass *createLowerBitSetsPass();
-} // namespace llvm
+} // End llvm namespace
#endif
bool shouldInline(CallSite CS);
};
-} // namespace llvm
+} // End llvm namespace
#endif
PreservedAnalyses run(Function &F, AnalysisManager<Function> *AM);
};
-} // namespace llvm
+}
#endif
/// protect against stack-based overflow vulnerabilities.
FunctionPass *createSafeStackPass();
-} // namespace llvm
+} // End llvm namespace
#endif
//
Pass *createObjCARCOptPass();
-} // namespace llvm
+} // End llvm namespace
#endif
//
FunctionPass *createLoopDistributePass();
-} // namespace llvm
+} // End llvm namespace
#endif
PreservedAnalyses run(Function &F, AnalysisManager<Function> *AM);
};
-} // namespace llvm
+}
#endif
PreservedAnalyses run(Function &F);
};
-} // namespace llvm
+}
#endif
PreservedAnalyses run(Function &F, AnalysisManager<Function> *AM);
};
-} // namespace llvm
+}
#endif
// The result is put here.
ASanStackFrameLayout *Layout);
-} // namespace llvm
+} // llvm namespace
#endif // LLVM_TRANSFORMS_UTILS_ASANSTACKFRAMELAYOUT_H
/// entered if the condition is false.
Value *GetIfCondition(BasicBlock *BB, BasicBlock *&IfTrue,
BasicBlock *&IfFalse);
-} // namespace llvm
+} // End llvm namespace
#endif
/// a pointer, Size is an 'intptr_t', and File is a pointer to FILE.
Value *EmitFWrite(Value *Ptr, Value *Size, Value *File, IRBuilder<> &B,
const DataLayout &DL, const TargetLibraryInfo *TLI);
-} // namespace llvm
+}
#endif
bool InlineFunction(CallSite CS, InlineFunctionInfo &IFI,
bool InsertLifetime = true);
-} // namespace llvm
+} // End llvm namespace
#endif
ValueSet &inputs,
ValueSet &outputs);
};
-} // namespace llvm
+}
#endif
bool optimizeGlobalCtorsList(Module &M,
function_ref<bool(Function *)> ShouldRemove);
-} // namespace llvm
+} // End llvm namespace
#endif
GlobalStatus();
};
-} // namespace llvm
+}
#endif
/// @brief Replace Rem with generated code.
bool expandDivisionUpTo64Bits(BinaryOperator *Div);
-} // namespace llvm
+} // End llvm namespace
#endif
/// the given edge. Returns the number of replacements made.
unsigned replaceDominatedUsesWith(Value *From, Value *To, DominatorTree &DT,
const BasicBlockEdge &Edge);
-} // namespace llvm
+} // End llvm namespace
#endif
/// variable. Returns true if this is an induction PHI along with the step
/// value.
bool isInductionPHI(PHINode *, ScalarEvolution *, ConstantInt *&);
-} // namespace llvm
+}
#endif
std::pair<Function *, Function *> createSanitizerCtorAndInitFunctions(
Module &M, StringRef CtorName, StringRef InitName,
ArrayRef<Type *> InitArgTypes, ArrayRef<Value *> InitArgs);
-} // namespace llvm
+} // End llvm namespace
#endif // LLVM_TRANSFORMS_UTILS_MODULEUTILS_H
AliasSetTracker *AST = nullptr,
AssumptionCache *AC = nullptr);
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
#undef DEBUG_TYPE // "ssaupdater"
-} // namespace llvm
+} // End llvm namespace
#endif
/// function by checking for an existing function with name FuncName + f
bool hasFloatVersion(StringRef FuncName);
};
-} // namespace llvm
+} // End llvm namespace
#endif
yaml::MappingNode *V,
RewriteDescriptorList *DL);
};
-} // namespace SymbolRewriter
+}
template <>
struct ilist_traits<SymbolRewriter::RewriteDescriptor>
ModulePass *createRewriteSymbolsPass();
ModulePass *createRewriteSymbolsPass(SymbolRewriter::RewriteDescriptorList &);
-} // namespace llvm
+}
#endif
Pass *createUnifyFunctionExitNodesPass();
-} // namespace llvm
+} // End llvm namespace
#endif
LPPassManager *LPM);
MDNode *GetUnrollMetadata(MDNode *LoopID, StringRef Name);
-} // namespace llvm
+}
#endif
Materializer));
}
-} // namespace llvm
+} // End llvm namespace
#endif
return Intrinsic::not_intrinsic;
}
-} // namespace llvm
+} // llvm namespace
#endif
bool vectorizeBasicBlock(Pass *P, BasicBlock &BB,
const VectorizeConfig &C = VectorizeConfig());
-} // namespace llvm
+} // End llvm namespace
#endif
return AliasAnalysis::getModRefInfo(CS1,CS2);
}
};
-} // namespace
+}
char AliasAnalysisCounter::ID = 0;
INITIALIZE_AG_PASS(AliasAnalysisCounter, AliasAnalysis, "count-aa",
bool runOnFunction(Function &F) override;
bool doFinalization(Module &M) override;
};
-} // namespace
+}
char AAEval::ID = 0;
INITIALIZE_PASS_BEGIN(AAEval, "aa-eval",
}
};
-} // namespace
+}
char AliasDebugger::ID = 0;
INITIALIZE_AG_PASS(AliasDebugger, AliasAnalysis, "debug-aa",
return false;
}
};
-} // namespace
+}
char AliasSetPrinter::ID = 0;
INITIALIZE_PASS_BEGIN(AliasSetPrinter, "print-alias-sets",
return !operator==(Other);
}
};
-} // namespace
+}
/// GetLinearExpression - Analyze the specified value as a linear expression:
static ChildIteratorType child_begin(NodeType *N) { return N->succ_begin(); }
static ChildIteratorType child_end(NodeType *N) { return N->succ_end(); }
};
-} // namespace llvm
+}
/// \brief Find extra irreducible headers.
///
AU.setPreservesAll();
}
};
-} // namespace
+}
char CFGViewer::ID = 0;
INITIALIZE_PASS(CFGViewer, "view-cfg", "View CFG of function", false, true)
AU.setPreservesAll();
}
};
-} // namespace
+}
char CFGOnlyViewer::ID = 0;
INITIALIZE_PASS(CFGOnlyViewer, "view-cfg-only",
AU.setPreservesAll();
}
};
-} // namespace
+}
char CFGPrinter::ID = 0;
INITIALIZE_PASS(CFGPrinter, "dot-cfg", "Print CFG of function to 'dot' file",
AU.setPreservesAll();
}
};
-} // namespace
+}
char CFGOnlyPrinter::ID = 0;
INITIALIZE_PASS(CFGOnlyPrinter, "dot-cfg-only",
typedef WeightedBidirectionalGraph<std::pair<EdgeType, StratifiedAttrs>> GraphT;
typedef DenseMap<Value *, GraphT::Node> NodeMapT;
-} // namespace
+}
// -- Setting up/registering CFLAA pass -- //
char CFLAliasAnalysis::ID = 0;
bool Captured;
};
-} // namespace
+}
/// PointerMayBeCaptured - Return true if this pointer value may be captured
/// by the enclosing function (which is required to exist). This routine can
}
}
-} // namespace
+} /// end namespace anonymous
FunctionPass *llvm::createDivergenceAnalysisPass() {
return new DivergenceAnalysis();
return DOTGraphTraits<DomTreeNode*>::getNodeLabel(Node, G->getRootNode());
}
};
-} // namespace llvm
+}
namespace {
struct DominatorTreeWrapperPassAnalysisGraphTraits {
}
};
-} // namespace llvm
+} // end llvm namespace
namespace {
GlobalValue *OkayStoreDest = nullptr);
bool AnalyzeIndirectGlobalMemory(GlobalValue *GV);
};
-} // namespace
+}
char GlobalsModRef::ID = 0;
INITIALIZE_AG_PASS_BEGIN(GlobalsModRef, AliasAnalysis,
void print(raw_ostream &O, const Module *M) const override {}
};
-} // namespace
+}
char InstCount::ID = 0;
INITIALIZE_PASS(InstCount, "instcount",
<< Val.getConstantRange().getUpper() << '>';
return OS << "constant<" << *Val.getConstant() << '>';
}
-} // namespace llvm
+}
//===----------------------------------------------------------------------===//
// LazyValueInfoCache Decl
deleted();
}
};
-} // namespace
+}
namespace {
/// This is the cache kept by LazyValueInfo which
WriteValues({V1, Vs...});
}
};
-} // namespace
+}
char Lint::ID = 0;
INITIALIZE_PASS_BEGIN(Lint, "lint", "Statically lint-checks LLVM IR",
};
char PrintLoopPass::ID = 0;
-} // namespace
+}
//===----------------------------------------------------------------------===//
// LPPassManager
return InstTypePair(inst, type);
}
};
-} // namespace
+}
char MemDepPrinter::ID = 0;
INITIALIZE_PASS_BEGIN(MemDepPrinter, "print-memdeps",
Vec.clear();
}
};
-} // namespace
+}
char MemDerefPrinter::ID = 0;
INITIALIZE_PASS_BEGIN(MemDerefPrinter, "print-memderefs",
}
void print(raw_ostream &O, const Module *M) const override;
};
-} // namespace
+}
char ModuleDebugInfoPrinter::ID = 0;
INITIALIZE_PASS(ModuleDebugInfoPrinter, "module-debuginfo",
}
};
-} // namespace
+}
char RegionOnlyPrinter::ID = 0;
INITIALIZE_PASS(RegionOnlyPrinter, "dot-regions-only",
llvm_unreachable("Unknown SCEV kind!");
}
};
-} // namespace
+}
/// GroupByComplexity - Given a list of SCEV objects, order them by their
/// complexity, and group objects of the same complexity together by value.
return false;
}
};
-} // namespace
+}
// Returns the size of the SCEV S.
static inline int sizeOfSCEV(const SCEV *S) {
const SCEV *Denominator, *Quotient, *Remainder, *Zero, *One;
};
-} // namespace
+}
//===----------------------------------------------------------------------===//
// Simple SCEV method implementations
const ExtendOpTraitsBase::GetExtendExprTy ExtendOpTraits<
SCEVZeroExtendExpr>::GetExtendExpr = &ScalarEvolution::getZeroExtendExpr;
-} // namespace
+}
// The recurrence AR has been shown to have no signed/unsigned wrap or something
// close to it. Typically, if we can prove NSW/NUW for AR, then we can just as
}
bool isDone() const { return FindOne; }
};
-} // namespace
+}
bool ScalarEvolution::checkValidity(const SCEV *S) const {
FindInvalidSCEVUnknown F;
return Found;
}
};
-} // namespace
+}
// Return true when S contains at least an undef value.
static inline bool
}
bool isDone() const { return false; }
};
-} // namespace
+}
/// Find parametric terms in this SCEVAddRecExpr.
void SCEVAddRecExpr::collectParametricTerms(
return FoundParameter;
}
};
-} // namespace
+}
// Returns true when S contains at least a SCEVUnknown parameter.
static inline bool
}
bool isDone() const { return IsFound; }
};
-} // namespace
+}
bool ScalarEvolution::hasOperand(const SCEV *S, const SCEV *Op) const {
SCEVSearch Search(Op);
}
};
-} // namespace
+}
Value *SCEVExpander::visitAddExpr(const SCEVAddExpr *S) {
Type *Ty = SE.getEffectiveSCEVType(S->getType());
}
bool isDone() const { return IsUnsafe; }
};
-} // namespace
+}
namespace llvm {
bool isSafeToExpand(const SCEV *S, ScalarEvolution &SE) {
bool inbounds(StratifiedIndex N) const { return N < Links.size(); }
};
-} // namespace llvm
+}
#endif // LLVM_ADT_STRATIFIEDSETS_H
return TBAAStructTypeNode(P);
}
};
-} // namespace
+}
namespace {
/// TypeBasedAliasAnalysis - This is a simple alias analysis
bool ParseUseListOrderIndexes(SmallVectorImpl<unsigned> &Indexes);
bool sortUseListOrder(Value *V, ArrayRef<unsigned> Indexes, SMLoc Loc);
};
-} // namespace llvm
+} // End llvm namespace
#endif
/// Provide fast operand accessors
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
};
-} // namespace
+}
// FIXME: can we inherit this from ConstantExpr?
template <>
public FixedNumOperandTraits<ConstantPlaceHolder, 1> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ConstantPlaceHolder, Value)
-} // namespace llvm
+}
void BitcodeReaderValueList::assignValue(Value *V, unsigned Idx) {
if (Idx == size()) {
llvm_unreachable("Unknown error type!");
}
};
-} // namespace
+}
static ManagedStatic<BitcodeErrorCategoryType> ErrorCategory;
return false;
}
};
-} // namespace
+}
char WriteBitcodePass::ID = 0;
IDs[V].first = ID;
}
};
-} // namespace
+}
static void orderValue(const Value *V, OrderMap &OM) {
if (OM.lookup(V).first)
void EnumerateNamedMetadata(const Module &M);
};
-} // namespace llvm
+} // End llvm namespace
#endif
RenameOrderType& RenameOrder,
std::map<unsigned, unsigned> &RenameMap);
};
-} // namespace llvm
+}
#endif
}
};
-} // namespace llvm
+}
#endif
void resetUsedFlag() { HasBeenUsed = false; }
};
-} // namespace llvm
+}
#endif
}
};
-} // namespace llvm
+}
#endif
AsmPrinter *AP;
DenseMap<const DIE *, unsigned> Numbering;
};
-} // namespace llvm
+}
#endif
void calculateDbgValueHistory(const MachineFunction *MF,
const TargetRegisterInfo *TRI,
DbgValueHistoryMap &Result);
-} // namespace llvm
+}
#endif
B.getExpression()->getBitPieceOffset();
}
-} // namespace llvm
+}
#endif
void dump() { print(dbgs()); }
#endif
};
-} // namespace llvm
+}
#endif
return getCUNode()->getEmissionKind() == DIBuilder::LineTablesOnly ||
(DD->useSplitDwarf() && !Skeleton);
}
-} // namespace llvm
+} // end llvm namespace
const MCSymbol *getBaseAddress() const { return BaseAddress; }
};
-} // namespace llvm
+} // end llvm namespace
#endif
void EmitUnsigned(uint64_t Value) override;
bool isFrameRegister(unsigned MachineReg) override;
};
-} // namespace llvm
+}
#endif
Vars.push_back(Var);
return true;
}
-} // namespace llvm
+}
return DITypeNodeToDieMap.lookup(TypeMD);
}
};
-} // namespace llvm
+}
#endif
/// Get a reference to an entry in the string pool.
EntryRef getEntry(AsmPrinter &Asm, StringRef Str);
};
-} // namespace llvm
+}
#endif
}
DwarfCompileUnit &getCU() override { return CU; }
};
-} // namespace llvm
+} // end llvm namespace
#endif
void beginInstruction(const MachineInstr *MI) override {}
void endInstruction() override {}
};
-} // namespace llvm
+}
#endif
return;
maybeRecordLocation(DL, Asm->MF);
}
-} // namespace llvm
+}
/// Gather and emit post-function exception information.
void endFunction(const MachineFunction *) override;
};
-} // namespace llvm
+}
#endif
bool isIdempotentRMW(AtomicRMWInst *AI);
bool simplifyIdempotentRMW(AtomicRMWInst *AI);
};
-} // namespace
+}
char AtomicExpand::ID = 0;
char &llvm::AtomicExpandID = AtomicExpand::ID;
MachineFunctionPass::getAnalysisUsage(AU);
}
};
-} // namespace
+}
char BranchFolderPass::ID = 0;
char &llvm::BranchFolderPassID = BranchFolderPass::ID;
bool HoistCommonCode(MachineFunction &MF);
bool HoistCommonCodeInSuccs(MachineBasicBlock *MBB);
};
-} // namespace llvm
+}
#endif /* LLVM_CODEGEN_BRANCHFOLDING_HPP */
bool splitBranchCondition(Function &F);
bool simplifyOffsetableRelocate(Instruction &I);
};
-} // namespace
+}
char CodeGenPrepare::ID = 0;
INITIALIZE_TM_PASS(CodeGenPrepare, "codegenprepare",
return (1 == PT->getAddressSpace());
}
};
-} // namespace
+}
static GCRegistry::Add<CoreCLRGC> X("coreclr", "CoreCLR-compatible GC");
const TargetRegisterClass *RC,
SmallVectorImpl<unsigned> &Forbid);
};
-} // namespace llvm
+}
#endif
// Schedule - Actual scheduling work.
void schedule() override;
};
-} // namespace llvm
+}
DefaultVLIWScheduler::DefaultVLIWScheduler(MachineFunction &MF,
MachineLoopInfo &MLI, bool IsPostRA)
private:
bool isDead(const MachineInstr *MI) const;
};
-} // namespace
+}
char DeadMachineInstructionElim::ID = 0;
char &llvm::DeadMachineInstructionElimID = DeadMachineInstructionElim::ID;
O << "}\n";
return O;
}
-} // namespace llvm
+}
/// view - Visualize the annotated bipartite CFG with Graphviz.
void EdgeBundles::view() const {
Instrs.clear();
}
};
-} // namespace
+}
namespace {
/// Information about a live register.
bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref);
void processUndefReads(MachineBasicBlock*);
};
-} // namespace
+}
char ExeDepsFix::ID = 0;
bool runOnFunction(Function &F) override;
bool doFinalization(Module &M) override;
};
-} // namespace
+}
INITIALIZE_PASS(GCModuleInfo, "collector-metadata",
"Create Garbage Collector Module Metadata", false, false)
bool runOnMachineFunction(MachineFunction &MF) override;
};
-} // namespace
+}
// -----------------------------------------------------------------------------
};
char IfConverter::ID = 0;
-} // namespace
+}
char &llvm::IfConverterID = IfConverter::ID;
bool runOnMachineFunction(MachineFunction &MF) override;
};
-} // namespace
+}
bool ImplicitNullChecks::runOnMachineFunction(MachineFunction &MF) {
TII = MF.getSubtarget().getInstrInfo();
void spillAroundUses(unsigned Reg);
void spillAll();
};
-} // namespace
+}
namespace llvm {
return new InlineSpiller(pass, mf, vrm);
}
-} // namespace llvm
+}
//===----------------------------------------------------------------------===//
// Snippets
/// in-loop predecessors of this chain.
unsigned LoopPredecessors;
};
-} // namespace
+}
namespace {
class MachineBlockPlacement : public MachineFunctionPass {
MachineFunctionPass::getAnalysisUsage(AU);
}
};
-} // namespace
+}
char MachineBlockPlacement::ID = 0;
char &llvm::MachineBlockPlacementID = MachineBlockPlacement::ID;
MachineFunctionPass::getAnalysisUsage(AU);
}
};
-} // namespace
+}
char MachineBlockPlacementStats::ID = 0;
char &llvm::MachineBlockPlacementStatsID = MachineBlockPlacementStats::ID;
void instr2instrSC(SmallVectorImpl<MachineInstr *> &Instrs,
SmallVectorImpl<const MCSchedClassDesc *> &InstrsSC);
};
-} // namespace
+}
char MachineCombiner::ID = 0;
char &llvm::MachineCombinerID = MachineCombiner::ID;
DenseMap<unsigned, MachineInstr*> &AvailCopyMap);
bool CopyPropagateBlock(MachineBasicBlock &MBB);
};
-} // namespace
+}
char MachineCopyPropagation::ID = 0;
char &llvm::MachineCopyPropagationID = MachineCopyPropagation::ID;
return OutStr;
}
};
-} // namespace llvm
+}
void MachineFunction::viewCFG() const
{
};
char MachineFunctionPrinterPass::ID = 0;
-} // namespace
+}
char &llvm::MachineFunctionPrinterPassID = MachineFunctionPrinterPass::ID;
INITIALIZE_PASS(MachineFunctionPrinterPass, "machineinstr-printer",
void UpdateForDeletedBlock(BasicBlock *BB);
void UpdateForRAUWBlock(BasicBlock *Old, BasicBlock *New);
};
-} // namespace llvm
+}
MCSymbol *MMIAddrLabelMap::getAddrLabelSymbol(BasicBlock *BB) {
assert(BB->hasAddressTaken() &&
}
};
-} // namespace llvm
+} // End llvm namespace
/// GetValueAtEndOfBlockInternal - Check to see if AvailableVals has an entry
/// for the specified BB and if so, return it. If not, construct SSA form by
protected:
void clusterNeighboringLoads(ArrayRef<SUnit*> Loads, ScheduleDAGMI *DAG);
};
-} // namespace
+} // anonymous
void LoadClusterMutation::clusterNeighboringLoads(ArrayRef<SUnit*> Loads,
ScheduleDAGMI *DAG) {
void apply(ScheduleDAGMI *DAG) override;
};
-} // namespace
+} // anonymous
/// \brief Callback from DAG postProcessing to create cluster edges to encourage
/// fused operations.
protected:
void constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG);
};
-} // namespace
+} // anonymous
/// constrainLocalCopy handles two possibilities:
/// 1) Local src:
MinInstrCountEnsemble(MachineTraceMetrics *mtm)
: MachineTraceMetrics::Ensemble(mtm) {}
};
-} // namespace
+}
// Select the preferred predecessor for MBB.
const MachineBasicBlock*
const MachineLoopInfo *loops)
: Blocks(blocks), Loops(loops), Downward(false) {}
};
-} // namespace
+}
// Specialize po_iterator_storage in order to prune the post-order traversal so
// it is limited to the current loop and doesn't traverse the loop back edges.
return LB.Visited.insert(To).second;
}
};
-} // namespace llvm
+}
/// Compute the trace through MBB.
void MachineTraceMetrics::Ensemble::computeTrace(const MachineBasicBlock *MBB) {
assert((++DefI).atEnd() && "Register has multiple defs");
}
};
-} // namespace
+}
// Get the input data dependencies that must be ready before UseMI can issue.
// Return true if UseMI has any physreg operands.
LiveRegUnit(unsigned RU) : RegUnit(RU), Cycle(0), MI(nullptr), Op(0) {}
};
-} // namespace
+}
// Identify physreg dependencies for UseMI, and update the live regunit
// tracking set when scanning instructions downwards.
}
};
-} // namespace
+}
char MachineVerifierPass::ID = 0;
INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
bool EntryIsSetup;
bool ExitIsSetup;
};
-} // namespace
+}
/// Make sure on every path through the CFG, a FrameSetup <n> is always followed
/// by a FrameDestroy <n>, stack adjustments are identical on all
bool IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle);
bool OptimizeBB(MachineBasicBlock &MBB);
};
-} // namespace
+}
char OptimizePHIs::ID = 0;
char &llvm::OptimizePHIsID = OptimizePHIs::ID;
MachineInstrExpressionTrait> LoweredPHIMap;
LoweredPHIMap LoweredPHIs;
};
-} // namespace
+}
STATISTIC(NumLowered, "Number of phis lowered");
STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
/// register of the last source.
unsigned getReg() const { return Reg; }
};
-} // namespace
+}
char PeepholeOptimizer::ID = 0;
char &llvm::PeepholeOptimizerID = PeepholeOptimizer::ID;
void dumpSchedule() const;
void emitNoop(unsigned CurCycle);
};
-} // namespace
+}
char &llvm::PostRASchedulerID = PostRAScheduler::ID;
bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
};
char RAFast::ID = 0;
-} // namespace
+}
/// getStackSpaceFor - This allocates space for the specified virtual register
/// to be held on the stack.
MBBPriorityInfo(MachineBasicBlock *mbb, unsigned depth, bool issplit)
: MBB(mbb), Depth(depth), IsSplit(issplit) {}
};
-} // namespace
+}
/// C-style comparator that sorts first based on the loop depth of the basic
/// block (the unsigned), and then on the MBB number.
/// Return the register class of the coalesced register.
const TargetRegisterClass *getNewRC() const { return NewRC; }
};
-} // namespace llvm
+} // End llvm namespace
#endif
return getCurr()->Preds.end();
}
};
-} // namespace
+} // anonymous
static bool hasDataSucc(const SUnit *SU) {
for (SUnit::const_succ_iterator
return G->addCustomGraphFeatures(GW);
}
};
-} // namespace llvm
+}
std::string DOTGraphTraits<ScheduleDAG*>::getNodeLabel(const SUnit *SU,
const ScheduleDAG *G) {
return TLI.getSetCCResultType(*DAG.getContext(), VT);
}
};
-} // namespace
+}
namespace {
DC.removeFromWorklist(N);
}
};
-} // namespace
+}
//===----------------------------------------------------------------------===//
// TargetLowering::DAGCombinerInfo implementation
return true;
}
};
-} // namespace
+}
/// \brief Check that all bits set in \p UsedBits form a dense region, i.e.,
/// \p UsedBits looks like 0..0 1..1 0..0.
DenseMap<SDValue, unsigned> &VRBaseMap);
};
-} // namespace llvm
+}
#endif
ReplacedNode(Old);
}
};
-} // namespace
+}
/// Return a vector shuffle operation which
/// performs the same shuffe in terms of order or result bytes, but on a type
NodesToAnalyze.insert(N);
}
};
-} // namespace
+}
/// ReplaceValueWith - The specified value was legalized to the specified other
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
}
-} // namespace
+}
bool SelectionDAG::LegalizeVectors() {
return VectorLegalizer(*this).Run();
bool isInvalidated() const { return Invalid; }
};
-} // namespace llvm
+} // end llvm namespace
#endif
void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
MachineBasicBlock::iterator InsertPos);
};
-} // namespace llvm
+}
#endif
: SelectionDAG::DAGUpdateListener(d), UI(ui), UE(ue) {}
};
-} // namespace
+}
/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
/// This can cause recursive merging of nodes in the DAG.
bool operator<(const UseMemo &L, const UseMemo &R) {
return (intptr_t)L.User < (intptr_t)R.User;
}
-} // namespace
+}
/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving
/// uses of other values produced by From.getNode() alone. The same value
VTs.push_back(MVT((MVT::SimpleValueType)i));
}
};
-} // namespace
+}
static ManagedStatic<std::set<EVT, EVT::compareRawBits> > EVTs;
static ManagedStatic<EVTArray> SimpleVTArray;
"Unknown sched type!");
return createILPListDAGScheduler(IS, OptLevel);
}
-} // namespace llvm
+}
// EmitInstrWithCustomInserter - This method should be implemented by targets
// that mark instructions with the 'usesCustomInserter' flag. These
J.setNode(E);
}
};
-} // namespace
+}
SDNode *SelectionDAGISel::
SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
"color=blue,style=dashed");
}
};
-} // namespace llvm
+}
std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
const SelectionDAG *G) {
Type *Ty, Value *BasePtr, int Idx1, int Idx2,
const char *Name);
};
-} // namespace
+}
INITIALIZE_PASS_BEGIN(ShadowStackGCLowering, "shadow-stack-gc-lowering",
"Shadow Stack GC Lowering", false, false)
}
}
};
-} // namespace
+}
Constant *ShadowStackGCLowering::GetFrameMap(Function &F) {
MachineFunction &mf,
VirtRegMap &vrm);
-} // namespace llvm
+}
#endif
unsigned IntvOut, SlotIndex EnterAfter);
};
-} // namespace llvm
+}
#endif
return (1 == PT->getAddressSpace());
}
};
-} // namespace
+}
static GCRegistry::Add<StatepointGC> X("statepoint-example",
"an example strategy for statepoint");
};
char TailDuplicatePass::ID = 0;
-} // namespace
+}
char &llvm::TailDuplicateID = TailDuplicatePass::ID;
AU.addPreserved<DominatorTreeWrapperPass>();
}
};
-} // namespace
+}
char UnreachableBlockElim::ID = 0;
INITIALIZE_PASS(UnreachableBlockElim, "unreachableblockelim",
"Remove unreachable blocks from the CFG", false, false)
void calculateStateNumbers(const Function &F);
void findActionRootLPads(const Function &F);
};
-} // namespace
+}
void WinEHNumbering::createUnwindMapEntry(int ToState, ActionHandler *AH) {
WinEHUnwindMapEntry UME;
}
}
}
-} // namespace llvm
+}
};
return makeArrayRef(sizes);
}
-} // namespace
+}
ArrayRef<uint8_t> DWARFFormValue::getFixedFormSizes(uint8_t AddrSize,
uint16_t Version) {
llvm::raw_ostream& get() { return OS; }
operator llvm::raw_ostream& () { return OS; }
};
-} // namespace syntax
-} // namespace dwarf
-} // namespace llvm
+}
+}
+}
#endif
ArgListType Args;
ArgListType::const_iterator CurIter;
};
-} // namespace
+}
PDBSymbolFunc::PDBSymbolFunc(const IPDBSession &PDBSession,
std::unique_ptr<IPDBRawSymbol> Symbol)
const IPDBSession &Session;
std::unique_ptr<ArgEnumeratorType> Enumerator;
};
-} // namespace
+}
PDBSymbolTypeFunctionSig::PDBSymbolTypeFunctionSig(
const IPDBSession &PDBSession, std::unique_ptr<IPDBRawSymbol> Symbol)
};
-} // namespace llvm
+} // End llvm namespace
#endif
bool CheckFunctionsOnly);
};
-} // namespace llvm
+} // End llvm namespace
#endif
return OwningBinary<ObjectFile>();
}
};
-} // namespace
+}
namespace llvm {
return (S == MCDisassembler::Success);
}
};
-} // namespace llvm
+}
RuntimeDyldCheckerImpl::RuntimeDyldCheckerImpl(RuntimeDyld &RTDyld,
MCDisassembler *Disassembler,
StubMap Stubs;
};
-} // namespace llvm
+}
#endif
}
};
-} // namespace
+}
namespace llvm {
addRelocationForSection(TargetRE, RE.SectionID);
}
};
-} // namespace llvm
+}
#undef DEBUG_TYPE
}
};
-} // namespace llvm
+}
#undef DEBUG_TYPE
}
};
-} // namespace llvm
+}
#undef DEBUG_TYPE
resolveRelocation(TargetRE, (uint64_t)Addr);
}
};
-} // namespace llvm
+}
#undef DEBUG_TYPE
IDs[V].first = ID;
}
};
-} // namespace
+}
static void orderValue(const Value *V, OrderMap &OM) {
if (OM.lookup(V).first)
AlignOf<AttributeSetImpl::IndexAttrPair>::Alignment,
"Alignment is insufficient for objects appended to AttributeSetImpl");
-} // namespace llvm
+} // end llvm namespace
#endif
ArrayRef<Constant *> Idxs);
Constant *ConstantFoldGetElementPtr(Type *Ty, Constant *C, bool inBounds,
ArrayRef<Value *> Idxs);
-} // namespace llvm
+} // End llvm namespace
#endif
return HeaderBuilder().concat("0x" + Twine::utohexstr(Tag));
}
};
-} // namespace
+}
DIBuilder::DIBuilder(Module &m, bool AllowUnresolvedNodes)
: M(m), VMContext(M.getContext()), TempEnumTypes(nullptr),
"the given regular expression"),
cl::Hidden, cl::location(PassRemarksAnalysisOptLoc), cl::ValueRequired,
cl::ZeroOrMore);
-} // namespace
+}
int llvm::getNextAvailablePluginDiagnosticKind() {
static std::atomic<int> PluginKindID(DK_FirstPluginKind);
OS << format("%5u:", LineNum) << Line << "\n";
}
};
-} // namespace
+}
/// Convert a path to a gcov filename. If PreservePaths is true, this
/// translates "/" to "#", ".." to "^", and drops ".", to match gcov.
}
};
-} // namespace
+}
char PrintModulePassWrapper::ID = 0;
INITIALIZE_PASS(PrintModulePassWrapper, "print-module",
P.first->dropAllReferences();
}
};
-} // namespace
+}
LLVMContextImpl::~LLVMContextImpl() {
// NOTE: We need to delete the contents of OwnedModules, but Module's dtor
/// does not cause MDOperand to be transparent. In particular, a bare pointer
/// doesn't get hashed before it's combined, whereas \a MDOperand would.
static const Metadata *get_hashable_data(const MDOperand &X) { return X.get(); }
-} // namespace llvm
+}
unsigned MDNodeOpsKey::calculateHash(MDNode *N, unsigned Offset) {
unsigned Hash = hash_combine_range(N->op_begin() + Offset, N->op_end());
void dropTriviallyDeadConstantArrays();
};
-} // namespace llvm
+}
#endif
void FunctionPassManagerImpl::anchor() {}
char FunctionPassManagerImpl::ID = 0;
-} // namespace legacy
-} // namespace llvm
+} // End of legacy namespace
+} // End of llvm namespace
namespace {
//===----------------------------------------------------------------------===//
void PassManagerImpl::anchor() {}
char PassManagerImpl::ID = 0;
-} // namespace legacy
-} // namespace llvm
+} // End of legacy namespace
+} // End of llvm namespace
namespace {
}
};
-} // namespace
+} // End of anon namespace
static TimingInfo *TheTimeInfo;
}
return true;
}
-} // namespace llvm
+}
CFGOnlyList.push_back(P->getTypeInfo());
}
};
-} // namespace
+}
// setPreservesCFG - This function should be called to by the pass, iff they do
// not:
}
}
-} // namespace llvm
+} // End llvm namespace
#endif
}
}
-} // namespace llvm
+} // End llvm namespace
llvm_unreachable("should never destroy an Operator");
}
-} // namespace llvm
+} // End llvm namespace
AU.setPreservesAll();
}
};
-} // namespace
+}
char VerifierLegacyPass::ID = 0;
INITIALIZE_PASS(VerifierLegacyPass, "verify", "Module Verifier", false, false)
LibOptTable() : OptTable(infoTable, llvm::array_lengthof(infoTable), true) {}
};
-} // namespace
+}
static std::string getOutputPath(llvm::opt::InputArgList *Args) {
if (auto *Arg = Args->getLastArg(OPT_out))
bool areTypesIsomorphic(Type *DstTy, Type *SrcTy);
};
-} // namespace
+}
void TypeMapTy::addTypeMapping(Type *DstTy, Type *SrcTy) {
assert(SpeculativeTypes.empty());
void linkNamedMDNodes();
void stripReplacedSubprograms();
};
-} // namespace
+}
/// The LLVM SymbolTable class autorenames globals that conflict in the symbol
/// table. This is good for all clients except for us. Go through the trouble
uint32_t GroupSymbolIndex, uint64_t Offset, uint64_t Size,
const MCSectionELF &Section);
};
-} // namespace
+}
void ELFObjectWriter::align(unsigned Alignment) {
uint64_t Padding = OffsetToAlignment(OS.tell(), Alignment);
STATISTIC(ObjectBytes, "Number of emitted object file bytes");
STATISTIC(RelaxationSteps, "Number of assembler layout and relaxation steps");
STATISTIC(RelaxedInstructions, "Number of relaxed instructions");
-} // namespace stats
-} // namespace
+}
+}
// FIXME FIXME FIXME: There are number of places in this file where we convert
// what is a 64-bit assembler value used for computation into a value in the
return new MCExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
SymbolLookUp, DisInfo);
}
-} // namespace llvm
+}
bool IsSignalFrame;
bool IsSimple;
};
-} // namespace
+}
namespace llvm {
template <>
LHS.IsSimple == RHS.IsSimple;
}
};
-} // namespace llvm
+}
void MCDwarfFrameEmitter::Emit(MCObjectStreamer &Streamer, MCAsmBackend *MAB,
bool IsEH) {
void EmitGPRel32Value(const MCExpr *Value) override {}
};
-} // namespace
+}
MCStreamer *llvm::createNullStreamer(MCContext &Context) {
return new MCNullStreamer(Context);
void initializeDirectiveKindMap();
};
-} // namespace
+}
namespace llvm {
private:
AsmLexer &Lexer;
};
-} // namespace
+}
bool AsmParser::parseMacroArgument(MCAsmMacroArgument &MA, bool Vararg) {
COFFAsmParser() {}
};
-} // namespace
+} // end annonomous namespace.
static SectionKind computeSectionKind(unsigned Flags) {
if (Flags & COFF::IMAGE_SCN_MEM_EXECUTE)
unsigned parseSunStyleSectionFlags();
};
-} // namespace
+}
/// ParseDirectiveSymbolAttribute
/// ::= { ".local", ".weak", ... } [ identifier ( , identifier )* ]
// One bit.
ELF_BindingSet_Shift = 12
};
-} // namespace
+}
void MCSymbolELF::setBinding(unsigned Binding) const {
setIsBindingSet();
bool MCSymbolELF::isBindingSet() const {
return getFlags() & (0x1 << ELF_BindingSet_Shift);
}
-} // namespace llvm
+}
llvm::EmitUnwindInfo(Streamer, info);
}
-} // namespace Win64EH
+}
} // End of namespace llvm
return getUnwindInfoSection(".xdata", XData, Function, Context);
}
-} // namespace WinEH
-} // namespace llvm
+}
+}
void writeObject(MCAssembler &Asm, const MCAsmLayout &Layout) override;
};
-} // namespace
+}
static inline void write_uint32_le(void *Data, uint32_t Value) {
support::endian::write<uint32_t, support::little, support::unaligned>(Data,
void MCWinCOFFStreamer::FatalError(const Twine &Msg) const {
getContext().reportFatalError(SMLoc(), Msg);
}
-} // namespace llvm
+}
COFF::DLLCharacteristics Characteristics;
};
-} // namespace
+}
void MappingTraits<COFFYAML::Relocation>::mapping(IO &IO,
COFFYAML::Relocation &Rel) {
IO.mapRequired("symbols", Obj.Symbols);
}
-} // namespace yaml
-} // namespace llvm
+}
+}
ELFYAML::ELF_STV Visibility;
ELFYAML::ELF_STO Other;
};
-} // namespace
+}
void MappingTraits<ELFYAML::Symbol>::mapping(IO &IO, ELFYAML::Symbol &Symbol) {
IO.mapOptional("Name", Symbol.Name, StringRef());
ELFYAML::ELF_REL Type3;
ELFYAML::ELF_RSS SpecSym;
};
-} // namespace
+}
void MappingTraits<ELFYAML::Relocation>::mapping(IO &IO,
ELFYAML::Relocation &Rel) {
void EmitCommonSymbol(MCSymbol *Symbol, uint64_t Size,
unsigned ByteAlignment) override;
};
-} // namespace llvm
+}
#endif
static inline bool operator<(const OptTable::Info &I, const char *Name) {
return StrCmpOptionNameIgnoreCase(I.Name, Name) < 0;
}
-} // namespace opt
-} // namespace llvm
+}
+}
OptSpecifier::OptSpecifier(const Option *Opt) : ID(Opt->getID()) {}
return Segments;
}
};
-} // namespace
+}
std::vector<StringRef> CoverageMapping::getUniqueSourceFiles() const {
std::vector<StringRef> Filenames;
llvm_unreachable("A value of coveragemap_error has no message.");
}
};
-} // namespace
+}
static ManagedStatic<CoverageMappingErrorCategoryType> ErrorCategory;
return std::error_code();
}
};
-} // namespace
+}
template <typename T, support::endianness Endian>
std::error_code readCoverageMappingData(
return C;
}
};
-} // namespace
+}
/// \brief Encode the counter.
///
llvm_unreachable("A value of instrprof_error has no message.");
}
};
-} // namespace
+}
static ManagedStatic<InstrProfErrorCategoryType> ErrorCategory;
const uint64_t Magic = 0x8169666f72706cff; // "\xfflprofi\x81"
const uint64_t Version = 2;
const HashT HashType = HashT::MD5;
-} // namespace IndexedInstrProf
+}
} // end namespace llvm
}
}
};
-} // namespace
+}
std::error_code
InstrProfWriter::addFunctionCounts(StringRef FunctionName,
llvm_unreachable("A value of sampleprof_error has no message.");
}
};
-} // namespace
+}
static ManagedStatic<SampleProfErrorCategoryType> ErrorCategory;
const unsigned int maxPowerOfFiveExponent = maxExponent + maxPrecision - 1;
const unsigned int maxPowerOfFiveParts = 2 + ((maxPowerOfFiveExponent * 815)
/ (351 * integerPartWidth));
-} // namespace llvm
+}
/* A bunch of private, handy routines. */
exp += FirstSignificant;
buffer.erase(&buffer[0], &buffer[FirstSignificant]);
}
-} // namespace
+}
void APFloat::toString(SmallVectorImpl<char> &Str,
unsigned FormatPrecision,
{
return findFirstSet(value, ZB_Max);
}
-} // namespace
+}
/* Sets the least significant part of a bignum to the input value, and
zeroes out higher parts. */
{ ARMBuildAttrs::ABI_align_needed, "Tag_ABI_align8_needed" },
{ ARMBuildAttrs::ABI_align_preserved, "Tag_ABI_align8_preserved" },
};
-} // namespace
+}
namespace llvm {
namespace ARMBuildAttrs {
return ARMAttributeTags[TI].Attr;
return -1;
}
-} // namespace ARMBuildAttrs
-} // namespace llvm
+}
+}
return std::make_pair(GPRMask, VFPMask);
}
-} // namespace WinEH
-} // namespace ARM
-} // namespace llvm
+}
+}
+}
<< "Number of elements free for recycling: " << FreeListSize << '\n';
}
-} // namespace llvm
+}
TEMPLATE_INSTANTIATION(class opt<std::string>);
TEMPLATE_INSTANTIATION(class opt<char>);
TEMPLATE_INSTANTIATION(class opt<bool>);
-} // namespace cl
-} // namespace llvm
+}
+} // end namespace llvm::cl
// Pin the vtables to this file.
void GenericOptionValue::anchor() {}
}
};
-} // namespace
+}
static ManagedStatic<sys::Mutex> gCrashRecoveryContextMutex;
static bool gCrashRecoveryEnabled = false;
: DDAI(DDAI), Required(Required) {}
};
-} // namespace
+}
DAGDeltaAlgorithmImpl::DAGDeltaAlgorithmImpl(
DAGDeltaAlgorithm &DDA, const changeset_ty &Changes,
}
};
-} // namespace
+}
std::unique_ptr<DataStreamer>
llvm::getDataFileStreamer(const std::string &Filename, std::string *StrError) {
}
};
-} // namespace
+}
static DebugOnlyOpt DebugOnlyOptLoc;
// Rename file to final name.
return sys::fs::rename(Twine(TempPath), Twine(FinalPath));
}
-} // namespace llvm
+} // namespace
Res << format("%.2x", Result[i]);
}
-} // namespace llvm
+}
const float huge_valf = HUGE_VALF;
#endif
-} // namespace llvm
+}
return MemoryBuffer_Malloc;
}
};
-} // namespace
+}
static ErrorOr<std::unique_ptr<MemoryBuffer>>
getFileAux(const Twine &Filename, int64_t FileSize, uint64_t MapSize,
return MemoryBuffer_MMap;
}
};
-} // namespace
+}
static ErrorOr<std::unique_ptr<MemoryBuffer>>
getMemoryBufferForStream(int FD, const Twine &BufferName) {
return errorcode == 0;
}
-} // namespace llvm
+}
#elif defined(LLVM_ON_UNIX)
#include "Unix/Mutex.inc"
return errorcode == 0;
}
-} // namespace llvm
+}
#elif defined(LLVM_ON_UNIX)
#include "Unix/RWMutex.inc"
Stats.push_back(S);
}
};
-} // namespace
+}
static ManagedStatic<StatisticInfo> StatInfo;
static ManagedStatic<sys::SmartMutex<true> > StatLock;
BytesSkipped(0), ObjectSize(0), EOFReached(false) {
BytesRead = this->Streamer->GetBytes(&Bytes[0], kChunkSize);
}
-} // namespace llvm
+}
}
}
-} // namespace llvm
+}
/// Include the platform-specific portion of TimeValue class
#ifdef LLVM_ON_UNIX
InfoOutputFilename("info-output-file", cl::value_desc("filename"),
cl::desc("File to append -stats and -timer output to"),
cl::Hidden, cl::location(getLibSupportInfoOutputFilename()));
-} // namespace
+}
// CreateInfoOutputFile - Return a file stream to print our output on.
raw_ostream *llvm::CreateInfoOutputFile() {
}
};
-} // namespace
+}
static ManagedStatic<Name2TimerMap> NamedTimers;
static ManagedStatic<Name2PairMap> NamedGroupedTimers;
int &FD;
bool KeepOpen;
};
-} // namespace
+}
std::error_code Process::FixupStandardFileDescriptors() {
int NullFD = -1;
#endif
}
-} // namespace llvm
+}
static bool Execute(ProcessInfo &PI, StringRef Program, const char **args,
const char **envp, const StringRef **redirects,
}
return true;
}
-} // namespace llvm
+}
setInstance(nullptr);
}
-} // namespace llvm
+}
#else
namespace llvm {
using namespace sys;
NANOSECONDS_PER_MICROSECOND ) );
}
-} // namespace llvm
+}
alarm(0);
#endif
}
- } // namespace sys
-} // namespace llvm
+ }
+}
Token() : Kind(TK_Error) {}
};
-} // namespace yaml
-} // namespace llvm
+}
+}
namespace llvm {
template<>
BumpPtrAllocator Alloc;
};
-} // namespace llvm
+}
typedef ilist<Token> TokenQueueT;
return Tok == Other.Tok;
}
};
-} // namespace
+}
/// @brief The Unicode scalar value of a UTF-8 minimal well-formed code unit
/// subsequence and the subsequence's length in code units (uint8_t).
// String valued tokens.
Id, StrVal, VarName, CodeFragment
};
-} // namespace tgtok
+}
/// TGLexer - TableGen Lexer class.
class TGLexer {
Color getColor(unsigned Register);
Chain *getAndEraseNext(Color PreferredColor, std::vector<Chain*> &L);
};
-} // namespace
+}
char AArch64A57FPLoadBalancing::ID = 0;
}
};
char AArch64BranchRelaxation::ID = 0;
-} // namespace
+}
/// verify - check BBOffsets, BBSizes, alignment of islands
void AArch64BranchRelaxation::verify() {
return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, SlotAlign);
}
-} // namespace
+}
#endif
MachineFunctionPass::getAnalysisUsage(AU);
}
};
-} // namespace
+}
char LDTLSCleanup::ID = 0;
FunctionPass *llvm::createAArch64CleanupLocalDynamicTLSPass() {
unsigned BitSize);
};
char AArch64ExpandPseudo::ID = 0;
-} // namespace
+}
/// \brief Transfer implicit operands on the pseudo instruction to the
/// instructions created from the expansion.
RegScavenger *RS) const override;
};
-} // namespace llvm
+} // End llvm namespace
#endif
MCSymbol *GetGlobalAddressSymbol(const MachineOperand &MO) const;
MCSymbol *GetExternalSymbolSymbol(const MachineOperand &MO) const;
};
-} // namespace llvm
+}
#endif
MILOHContainer LOHContainerSet;
SetOfInstructions LOHRelated;
};
-} // namespace llvm
+} // End llvm namespace
#endif
return isOdd(reg1) == isOdd(reg2);
}
-} // namespace
+}
bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd,
unsigned Ra) {
// Add constraints between existing chains
void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
};
-} // namespace llvm
+}
#endif // LLVM_LIB_TARGET_AARCH64_AARCH64PBQPREGALOC_H
unsigned Align, bool isVolatile,
MachinePointerInfo DstPtrInfo) const override;
};
-} // namespace llvm
+}
#endif
}
};
char AArch64StorePairSuppress::ID = 0;
-} // namespace
+} // anonymous
FunctionPass *llvm::createAArch64StorePairSuppressPass() {
return new AArch64StorePairSuppress();
std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
};
-} // namespace llvm
+} // End llvm namespace
#endif
static const char *getRegisterName(unsigned RegNo,
unsigned AltIdx = AArch64::NoRegAltName);
};
-} // namespace llvm
+}
#endif
UNWIND_AArch64_FRAME_D14_D15_PAIR = 0x00000800
};
-} // namespace CU
+} // end CU namespace
// FIXME: This should be in a separate file.
class DarwinAArch64AsmBackend : public AArch64AsmBackend {
}
AArch64AsmBackend::applyFixup (Fixup, Data, DataSize, Value, IsPCRel);
}
-} // namespace
+}
MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
private:
};
-} // namespace
+}
AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI,
bool IsLittleEndian)
return new AArch64TargetELFStreamer(S);
return nullptr;
}
-} // namespace llvm
+}
MCTargetStreamer *createAArch64ObjectTargetStreamer(MCStreamer &S,
const MCSubtargetInfo &STI);
-} // namespace llvm
+} // End llvm namespace
// Defines symbolic names for AArch64 registers. This defines a mapping from
// register name to register number.
const MCFixup &Fixup, MCValue Target,
uint64_t &FixedValue) override;
};
-} // namespace
+}
bool AArch64MachObjectWriter::getAArch64FixupKindMachOInfo(
const MCFixup &Fixup, unsigned &RelocType, const MCSymbolRefExpr *Sym,
ATMapper();
};
-} // namespace AArch64AT
+}
namespace AArch64DB {
enum DBValues {
Invalid = -1,
DBarrierMapper();
};
-} // namespace AArch64DB
+}
namespace AArch64DC {
enum DCValues {
DCMapper();
};
-} // namespace AArch64DC
+}
namespace AArch64IC {
enum ICValues {
static inline bool NeedsRegister(ICValues Val) {
return Val == IVAU;
}
-} // namespace AArch64IC
+}
namespace AArch64ISB {
enum ISBValues {
ISBMapper();
};
-} // namespace AArch64ISB
+}
namespace AArch64PRFM {
enum PRFMValues {
PRFMMapper();
};
-} // namespace AArch64PRFM
+}
namespace AArch64PState {
enum PStateValues {
PStateMapper();
};
-} // namespace AArch64PState
+}
namespace AArch64SE {
enum ShiftExtSpecifiers {
SXTW,
SXTX
};
-} // namespace AArch64SE
+}
namespace AArch64Layout {
enum VectorLayout {
VL_S,
VL_D
};
-} // namespace AArch64Layout
+}
inline static const char *
AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) {
};
uint32_t ParseGenericRegister(StringRef Name, bool &Valid);
-} // namespace AArch64SysReg
+}
namespace AArch64TLBI {
enum TLBIValues {
return true;
}
}
-} // namespace AArch64TLBI
+}
namespace AArch64II {
/// Target Operand Flag enum.
size_t DisasmLineMaxLen;
};
-} // namespace llvm
+} // End anonymous llvm
#endif
};
int DiagnosticInfoUnsupported::KindID = 0;
-} // namespace
+}
static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
} // End namespace AMDGPU
-} // namespace llvm
+} // End llvm namespace
#define AMDGPU_FLAG_REGISTER_LOAD (UINT64_C(1) << 63)
#define AMDGPU_FLAG_REGISTER_STORE (UINT64_C(1) << 62)
bool IsKernel;
};
-} // namespace llvm
+}
#endif
bool (*ConvertResult)(int64_t&);
};
-} // namespace
+}
static unsigned getRegClass(bool IsVgpr, unsigned RegWidth) {
if (IsVgpr) {
LastTargetFixupKind,
NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
};
-} // namespace AMDGPU
-} // namespace llvm
+}
+}
#endif
MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit,
raw_pwrite_stream &OS);
-} // namespace llvm
+} // End llvm namespace
#define GET_REGINFO_ENUM
#include "AMDGPUGenRegisterInfo.inc"
IS_EXPORT = (1 << 17),
LDS_1A2D = (1 << 18)
};
-} // namespace R600_InstFlag
+}
#define HAS_NATIVE_OPERANDS(Flags) ((Flags) & R600_InstFlag::NATIVE_OPERANDS)
VEC_COUNT
};
-} // namespace OpName
+}
//===----------------------------------------------------------------------===//
// Config register definitions
SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
};
-} // namespace llvm
+} // End namespace llvm;
#endif
} //End namespace AMDGPU
-} // namespace llvm
+} // End llvm namespace
#endif
unsigned StackSize;
};
-} // namespace llvm
+} // End llvm namespace
#endif
return false;
}
-} // namespace
+}
llvm::FunctionPass *llvm::createR600VectorRegMerger(TargetMachine &tm) {
return new R600VectorRegMerger(tm);
char R600TextureIntrinsicsReplacer::ID = 0;
-} // namespace
+}
FunctionPass *llvm::createR600TextureIntrinsicsReplacer() {
return new R600TextureIntrinsicsReplacer();
WQM = 1 << 20,
VGPRSpill = 1 << 21
};
-} // namespace SIInstrFlags
+}
namespace llvm {
namespace AMDGPU {
P_NORMAL = 1 << 8, // Positive normal
P_INFINITY = 1 << 9 // Positive infinity
};
-} // namespace SIInstrFlags
+}
namespace SISrcMods {
enum {
void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
ARMAsmPrinter &AP);
-} // namespace llvm
+} // end namespace llvm;
#endif
// all definitions of CPSR are dead
return true;
}
-} // namespace llvm
+}
/// GetInstSize - Return the size of the specified MachineInstr.
///
unsigned FrameReg, int &Offset,
const ARMBaseInstrInfo &TII);
-} // namespace llvm
+} // End llvm namespace
#endif
return true;
}
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
char ARMConstantIslands::ID = 0;
-} // namespace
+}
/// verify - check BBOffsets, BBSizes, alignment of islands
void ARMConstantIslands::verify() {
GOTTPOFF,
TPOFF
};
-} // namespace ARMCP
+}
/// ARMConstantPoolValue - ARM specific constantpool value. This is used to
/// represent PC-relative displacement between the address of the load
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
MachineBasicBlock::iterator &MBBI);
};
char ARMExpandPseudo::ID = 0;
-} // namespace
+}
/// TransferImpOps - Transfer implicit operands on the pseudo instruction to
/// the instructions created from the expansion.
return PseudoOpc < TE.PseudoOpc;
}
};
-} // namespace
+}
static const NEONLdStTableEntry NEONLdStTable[] = {
{ ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
{ { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
{ { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
};
-} // namespace
+}
/// \brief The specified machine instr operand is a vreg, and that
/// vreg is being provided by the specified load instruction. If possible,
}
}
-} // namespace llvm
+}
#endif
}
}
};
-} // namespace
+}
/// Emit an instruction sequence that will align the address in
/// register Reg by zero-ing out the lower bits. For versions of the
MachineBasicBlock::iterator MI) const override;
};
-} // namespace llvm
+} // End llvm namespace
#endif
SDValue GetVLDSTAlign(SDValue Align, SDLoc dl, unsigned NumVecs,
bool is64BitVector);
};
-} // namespace
+}
/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
/// operand. If so Imm will receive the 32-bit value.
CallOrPrologue = PC;
}
};
-} // namespace
+}
// The APCS parameter registers.
static const MCPhysReg GPRArgRegs[] = {
VST3LN_UPD,
VST4LN_UPD
};
- } // namespace ARMISD
+ }
/// Define some predicates that are used for node matching.
namespace ARM {
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
const TargetLibraryInfo *libInfo);
}
-} // namespace llvm
+}
#endif // ARMISELLOWERING_H
MachineFunctionPass::getAnalysisUsage(AU);
}
};
-} // namespace
+}
char ARMCGBR::ID = 0;
FunctionPass*
Reloc::Model RM) const override;
};
-} // namespace llvm
+}
#endif
bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
};
char ARMLoadStoreOpt::ID = 0;
-} // namespace
+}
static bool definesCPSR(const MachineInstr *MI) {
for (const auto &MO : MI->operands()) {
bool RescheduleLoadStoreInstrs(MachineBasicBlock *MBB);
};
char ARMPreAllocLoadStoreOpt::ID = 0;
-} // namespace
+}
bool ARMPreAllocLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
TD = Fn.getTarget().getDataLayout();
return It;
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
char ARMOptimizeBarriersPass::ID = 0;
-} // namespace
+}
// Returns whether the instruction can safely move past a DMB instruction
// The current implementation allows this iif MI does not have any possible
RTLIB::Libcall LC) const;
};
-} // namespace llvm
+}
#endif
/// True if fast-isel is used.
bool useFastISel() const;
};
-} // namespace llvm
+} // End llvm namespace
#endif // ARMSUBTARGET_H
private:
std::vector<unsigned char> ITStates;
};
-} // namespace
+}
namespace {
/// ARM disassembler for all ARM platforms.
DecodeStatus AddThumbPredicate(MCInst&) const;
void UpdateThumbVFPPredicate(MCInst&) const;
};
-} // namespace
+}
static bool Check(DecodeStatus &Out, DecodeStatus In) {
switch (In) {
Subtype);
}
};
-} // namespace
+}
#endif
return createARMELFObjectWriter(OS, OSABI, isLittle());
}
};
-} // namespace
+}
#endif
case ID: return "id";
}
}
-} // namespace ARM_PROC
+}
namespace ARM_MB {
// The Memory Barrier Option constants map directly to the 4-bit encoding of
} // end namespace ARMII
-} // namespace llvm
+} // end namespace llvm;
#endif
bool needsRelocateWithSymbol(const MCSymbol &Sym,
unsigned Type) const override;
};
-} // namespace
+}
ARMELFObjectWriter::ARMELFObjectWriter(uint8_t OSABI)
: MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI,
return S;
}
-} // namespace llvm
+}
LastTargetFixupKind,
NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
};
-} // namespace ARM
-} // namespace llvm
+}
+}
#endif
}
};
-} // namespace
+}
static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
return new ARMMCInstrAnalysis(Info);
/// Construct ARM Mach-O relocation info.
MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
-} // namespace llvm
+} // End llvm namespace
// Defines symbolic names for ARM registers. This defines a mapping from
// register name to register number.
const MCFixup &Fixup, MCValue Target,
uint64_t &FixedValue) override;
};
-} // namespace
+}
static bool getARMFixupKindMachOInfo(unsigned Kind, unsigned &RelocType,
unsigned &Log2Size) {
EmitByte(ARM::EHABI::UNWIND_OPCODE_FINISH);
}
};
-} // namespace
+}
void UnwindOpcodeAssembler::EmitRegSave(uint32_t RegSave) {
if (RegSave == 0u)
bool ARMWinCOFFObjectWriter::recordRelocation(const MCFixup &Fixup) const {
return static_cast<unsigned>(Fixup.getKind()) != ARM::fixup_t2_movt_hi16;
}
-} // namespace
+}
namespace llvm {
MCObjectWriter *createARMWinCOFFObjectWriter(raw_pwrite_stream &OS,
void ARMWinCOFFStreamer::EmitThumbFunc(MCSymbol *Symbol) {
getAssembler().setIsThumbFunc(Symbol);
}
-} // namespace
+}
MCStreamer *llvm::createARMWinCOFFStreamer(MCContext &Context,
MCAsmBackend &MAB,
bool ExpandFPMLxInstructions(MachineBasicBlock &MBB);
};
char MLxExpansion::ID = 0;
-} // namespace
+}
void MLxExpansion::clearStack() {
std::fill(LastMIs, LastMIs + 4, nullptr);
MachineBasicBlock::iterator MI) const override;
};
-} // namespace llvm
+} // End llvm namespace
#endif
void expandLoadStackGuard(MachineBasicBlock::iterator MI,
Reloc::Model RM) const override;
};
-} // namespace llvm
+}
#endif
bool InsertITInstructions(MachineBasicBlock &MBB);
};
char Thumb2ITBlockPass::ID = 0;
-} // namespace
+}
/// TrackDefUses - Tracking what registers are being defined and used by
/// instructions in the IT block. This also tracks "dependencies", i.e. uses
ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
-} // namespace llvm
+}
#endif
std::function<bool(const Function &)> PredicateFtor;
};
char Thumb2SizeReduce::ID = 0;
-} // namespace
+}
Thumb2SizeReduce::Thumb2SizeReduce(std::function<bool(const Function &)> Ftor)
: MachineFunctionPass(ID), PredicateFtor(Ftor) {
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = nullptr) const override;
};
-} // namespace llvm
+}
#endif
const char *Modifier = nullptr);
void EmitInstruction(const MachineInstr *MI) override;
};
-} // namespace
+}
void BPFAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
raw_ostream &O, const char *Modifier) {
MBB.erase(MI);
}
};
-} // namespace llvm
+}
#endif
// Complex Pattern for address selection.
bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset);
};
-} // namespace
+}
// ComplexPattern used on BPF Load/Store instructions
bool BPFDAGToDAGISel::SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) {
};
int DiagnosticInfoUnsupported::KindID = 0;
-} // namespace
+}
BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
const BPFSubtarget &STI)
return true;
}
};
-} // namespace llvm
+}
#endif
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
DebugLoc DL) const override;
};
-} // namespace llvm
+}
#endif
MCSymbol *GetGlobalAddressSymbol(const MachineOperand &MO) const;
};
-} // namespace llvm
+}
#endif
unsigned getFrameRegister(const MachineFunction &MF) const override;
};
-} // namespace llvm
+}
#endif
return &InstrInfo.getRegisterInfo();
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
bool addInstSelector() override;
};
-} // namespace
+}
TargetPassConfig *BPFTargetMachine::createPassConfig(PassManagerBase &PM) {
return new BPFPassConfig(this, PM);
return TLOF.get();
}
};
-} // namespace llvm
+}
#endif
void printInstruction(const MCInst *MI, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);
};
-} // namespace llvm
+}
#endif
MCObjectWriter *BPFAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
return createBPFELFObjectWriter(OS, 0, IsLittleEndian);
}
-} // namespace
+}
MCAsmBackend *llvm::createBPFAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
bool IsPCRel) const override;
};
-} // namespace
+}
BPFELFObjectWriter::BPFELFObjectWriter(uint8_t OSABI)
: MCELFObjectTargetWriter(/*Is64Bit*/ true, OSABI, ELF::EM_NONE,
HasDotTypeDotSizeDirective = false;
}
};
-} // namespace llvm
+}
#endif
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;
};
-} // namespace
+}
MCCodeEmitter *llvm::createBPFMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCObjectWriter *createBPFELFObjectWriter(raw_pwrite_stream &OS,
uint8_t OSABI, bool IsLittleEndian);
-} // namespace llvm
+}
// Defines symbolic names for BPF registers. This defines a mapping from
// register name to register number.
extern Target TheCppBackendTarget;
-} // namespace llvm
+} // End llvm namespace
#endif
raw_ostream &VStream,
raw_ostream &CStream) const override;
};
-} // namespace
+}
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
/// \brief Creates a Hexagon-specific Target Transformation Info pass.
ImmutablePass *createHexagonTargetTransformInfoPass(const HexagonTargetMachine *TM);
-} // namespace llvm
+} // end namespace llvm;
#endif
static const char *getRegisterName(unsigned RegNo);
};
-} // namespace llvm
+} // end of llvm namespace
#endif
}
return true;
}
-} // namespace
+}
//===----------------------------------------------------------------------===//
bool coalesceRegisters(RegisterRef R1, RegisterRef R2);
bool coalesceSegments(MachineFunction &MF);
};
-} // namespace
+}
char HexagonExpandCondsets::ID = 0;
return true;
}
-} // namespace
+}
//===----------------------------------------------------------------------===//
// Public Constructor Functions
};
char HexagonFixupHwLoops::ID = 0;
-} // namespace
+}
INITIALIZE_PASS(HexagonFixupHwLoops, "hwloopsfixup",
"Hexagon Hardware Loops Fixup", false, false)
return true;
return false;
}
-} // namespace
+}
/// Implements shrink-wrapping of the stack frame. By default, stack frame
bool useRestoreFunction(MachineFunction &MF, const CSIVect &CSI) const;
};
-} // namespace llvm
+} // End llvm namespace
#endif
unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
};
-} // namespace
+}
// Implement calling convention for Hexagon.
static bool
OP_END
};
- } // namespace HexagonISD
+ }
class HexagonSubtarget;
};
-} // namespace llvm
+}
#endif
void setStackAlignBaseVReg(unsigned R) { StackAlignBaseReg = R; }
unsigned getStackAlignBaseVReg() const { return StackAlignBaseReg; }
};
-} // namespace llvm
+} // End llvm namespace
#endif
#endif
};
-} // namespace llvm
+} // namespace
#endif
private:
void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src);
};
-} // namespace
+}
char HexagonPeephole::ID = 0;
FunctionPass::getAnalysisUsage(AU);
}
};
-} // namespace
+}
char HexagonRemoveExtendArgs::ID = 0;
MachinePointerInfo SrcPtrInfo) const override;
};
-} // namespace llvm
+}
#endif
return true;
}
-} // namespace
+}
//===----------------------------------------------------------------------===//
// Public Constructor Functions
FunctionPass *createHexagonCopyToCombine();
FunctionPass *createHexagonPacketizer();
FunctionPass *createHexagonNewValueJump();
-} // namespace llvm
+} // end namespace llvm;
/// HexagonTargetMachine ctor - Create an ILP32 architecture model.
///
unsigned ByteAlign,
unsigned AccessGranularity){};
};
-} // namespace llvm
+}
#endif
void reserveResourcesForConstExt(MachineInstr* MI);
bool isNewValueInst(MachineInstr* MI);
};
-} // namespace
+}
INITIALIZE_PASS_BEGIN(HexagonPacketizer, "packets", "Hexagon Packetizer",
false, false)
unsigned GetRelocType(MCValue const &Target, MCFixup const &Fixup,
bool IsPCRel) const override;
};
-} // namespace
+}
HexagonELFObjectWriter::HexagonELFObjectWriter(uint8_t OSABI, StringRef C)
: MCELFObjectTargetWriter(/*Is64bit*/ false, OSABI, ELF::EM_HEXAGON,
return false;
}
}
-} // namespace
+}
unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
const MCOperand &MO,
return HexagonII::HCG_None;
}
-} // namespace
+}
/// getCompoundOp - Return the index from 0-7 into the above opcode lists.
namespace {
return (PredReg == Hexagon::P0) ? tp0_jump_t : tp1_jump_t;
}
}
-} // namespace
+}
namespace {
MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, MCInst const &R) {
return CompoundInsn;
}
-} // namespace
+}
/// Non-Symmetrical. See if these two instructions are fit for compound pair.
namespace {
return ((MIaG == HexagonII::HCG_A && MIbG == HexagonII::HCG_B) &&
(MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg()));
}
-} // namespace
+}
namespace {
bool lookForCompound(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI) {
}
return false;
}
-} // namespace
+}
/// tryCompound - Given a bundle check for compound insns when one
/// is found update the contents fo the bundle with the compound insn.
MCOperand &Operand = MCI.getOperand(0);
Operand.setImm(Operand.getImm() | outerLoopMask);
}
-} // namespace llvm
+}
// Attempt to find and replace compound pairs
void tryCompound(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI);
-} // namespace HexagonMCInstrInfo
-} // namespace llvm
+}
+}
#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
unsigned HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
MCContext &Context, MCInst &,
SmallVector<DuplexCandidate, 8>);
-} // namespace llvm
+}
#endif // HEXAGONMCSHUFFLER_H
OS << "\n\t}" << PacketBundle.second;
}
};
-} // namespace
+}
namespace {
class HexagonTargetELFStreamer : public HexagonTargetStreamer {
Symbol, Size, ByteAlignment, AccessSize);
}
};
-} // namespace
+}
static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
const Triple &TT) {
MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS,
uint8_t OSABI, StringRef CPU);
-} // namespace llvm
+} // End llvm namespace
// Define symbolic names for Hexagon registers. This defines a mapping from
// register name to register number.
void setError(unsigned Err) { Error = Err; };
unsigned getError() const { return (Error); };
};
-} // namespace llvm
+}
#endif // HEXAGONSHUFFLER_H
void printCCOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
};
-} // namespace llvm
+}
#endif
COND_INVALID = -1
};
-} // namespace MSP430CC
+}
namespace llvm {
class MSP430TargetMachine;
FunctionPass *createMSP430BranchSelectionPass();
-} // namespace llvm
+} // end namespace llvm;
#endif
}
};
char MSP430BSel::ID = 0;
-} // namespace
+}
/// createMSP430BranchSelectionPass - returns an instance of the Branch
/// Selection Pass
RegScavenger *RS = nullptr) const override;
};
-} // namespace llvm
+} // End llvm namespace
#endif
errs() << " JT" << JT << " Align" << Align << '\n';
}
};
-} // namespace
+}
/// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
/// instructions for SelectionDAG operations.
/// SHL, SRA, SRL - Non-constant shifts.
SHL, SRA, SRL
};
- } // namespace MSP430ISD
+ }
class MSP430Subtarget;
class MSP430TargetLowering : public TargetLowering {
Size4Bytes = 3 << SizeShift,
Size6Bytes = 4 << SizeShift
};
-} // namespace MSP430II
+}
class MSP430InstrInfo : public MSP430GenInstrInfo {
const MSP430RegisterInfo RI;
};
-} // namespace llvm
+}
#endif
MCSymbol *GetBlockAddressSymbol(const MachineOperand &MO) const;
};
-} // namespace llvm
+}
#endif
void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
};
-} // namespace llvm
+} // End llvm namespace
#endif
~MSP430SelectionDAGInfo();
};
-} // namespace llvm
+}
#endif
return &TSInfo;
}
};
-} // namespace llvm
+} // End llvm namespace
#endif // LLVM_TARGET_MSP430_SUBTARGET_H
OS.EmitIntValue(ABIFlagsSection.getFlags2Value(), 4); // flags2
return OS;
}
-} // namespace llvm
+}
};
MCStreamer &operator<<(MCStreamer &OS, MipsABIFlagsSection &ABIFlagsSection);
-} // namespace llvm
+}
#endif
unsigned GetEhDataReg(unsigned I) const;
};
-} // namespace llvm
+}
#endif
}; // class MipsAsmBackend
-} // namespace llvm
+} // namespace
#endif
FormMask = 15
};
-} // namespace MipsII
-} // namespace llvm
+}
+}
#endif
virtual void sortRelocs(const MCAssembler &Asm,
std::vector<ELFRelocationEntry> &Relocs) override;
};
-} // namespace
+}
MipsELFObjectWriter::MipsELFObjectWriter(bool _is64Bit, uint8_t OSABI,
bool _isN64, bool IsLittleEndian)
MCELFStreamer *createMipsNaClELFStreamer(MCContext &Context, MCAsmBackend &TAB,
raw_pwrite_stream &OS,
MCCodeEmitter *Emitter, bool RelaxAll);
-} // namespace llvm
+}
#endif
StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
}
-} // namespace llvm
+} // End llvm namespace
// Defines symbolic names for Mips registers. This defines a mapping from
// register name to register number.
return S;
}
-} // namespace llvm
+}
FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
FunctionPass *createMipsLongBranchPass(MipsTargetMachine &TM);
FunctionPass *createMipsConstantIslandPass(MipsTargetMachine &tm);
-} // namespace llvm
+} // end namespace llvm;
#endif
RegScavenger *RS) const override;
};
-} // namespace llvm
+} // End llvm namespace
#endif
};
char Mips16HardFloat::ID = 0;
-} // namespace
+}
//
// Return types that matter for hard float are:
}
return nullptr;
}
-} // namespace Mips16HardFloatInfo
-} // namespace llvm
+}
+}
extern const FuncNameSignature PredefinedFuncs[];
extern FuncSignature const *findFuncSignature(const char *name);
-} // namespace Mips16HardFloatInfo
-} // namespace llvm
+}
+}
#endif
FunctionPass *createMips16ISelDag(MipsTargetMachine &TM);
-} // namespace llvm
+}
#endif
return std::strcmp(Name, RHS.Name) == 0;
}
};
-} // namespace
+}
// Libcalls for which no helper is generated. Sorted by name for binary search.
static const Mips16Libcall HardFloatLibCalls[] = {
unsigned SltiOpc, unsigned SltiXOpc,
MachineInstr *MI, MachineBasicBlock *BB )const;
};
-} // namespace llvm
+}
#endif
};
-} // namespace llvm
+}
#endif
unsigned ADDiu, ORi, SLL, LUi;
InstSeq Insts;
};
-} // namespace llvm
+}
#endif
void EmitEndOfAsmFile(Module &M) override;
void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
};
-} // namespace llvm
+}
#endif
bool IsCallOperandFixed(unsigned ValNo) { return CallOperandIsFixed[ValNo]; }
SpecialCallingConvType getSpecialCallingConv() { return SpecialCallingConv; }
};
-} // namespace llvm
+}
#endif
const MipsFrameLowering *createMips16FrameLowering(const MipsSubtarget &ST);
const MipsFrameLowering *createMipsSEFrameLowering(const MipsSubtarget &ST);
-} // namespace llvm
+} // End llvm namespace
#endif
unsigned ConstraintID,
std::vector<SDValue> &OutOps) override;
};
-} // namespace llvm
+}
#endif
SDL,
SDR
};
- } // namespace MipsISD
+ }
//===--------------------------------------------------------------------===//
// TargetLowering Implementation
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
const TargetLibraryInfo *libInfo);
}
-} // namespace llvm
+}
#endif
const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI);
const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI);
-} // namespace llvm
+}
#endif
MCSymbolRefExpr::VariantKind Kind) const;
bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
};
-} // namespace llvm
+}
#endif
};
char MipsModuleDAGToDAGISel::ID = 0;
-} // namespace
+}
bool MipsModuleDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
DEBUG(errs() << "In MipsModuleDAGToDAGISel::runMachineFunction\n");
};
char MipsOs16::ID = 0;
-} // namespace
+}
// Figure out if we need float point based on the function signature.
// We need to move variables in and/or out of floating point
const MipsSEInstrInfo &TII;
const MipsRegisterInfo &RegInfo;
};
-} // namespace
+}
ExpandPseudo::ExpandPseudo(MachineFunction &MF_)
: MF(MF_), MRI(MF.getRegInfo()),
unsigned ehDataReg(unsigned I) const;
};
-} // namespace llvm
+} // End llvm namespace
#endif
FunctionPass *createMipsSEISelDag(MipsTargetMachine &TM);
-} // namespace llvm
+}
#endif
MachineBasicBlock *emitFEXP2_D_1(MachineInstr *MI,
MachineBasicBlock *BB) const;
};
-} // namespace llvm
+}
#endif
MachineBasicBlock::iterator I) const;
};
-} // namespace llvm
+}
#endif
~MipsSelectionDAGInfo();
};
-} // namespace llvm
+}
#endif
return &InstrItins;
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
CodeGenOpt::Level OL);
};
-} // namespace llvm
+} // End llvm namespace
#endif
void emitDirectiveModuleOddSPReg(bool Enabled, bool IsO32ABI) override;
void emitMipsAbiFlags();
};
-} // namespace llvm
+}
#endif
raw_ostream &O, const char *Modifier = nullptr);
};
-} // namespace llvm
+}
#endif
IsSurfTexQueryFlag = 0x800,
IsTexModeUnifiedFlag = 0x1000
};
-} // namespace NVPTXII
-} // namespace llvm
+}
+}
#endif
}
};
-} // namespace llvm
+}
#endif
V2 = 2,
V4 = 4
};
-} // namespace PTXLdStInstCode
+}
/// PTXCvtMode - Conversion code enumeration
namespace PTXCvtMode {
FTZ_FLAG = 0x10,
SAT_FLAG = 0x20
};
-} // namespace PTXCvtMode
+}
/// PTXCmpMode - Comparison mode enumeration
namespace PTXCmpMode {
BASE_MASK = 0xFF,
FTZ_FLAG = 0x100
};
-} // namespace PTXCmpMode
-} // namespace NVPTX
-} // namespace llvm
+}
+}
+} // end namespace llvm;
// Defines symbolic names for NVPTX registers. This defines a mapping from
// register name to register number.
Visited.insert(GV);
Visiting.erase(GV);
}
-} // namespace
+}
void NVPTXAsmPrinter::emitLineNumberAsDotLoc(const MachineInstr &MI) {
if (!EmitLineNumbers)
DebugLoc prevDebugLoc;
void emitLineNumberAsDotLoc(const MachineInstr &);
};
-} // namespace llvm
+} // end of namespace
#endif
/// \brief Clean up the name to remove symbols invalid in PTX.
std::string cleanUpName(StringRef Name);
};
-} // namespace
+}
char NVPTXAssignValidGlobalNames::ID = 0;
/// Helper function for bitcasts.
Value *hoistAddrSpaceCastFromBitCast(BitCastOperator *BC, int Depth);
};
-} // namespace
+}
char NVPTXFavorNonGenericAddrSpaces::ID = 0;
MachineBasicBlock::iterator I) const override;
};
-} // namespace llvm
+} // End llvm namespace
#endif
bool ChkMemSDNodeAddressSpace(SDNode *N, unsigned int spN) const;
};
-} // namespace
+}
#endif
Suld3DV4I16Zero,
Suld3DV4I32Zero
};
-} // namespace NVPTXISD
+}
class NVPTXSubtarget;
Value *cleanupValue(Value *V);
void replaceWith(Instruction *From, ConstantInt *To);
};
-} // namespace
+}
char NVPTXImageOptimizer::ID = 0;
return ImageHandleList[Idx].c_str();
}
};
-} // namespace llvm
+}
#endif
private:
void calculateFrameObjectOffsets(MachineFunction &Fn);
};
-} // namespace
+}
MachineFunctionPass *llvm::createNVPTXPrologEpilogPass() {
return new NVPTXPrologEpilogPass();
}
return "";
}
-} // namespace llvm
+}
NVPTXRegisterInfo::NVPTXRegisterInfo() : NVPTXGenRegisterInfo(0) {}
bool findIndexForHandle(MachineOperand &Op, MachineFunction &MF,
unsigned &Idx);
};
-} // namespace
+}
char NVPTXReplaceImageHandles::ID = 0;
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
};
-} // namespace llvm
+} // End llvm namespace
#endif
void dumpInstRec(Value *v);
void dumpParent(Value *v);
-} // namespace llvm
+}
#endif
bool handleFunction(Function *ReflectFunction);
void setVarMap();
};
-} // namespace
+}
ModulePass *llvm::createNVVMReflectPass() {
return new NVVMReflect();
bool needsRelocateWithSymbol(const MCSymbol &Sym,
unsigned Type) const override;
};
-} // namespace
+}
PPCELFObjectWriter::PPCELFObjectWriter(bool Is64Bit, uint8_t OSABI)
: MCELFObjectTargetWriter(Is64Bit, OSABI,
LastTargetFixupKind,
NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
};
-} // namespace PPC
-} // namespace llvm
+}
+}
#endif
llvm_unreachable("Unknown pseudo-op: .localentry");
}
};
-} // namespace
+}
static MCTargetStreamer *createAsmTargetStreamer(MCStreamer &S,
formatted_raw_ostream &OS,
return false;
}
-} // namespace llvm
+} // End llvm namespace
// Generated files will use "namespace PPC". To avoid symbol clash,
// undefine PPC here. PPC may be predefined on some hosts.
FixedValue);
}
};
-} // namespace
+}
/// computes the log2 of the size of the relocation,
/// used for relocation_info::r_length.
/// Assume the condition register is set by MI(a,b), return the predicate if
/// we modify the instructions such that condition register is set by MI(b,a).
Predicate getSwappedPredicate(Predicate Opcode);
-} // namespace PPC
-} // namespace llvm
+}
+}
#endif
};
} // end namespace PPCII
-} // namespace llvm
+} // end namespace llvm;
#endif
}
};
char PPCBSel::ID = 0;
-} // namespace
+}
INITIALIZE_PASS(PPCBSel, "ppc-branch-select", "PowerPC Branch Selector",
false, false)
return false;
}
-} // namespace llvm
+} // End llvm namespace
#endif
MachineFunctionPass::getAnalysisUsage(AU);
}
};
-} // namespace
+}
INITIALIZE_PASS(PPCEarlyReturn, DEBUG_TYPE,
"PowerPC Early-Return Creation", false, false)
return new PPCFastISel(FuncInfo, LibInfo);
return nullptr;
}
-} // namespace llvm
+}
const SpillSlot *
getCalleeSavedSpillSlots(unsigned &NumEntries) const override;
};
-} // namespace llvm
+} // End llvm namespace
#endif
SDNode *transferMemOperands(SDNode *N, SDNode *Result);
};
-} // namespace
+}
/// InsertVRSaveCode - Once the entire function has been instruction selected,
/// all virtual registers are created and all machine instructions are built,
TailCallArgumentInfo() : FrameIdx(0) {}
};
-} // namespace
+}
/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
static void
/// the last operand.
TOC_ENTRY
};
- } // namespace PPCISD
+ }
/// Define some predicates that are used for node matching.
namespace PPC {
/// If this is a qvaligni shuffle mask, return the shift
/// amount, otherwise return -1.
int isQVALIGNIShuffleMask(SDNode *N);
- } // namespace PPC
+ }
class PPCTargetLowering : public TargetLowering {
const PPCSubtarget &Subtarget;
CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags,
CCState &State);
-} // namespace llvm
+}
#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
return MIB.addFrameIndex(FI).addImm(Offset);
}
-} // namespace llvm
+} // End llvm namespace
#endif
void getNoopForMachoTarget(MCInst &NopInst) const override;
};
-} // namespace llvm
+}
#endif
const TargetTransformInfo *TTI;
const DataLayout *DL;
};
-} // namespace
+}
char PPCLoopDataPrefetch::ID = 0;
INITIALIZE_PASS_BEGIN(PPCLoopDataPrefetch, "ppc-loop-data-prefetch",
LoopInfo *LI;
ScalarEvolution *SE;
};
-} // namespace
+}
char PPCLoopPreIncPrep::ID = 0;
static const char *name = "Prepare loop for pre-inc. addressing modes";
protected:
ScalarEvolution *SE;
};
-} // namespace
+}
static bool IsPtrInBounds(Value *BasePtr) {
Value *StrippedBasePtr = BasePtr;
~PPCSelectionDAGInfo();
};
-} // namespace llvm
+}
#endif
DIR_PWR8,
DIR_64
};
-} // namespace PPC
+}
class GlobalValue;
class TargetMachine;
bool enableSubRegLiveness() const override;
};
-} // namespace llvm
+} // End llvm namespace
#endif
MachineFunctionPass::getAnalysisUsage(AU);
}
};
-} // namespace
+}
INITIALIZE_PASS_BEGIN(PPCTLSDynamicCall, DEBUG_TYPE,
"PowerPC TLS Dynamic Call Fixup", false, false)
MachineFunctionPass::getAnalysisUsage(AU);
}
};
-} // namespace
+}
INITIALIZE_PASS(PPCTOCRegDeps, DEBUG_TYPE,
"PowerPC TOC Register Dependencies", false, false)
virtual void emitAbiVersion(int AbiVersion) = 0;
virtual void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset) = 0;
};
-} // namespace llvm
+}
#endif
MachineFunctionPass::getAnalysisUsage(AU);
}
};
-} // namespace
+}
INITIALIZE_PASS(PPCVSXCopy, DEBUG_TYPE,
"PowerPC VSX Copy Legalization", false, false)
MachineFunctionPass::getAnalysisUsage(AU);
}
};
-} // namespace
+}
INITIALIZE_PASS_BEGIN(PPCVSXFMAMutate, DEBUG_TYPE,
"PowerPC VSX FMA Mutation", false, false)
DEBUG(dbgs() << "\n");
}
-} // namespace
+} // end default namespace
INITIALIZE_PASS_BEGIN(PPCVSXSwapRemoval, DEBUG_TYPE,
"PowerPC VSX Swap Removal", false, false)
raw_ostream &VStream,
raw_ostream &CStream) const override;
};
-} // namespace
+}
namespace llvm {
extern Target TheSparcTarget, TheSparcV9Target, TheSparcelTarget;
unsigned Type) const override;
};
-} // namespace
+}
unsigned SparcELFObjectWriter::GetRelocType(const MCValue &Target,
const MCFixup &Fixup,
LastTargetFixupKind,
NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
};
- } // namespace Sparc
-} // namespace llvm
+ }
+}
#endif
const Triple &TT, StringRef CPU);
MCObjectWriter *createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
bool IsLIttleEndian, uint8_t OSABI);
-} // namespace llvm
+} // End llvm namespace
// Defines symbolic names for Sparc registers. This defines a mapping from
// register name to register number.
void LowerSparcMachineInstrToMCInst(const MachineInstr *MI,
MCInst &OutMI,
AsmPrinter &AP);
-} // namespace llvm
+} // end namespace llvm;
namespace llvm {
// Enums corresponding to Sparc condition codes, both icc's and fcc's. These
FCC_ULE = 14+16, // Unordered or Less or Equal
FCC_O = 15+16 // Ordered
};
- } // namespace SPCC
+ }
inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) {
switch (CC) {
};
-} // namespace llvm
+} // End llvm namespace
#endif
TLS_LD,
TLS_CALL
};
- } // namespace SPISD
+ }
class SparcTargetLowering : public TargetLowering {
const SparcSubtarget *Subtarget;
unsigned getGlobalBaseReg(MachineFunction *MF) const;
};
-} // namespace llvm
+}
#endif
void setLeafProc(bool rhs) { IsLeafProc = rhs; }
bool isLeafProc() const { return IsLeafProc; }
};
-} // namespace llvm
+}
#endif
~SparcSelectionDAGInfo() override;
};
-} // namespace llvm
+}
#endif
unsigned Operand;
unsigned char Bytes[SystemZ::VectorBytes];
};
-} // namespace
+}
static const Permute PermuteForms[] = {
// VMRHG
// The type of the shuffle result.
EVT VT;
};
-} // namespace
+}
// Add an extra undefined element to the shuffle.
void GeneralShuffle::addUndef() {
return new X86AsmInstrumentation(STI);
}
-} // namespace llvm
+} // End llvm namespace
unsigned InitialFrameReg;
};
-} // namespace llvm
+} // End llvm namespace
#endif
extern Target TheX86_32Target, TheX86_64Target;
-} // namespace llvm
+}
static bool translateInstruction(MCInst &target,
InternalInstruction &source,
private:
bool HasCustomInstComment;
};
-} // namespace llvm
+}
#endif
}
};
-} // namespace llvm
+}
#endif
UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
};
-} // namespace CU
+} // end CU namespace
class DarwinX86AsmBackend : public X86AsmBackend {
const MCRegisterInfo &MRI;
/// AddrNumOperands - Total number of operands in a memory reference.
AddrNumOperands = 5
};
-} // namespace X86
+} // end namespace X86;
/// X86II - This namespace holds all of the target specific flags that
/// instruction info tracks.
return (reg == X86::SPL || reg == X86::BPL ||
reg == X86::SIL || reg == X86::DIL);
}
-} // namespace X86II
+}
-} // namespace llvm
+} // end namespace llvm;
#endif
unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
bool IsPCRel) const override;
};
-} // namespace
+}
X86ELFObjectWriter::X86ELFObjectWriter(bool IsELF64, uint8_t OSABI,
uint16_t EMachine)
LastTargetFixupKind,
NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
};
-} // namespace X86
-} // namespace llvm
+}
+}
#endif
/// do not need to go through TargetRegistry.
MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU,
StringRef FS);
-} // namespace X86_MC
+}
MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
/// Construct X86-64 ELF relocation info.
MCRelocationInfo *createX86_64ELFRelocationInfo(MCContext &Ctx);
-} // namespace llvm
+} // End llvm namespace
// Defines symbolic names for X86 registers. This defines a mapping from
FixedValue);
}
};
-} // namespace
+}
static bool isFixupKindRIPRel(unsigned Kind) {
return Kind == X86::reloc_riprel_4byte ||
bool IsCrossSection,
const MCAsmBackend &MAB) const override;
};
-} // namespace
+}
X86WinCOFFObjectWriter::X86WinCOFFObjectWriter(bool Is64Bit)
: MCWinCOFFObjectTargetWriter(Is64Bit ? COFF::IMAGE_FILE_MACHINE_AMD64
MCWinCOFFStreamer::FinishImpl();
}
-} // namespace
+}
MCStreamer *llvm::createX86WinCOFFStreamer(MCContext &C, MCAsmBackend &AB,
raw_pwrite_stream &OS,
for (unsigned i = 1; i < NumElts; i++)
Mask.push_back(IsLoad ? static_cast<int>(SM_SentinelZero) : i);
}
-} // namespace llvm
+} // llvm namespace
/// \brief Decode a scalar float move instruction as a shuffle mask.
void DecodeScalarMoveMask(MVT VT, bool IsLoad,
SmallVectorImpl<int> &ShuffleMask);
-} // namespace llvm
+} // llvm namespace
#endif
/// must run after prologue/epilogue insertion and before lowering
/// the MachineInstr to MC.
FunctionPass *createX86ExpandPseudoPass();
-} // namespace llvm
+} // End llvm namespace
#endif
};
char X86CallFrameOptimization::ID = 0;
-} // namespace
+}
FunctionPass *llvm::createX86CallFrameOptimization() {
return new X86CallFrameOptimization();
return false;
}
-} // namespace llvm
+} // End llvm namespace
#endif
const X86InstrInfo *TII; // Machine instruction info.
};
char FixupLEAPass::ID = 0;
-} // namespace
+}
MachineInstr *
FixupLEAPass::postRAConvertToLEA(MachineFunction::iterator &MFI,
void setKillFlags(MachineBasicBlock &MBB) const;
};
char FPS::ID = 0;
-} // namespace
+}
FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
return V < TE.from;
}
};
-} // namespace
+}
#ifndef NDEBUG
static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
bool InEpilogue) const;
};
-} // namespace llvm
+} // End llvm namespace
#endif
}
#endif
};
-} // namespace
+}
namespace {
//===--------------------------------------------------------------------===//
return true;
}
};
-} // namespace
+}
bool
// have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
// thought as target memory ops!
};
- } // namespace X86ISD
+ }
/// Define some predicates that are used for node matching.
namespace X86 {
TO_ZERO = 3,
CUR_DIRECTION = 4
};
- } // namespace X86
+ }
//===--------------------------------------------------------------------===//
// X86 Implementation of the TargetLowering interface
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
const TargetLibraryInfo *libInfo);
}
-} // namespace llvm
+}
#endif // X86ISELLOWERING_H
.addConstantPoolIndex(CPI, 0, OpFlags).addReg(0);
}
-} // namespace llvm
+} // End llvm namespace
#endif
MachineFunctionPass::getAnalysisUsage(AU);
}
};
-} // namespace
+}
char CGBR::ID = 0;
FunctionPass*
MachineFunctionPass::getAnalysisUsage(AU);
}
};
-} // namespace
+}
char LDTLSCleanup::ID = 0;
FunctionPass*
/// GetOppositeBranchCondition - Return the inverse of the specified cond,
/// e.g. turning COND_E to COND_NE.
CondCode GetOppositeBranchCondition(CondCode CC);
-} // namespace X86
+} // end namespace X86;
/// isGlobalStubReference - Return true if the specified TargetFlag operand is
int &FrameIndex) const;
};
-} // namespace llvm
+} // End llvm namespace
#endif
OutStreamer->EmitInstruction(Inst, getSubtargetInfo());
SMShadowTracker.count(Inst, getSubtargetInfo());
}
-} // namespace llvm
+} // end llvm namespace
X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
X86AsmPrinter &asmprinter)
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
};
char PadShortFunc::ID = 0;
-} // namespace
+}
FunctionPass *llvm::createX86PadShortFunctions() {
return new PadShortFunc();
llvm_unreachable("Unexpected SIMD register");
}
-} // namespace llvm
+}
//get512BitRegister - X86 utility - returns 512-bit super register
unsigned get512BitSuperRegister(unsigned Reg);
-} // namespace llvm
+} // End llvm namespace
#endif
MachinePointerInfo SrcPtrInfo) const override;
};
-} // namespace llvm
+}
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
};
char VZeroUpperInserter::ID = 0;
-} // namespace
+}
FunctionPass *llvm::createX86IssueVZeroUpperPass() {
return new VZeroUpperInserter();
/// The linked list node subobject inside of RegNode.
Value *Link = nullptr;
};
-} // namespace
+}
FunctionPass *llvm::createX86WinEHStatePass() { return new WinEHStatePass(); }
raw_ostream &VStream,
raw_ostream &CStream) const override;
};
-} // namespace
+}
static bool readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
uint64_t &Size, uint16_t &Insn) {
void XCoreTargetAsmStreamer::emitCCBottomFunction(StringRef Name) {
OS << "\t.cc_bottom " << Name << ".function\n";
}
-} // namespace
+}
static MCTargetStreamer *createTargetAsmStreamer(MCStreamer &S,
formatted_raw_ostream &OS,
CodeGenOpt::Level OptLevel);
ModulePass *createXCoreLowerThreadLocalPass();
-} // namespace llvm
+} // end namespace llvm;
#endif
return 4;
}
};
-} // namespace llvm
+}
#endif
}
};
char XCoreFTAOElim::ID = 0;
-} // namespace
+}
/// createXCoreFrameToArgsOffsetEliminationPass - returns an instance of the
/// Frame to args offset elimination pass
// Memory barrier.
MEMBARRIER
};
- } // namespace XCoreISD
+ }
//===--------------------------------------------------------------------===//
// TargetLowering Implementation
const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
LLVMContext &Context) const override;
};
-} // namespace llvm
+}
#endif
COND_INVALID
};
}
-} // namespace llvm
+}
// Pin the vtable to this file.
void XCoreInstrInfo::anchor() {}
unsigned Reg, uint64_t Value) const;
};
-} // namespace llvm
+}
#endif
bool runOnModule(Module &M) override;
};
-} // namespace
+}
char XCoreLowerThreadLocal::ID = 0;
MCOperand LowerSymbolOperand(const MachineOperand &MO,
MachineOperandType MOTy, unsigned Offset) const;
};
-} // namespace llvm
+}
#endif
return SpillLabels;
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
MachinePointerInfo SrcPtrInfo) const override;
};
-} // namespace llvm
+}
#endif
return &InstrInfo.getRegisterInfo();
}
};
-} // namespace llvm
+} // End llvm namespace
#endif
virtual void emitCCBottomData(StringRef Name) = 0;
virtual void emitCCBottomFunction(StringRef Name) = 0;
};
-} // namespace llvm
+}
#endif
return false;
}
};
-} // namespace
+}
char Hello::ID = 0;
static RegisterPass<Hello> X("hello", "Hello World Pass");
AU.setPreservesAll();
}
};
-} // namespace
+}
char Hello2::ID = 0;
static RegisterPass<Hello2>
unsigned maxElements;
DenseMap<const Function *, DISubprogram *> FunctionDIs;
};
-} // namespace
+}
char ArgPromotion::ID = 0;
INITIALIZE_PASS_BEGIN(ArgPromotion, "argpromotion",
bool runOnModule(Module &M) override { return false; }
};
-} // namespace
+}
ModulePass *llvm::createBarrierNoopPass() { return new BarrierNoop(); }
unsigned getAlignment(GlobalVariable *GV) const;
};
-} // namespace
+}
char ConstantMerge::ID = 0;
INITIALIZE_PASS(ConstantMerge, "constmerge",
bool DeleteDeadVarargs(Function &Fn);
bool RemoveDeadArgumentsFromCallers(Function &Fn);
};
-} // namespace
+}
char DAE::ID = 0;
bool ShouldHackArguments() const override { return true; }
};
-} // namespace
+}
char DAH::ID = 0;
INITIALIZE_PASS(DAH, "deadarghaX0r",
};
char GVExtractorPass::ID = 0;
-} // namespace
+}
ModulePass *llvm::createGVExtractionPass(std::vector<GlobalValue *> &GVs,
bool deleteFn) {
AliasAnalysis *AA;
TargetLibraryInfo *TLI;
};
-} // namespace
+}
char FunctionAttrs::ID = 0;
INITIALIZE_PASS_BEGIN(FunctionAttrs, "functionattrs",
const SmallPtrSet<Function*, 8> &SCCNodes;
};
-} // namespace
+}
namespace llvm {
template<> struct GraphTraits<ArgumentGraphNode*> {
return AG->end();
}
};
-} // namespace llvm
+}
// Returns Attribute::None, Attribute::ReadOnly or Attribute::ReadNone.
static Attribute::AttrKind
bool RemoveUnusedGlobalValue(GlobalValue &GV);
};
-} // namespace
+}
/// Returns true if F contains only a single "ret" instruction.
static bool isEmptyFunction(Function *F) {
TargetLibraryInfo *TLI;
SmallSet<const Comdat *, 8> NotDiscardableComdats;
};
-} // namespace
+}
char GlobalOpt::ID = 0;
INITIALIZE_PASS_BEGIN(GlobalOpt, "globalopt",
setUsedInitializer(*CompilerUsedV, CompilerUsed);
}
};
-} // namespace
+}
static bool hasUseOtherThanLLVMUsed(GlobalAlias &GA, const LLVMUsed &U) {
if (GA.use_empty()) // No use at all.
bool PropagateConstantsIntoArguments(Function &F);
bool PropagateConstantReturn(Function &F);
};
-} // namespace
+}
char IPCP::ID = 0;
INITIALIZE_PASS(IPCP, "ipconstprop",
}
};
-} // namespace
+}
char AlwaysInliner::ID = 0;
INITIALIZE_PASS_BEGIN(AlwaysInliner, "always-inline",
AU.addRequired<DominatorTreeWrapperPass>();
}
};
-} // namespace
+}
char LoopExtractor::ID = 0;
INITIALIZE_PASS_BEGIN(LoopExtractor, "loop-extract",
bool runOnModule(Module &M) override;
};
-} // namespace
+}
char BlockExtractorPass::ID = 0;
INITIALIZE_PASS(BlockExtractorPass, "extract-blocks",
return (FunctionComparator(F, RHS.getFunc()).compare()) == -1;
}
};
-} // namespace
+}
int FunctionComparator::cmpNumbers(uint64_t L, uint64_t R) const {
if (L < R) return -1;
private:
Function* unswitchFunction(Function* F);
};
-} // namespace
+}
char PartialInliner::ID = 0;
INITIALIZE_PASS(PartialInliner, "partial-inliner",
bool SimplifyFunction(Function *F);
void DeleteBasicBlock(BasicBlock *BB);
};
-} // namespace
+}
char PruneEH::ID = 0;
INITIALIZE_PASS_BEGIN(PruneEH, "prune-eh",
AU.setPreservesAll();
}
};
-} // namespace
+}
char StripSymbols::ID = 0;
INITIALIZE_PASS(StripSymbols, "strip",
void incCreateInstNum() {}
#endif
};
-} // namespace
+}
//===----------------------------------------------------------------------===//
//
UDivFoldAction(FoldUDivOperandCb FA, Value *InputOperand, size_t SLHS)
: FoldAction(FA), OperandToFold(InputOperand), SelectLHSIdx(SLHS) {}
};
-} // namespace
+}
// X udiv 2^C -> X >> C
static Instruction *foldUDivPow2Cst(Value *Op0, Value *Op1,
LoweredPHIRecord(PHINode *pn, unsigned Sh)
: PN(pn), Shift(Sh), Width(0) {}
};
-} // namespace
+}
namespace llvm {
template<>
LHS.Width == RHS.Width;
}
};
-} // namespace llvm
+}
/// SliceUpIllegalIntegerPHI - This is an integer PHI and we know that it has an
void getAnalysisUsage(AnalysisUsage &AU) const override;
bool runOnFunction(Function &F) override;
};
-} // namespace
+}
void InstructionCombiningPass::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
void emitBranchToTrap(Value *Cmp = nullptr);
bool instrument(Value *Ptr, Value *Val, const DataLayout &DL);
};
-} // namespace
+}
char BoundsChecking::ID = 0;
INITIALIZE_PASS(BoundsChecking, "bounds-checking", "Run-time bounds checking",
void visitMemTransferInst(MemTransferInst &I);
};
-} // namespace
+}
char DataFlowSanitizer::ID;
INITIALIZE_PASS(DataFlowSanitizer, "dfsan",
LLVMContext *Ctx;
SmallVector<std::unique_ptr<GCOVFunction>, 16> Funcs;
};
-} // namespace
+}
char GCOVProfiler::ID = 0;
INITIALIZE_PASS(GCOVProfiler, "insert-gcov-profiling",
DenseMap<BasicBlock *, GCOVBlock> Blocks;
GCOVBlock ReturnBlock;
};
-} // namespace
+}
std::string GCOVProfiler::mangleName(const DICompileUnit *CU,
const char *NewStem) {
return Map.empty();
}
};
-} // namespace llvm
+} //
initializeObjCARCAPElimPass(*PassRegistry::getPassRegistry());
}
};
-} // namespace
+}
char ObjCARCAPElim::ID = 0;
INITIALIZE_PASS(ObjCARCAPElim,
initializeObjCARCContractPass(*PassRegistry::getPassRegistry());
}
};
-} // namespace
+}
//===----------------------------------------------------------------------===//
// Implementation
initializeObjCARCExpandPass(*PassRegistry::getPassRegistry());
}
};
-} // namespace
+}
char ObjCARCExpand::ID = 0;
INITIALIZE_PASS(ObjCARCExpand,
};
const unsigned BBState::OverflowOccurredValue = 0xffffffff;
-} // namespace
+}
namespace llvm {
raw_ostream &operator<<(raw_ostream &OS,
initializeObjCARCOptPass(*PassRegistry::getPassRegistry());
}
};
-} // namespace
+}
char ObjCARCOpt::ID = 0;
INITIALIZE_PASS_BEGIN(ObjCARCOpt,
AU.setPreservesCFG();
}
};
-} // namespace
+}
char ADCE::ID = 0;
INITIALIZE_PASS(ADCE, "adce", "Aggressive Dead Code Elimination", false, false)
const SCEV *&OffSCEV);
bool processAssumption(CallInst *I);
};
-} // namespace
+}
char AlignmentFromAssumptions::ID = 0;
static const char aip_name[] = "Alignment from assumptions";
AssumptionCache *AC;
DominatorTree *DT;
};
-} // namespace
+}
char BDCE::ID = 0;
INITIALIZE_PASS_BEGIN(BDCE, "bdce", "Bit-Tracking Dead Code Elimination",
void deleteDeadCastInst() const;
bool optimizeConstants(Function &Fn);
};
-} // namespace
+}
char ConstantHoisting::ID = 0;
INITIALIZE_PASS_BEGIN(ConstantHoisting, "consthoist", "Constant Hoisting",
AU.addRequired<TargetLibraryInfoWrapperPass>();
}
};
-} // namespace
+}
char ConstantPropagation::ID = 0;
INITIALIZE_PASS_BEGIN(ConstantPropagation, "constprop",
AU.addRequired<LazyValueInfo>();
}
};
-} // namespace
+}
char CorrelatedValuePropagation::ID = 0;
INITIALIZE_PASS_BEGIN(CorrelatedValuePropagation, "correlated-propagation",
AU.setPreservesCFG();
}
};
-} // namespace
+}
char DeadInstElimination::ID = 0;
INITIALIZE_PASS(DeadInstElimination, "die",
AU.setPreservesCFG();
}
};
-} // namespace
+}
char DCE::ID = 0;
INITIALIZE_PASS(DCE, "dce", "Dead Code Elimination", false, false)
AU.addPreserved<MemoryDependenceAnalysis>();
}
};
-} // namespace
+}
char DSE::ID = 0;
INITIALIZE_PASS_BEGIN(DSE, "dse", "Dead Store Elimination", false, false)
isa<ExtractValueInst>(Inst) || isa<InsertValueInst>(Inst);
}
};
-} // namespace
+}
namespace llvm {
template <> struct DenseMapInfo<SimpleValue> {
static unsigned getHashValue(SimpleValue Val);
static bool isEqual(SimpleValue LHS, SimpleValue RHS);
};
-} // namespace llvm
+}
unsigned DenseMapInfo<SimpleValue>::getHashValue(SimpleValue Val) {
Instruction *Inst = Val.Inst;
return true;
}
};
-} // namespace
+}
namespace llvm {
template <> struct DenseMapInfo<CallValue> {
static unsigned getHashValue(CallValue Val);
static bool isEqual(CallValue LHS, CallValue RHS);
};
-} // namespace llvm
+}
unsigned DenseMapInfo<CallValue>::getHashValue(CallValue Val) {
Instruction *Inst = Val.Inst;
ExpectedType);
}
};
-} // namespace
+}
bool EarlyCSE::processNode(DomTreeNode *Node) {
BasicBlock *BB = Node->getBlock();
AU.setPreservesCFG();
}
};
-} // namespace
+}
char EarlyCSELegacyPass::ID = 0;
private:
AliasAnalysis *AA;
};
-} // namespace
+}
char FlattenCFGPass::ID = 0;
INITIALIZE_PASS_BEGIN(FlattenCFGPass, "flattencfg", "Flatten the CFG", false,
MapVector<Instruction*, Value*> ConvertedInsts;
LLVMContext *Ctx;
};
-} // namespace
+}
char Float2Int::ID = 0;
INITIALIZE_PASS(Float2Int, "float2int", "Float to int", false, false)
uint32_t getNextUnusedValueNumber() { return nextValueNumber; }
void verifyRemoved(const Value *) const;
};
-} // namespace
+}
namespace llvm {
template <> struct DenseMapInfo<Expression> {
}
};
-} // namespace llvm
+}
//===----------------------------------------------------------------------===//
// ValueTable Internal Functions
};
char GVN::ID = 0;
-} // namespace
+}
// The public interface to this file...
FunctionPass *llvm::createGVNPass(bool NoLoads) {
void SinkUnusedInvariants(Loop *L);
};
-} // namespace
+}
char IndVarSimplify::ID = 0;
INITIALIZE_PASS_BEGIN(IndVarSimplify, "indvars",
RewritePhi(PHINode *P, unsigned I, Value *V, bool H, bool S)
: PN(P), Ith(I), Val(V), HighCost(H), SafePhi(S) {}
};
-} // namespace
+}
//===----------------------------------------------------------------------===//
// RewriteLoopExitValues - Optimize IV users outside the loop.
WideIVInfo() : NarrowIV(nullptr), WidestNativeType(nullptr),
IsSigned(false) {}
};
-} // namespace
+}
/// visitCast - Update information about the induction variable that is
/// extended by this sign or zero extend operation. This is used to determine
// Implement the interface used by simplifyUsersOfIV.
void visitCast(CastInst *Cast) override { visitIVCast(Cast, WI, SE, TTI); }
};
-} // namespace
+}
/// SimplifyAndExtend - Iteratively perform simplification on a worklist of IV
/// users. Each successive simplification may push more users which may
};
char InductiveRangeCheckElimination::ID = 0;
-} // namespace
+}
INITIALIZE_PASS(InductiveRangeCheckElimination, "irce",
"Inductive range check elimination", false, false)
bool run();
};
-} // namespace
+}
void LoopConstrainer::replacePHIBlock(PHINode *PN, BasicBlock *Block,
BasicBlock *ReplaceBy) {
bool SimplifyPartiallyRedundantLoad(LoadInst *LI);
bool TryToUnfoldSelect(CmpInst *CondCmp, BasicBlock *BB);
};
-} // namespace
+}
char JumpThreading::ID = 0;
INITIALIZE_PASS_BEGIN(JumpThreading, "jump-threading",
/// Simple Analysis hook. Delete loop L from alias set map.
void deleteAnalysisLoop(Loop *L) override;
};
-} // namespace
+}
char LICM::ID = 0;
INITIALIZE_PASS_BEGIN(LICM, "licm", "Loop Invariant Code Motion", false, false)
AST.deleteValue(I);
}
};
-} // namespace
+} // end anon namespace
/// Try to promote memory values to scalars by sinking stores out of the
/// loop and moving loads to before the loop. We do this by looping over
bool aggregateLoads(SmallVectorImpl<LoadPOPPair> &);
bool combineLoads(SmallVectorImpl<LoadPOPPair> &);
};
-} // namespace
+}
bool LoadCombine::doInitialization(Function &F) {
DEBUG(dbgs() << "LoadCombine function: " << F.getName() << "\n");
bool &Changed, BasicBlock *Preheader);
};
-} // namespace
+}
char LoopDeletion::ID = 0;
INITIALIZE_PASS_BEGIN(LoopDeletion, "loop-deletion",
bool runOnNoncountableLoop();
bool runOnCountableLoop();
};
-} // namespace
+}
char LoopIdiomRecognize::ID = 0;
INITIALIZE_PASS_BEGIN(LoopIdiomRecognize, "loop-idiom", "Recognize loop idioms",
AU.addRequired<TargetLibraryInfoWrapperPass>();
}
};
-} // namespace
+}
char LoopInstSimplify::ID = 0;
INITIALIZE_PASS_BEGIN(LoopInstSimplify, "loop-instsimplify",
bool reroll(Instruction *IV, Loop *L, BasicBlock *Header, const SCEV *IterCount,
ReductionTracker &Reductions);
};
-} // namespace
+}
char LoopReroll::ID = 0;
INITIALIZE_PASS_BEGIN(LoopReroll, "loop-reroll", "Reroll loops", false, false)
AssumptionCache *AC;
DominatorTree *DT;
};
-} // namespace
+}
char LoopRotate::ID = 0;
INITIALIZE_PASS_BEGIN(LoopRotate, "loop-rotate", "Rotate Loops", false, false)
void dump() const;
};
-} // namespace
+}
void RegSortData::print(raw_ostream &OS) const {
OS << "[NumUses=" << UsedByIndices.count() << ']';
const_iterator end() const { return RegSequence.end(); }
};
-} // namespace
+}
void
RegUseTracker::CountRegister(const SCEV *Reg, size_t LUIdx) {
void dump() const;
};
-} // namespace
+}
/// DoInitialMatch - Recursion helper for InitialMatch.
static void DoInitialMatch(const SCEV *S, Loop *L,
SmallPtrSetImpl<const SCEV *> *LoserRegs);
};
-} // namespace
+}
/// RateRegister - Tally up interesting quantities from the given register.
void Cost::RateRegister(const SCEV *Reg,
void dump() const;
};
-} // namespace
+}
LSRFixup::LSRFixup()
: UserInst(nullptr), OperandValToReplace(nullptr), LUIdx(~size_t(0)),
void dump() const;
};
-} // namespace
+}
/// HasFormula - Test whether this use as a formula which has the same
/// registers as the given formula.
void dump() const;
};
-} // namespace
+}
/// OptimizeShadowIV - If IV is used in a int-to-float cast
/// inside the loop then try to eliminate the cast operation.
void dump() const;
};
-} // namespace
+}
void WorkItem::print(raw_ostream &OS) const {
OS << "in formulae referencing " << *OrigReg << " in use " << LUIdx
void getAnalysisUsage(AnalysisUsage &AU) const override;
};
-} // namespace
+}
char LoopStrengthReduce::ID = 0;
INITIALIZE_PASS_BEGIN(LoopStrengthReduce, "loop-reduce",
unsigned DynamicCostSavingsDiscount,
uint64_t UnrolledCost, uint64_t RolledDynamicCost);
};
-} // namespace
+}
char LoopUnroll::ID = 0;
INITIALIZE_PASS_BEGIN(LoopUnroll, "loop-unroll", "Unroll loops", false, false)
BasicBlock **LoopExit = nullptr);
};
-} // namespace
+}
// Analyze loop. Check its size, calculate is it possible to unswitch
// it. Returns true if we can unswitch this loop.
return Changed;
}
};
-} // namespace
+}
char LowerAtomic::ID = 0;
INITIALIZE_PASS(LowerAtomic, "loweratomic",
bool runOnFunction(Function &F) override { return lowerExpectIntrinsic(F); }
};
-} // namespace
+}
char LowerExpectIntrinsic::ID = 0;
INITIALIZE_PASS(LowerExpectIntrinsic, "lower-expect",
bool isProfitableToUseMemset(const DataLayout &DL) const;
};
-} // namespace
+} // end anon namespace
bool MemsetRange::isProfitableToUseMemset(const DataLayout &DL) const {
// If we found more than 4 stores to merge or 16 bytes, use memset.
};
-} // namespace
+} // end anon namespace
/// addRange - Add a new store to the MemsetRanges data structure. This adds a
};
char MemCpyOpt::ID = 0;
-} // namespace
+}
// createMemCpyOptPass - The public interface to this file...
FunctionPass *llvm::createMemCpyOptPass() { return new MemCpyOpt(); }
};
char MergedLoadStoreMotion::ID = 0;
-} // namespace
+}
///
/// \brief createMergedLoadStoreMotionPass - The public interface to this file.
};
char PartiallyInlineLibCalls::ID = 0;
-} // namespace
+}
INITIALIZE_PASS(PartiallyInlineLibCalls, "partially-inline-libcalls",
"Partially inline calls to library functions", false, false)
AU.setPreservesAll();
}
};
-} // namespace
+}
static cl::opt<bool> NoEntry("spp-no-entry", cl::Hidden, cl::init(false));
static cl::opt<bool> NoCall("spp-no-call", cl::Hidden, cl::init(false));
// if that was worth doing
}
};
-} // namespace
+}
// Insert a safepoint poll immediately before the given instruction. Does
// not handle the parsability of state at the runtime call, that's the
unsigned SymbolicRank;
bool isOr;
};
-} // namespace
+}
namespace {
class Reassociate : public FunctionPass {
void OptimizeInst(Instruction *I);
Instruction *canonicalizeNegConstExpr(Instruction *I);
};
-} // namespace
+}
XorOpnd::XorOpnd(Value *V) {
assert(!isa<ConstantInt>(V) && "No ConstantInt");
bool runOnFunction(Function &F) override;
};
-} // namespace
+}
char RegToMem::ID = 0;
INITIALIZE_PASS_BEGIN(RegToMem, "reg2mem", "Demote all values to stack slots",
/// Maps rematerialized copy to it's original value.
RematerializedValueMapTy RematerializedValues;
};
-} // namespace
+}
/// Compute the live-in set for every basic block in the function
static void computeLiveInValues(DominatorTree &DT, Function &F,
llvm_unreachable("only three states!");
}
};
-} // namespace
+}
/// For a given value or instruction, figure out what base ptr it's derived
/// from. For gc objects, this is simply itself. On success, returns a value
/// which is the base pointer. (This is reliable and can be used for
typedef llvm::IRBuilder<false, ConstantFolder, IRBuilderPrefixedInserter<false>>
IRBuilderTy;
#endif
-} // namespace
+}
namespace {
/// \brief A used slice of an alloca.
/// the alloca.
SmallVector<Use *, 8> DeadOperands;
};
-} // namespace
+}
static Value *foldSelectInst(SelectInst &SI) {
// If the condition being selected on is a constant or the same value is
}
}
};
-} // namespace
+} // end anon namespace
namespace {
/// \brief An optimization pass providing Scalar Replacement of Aggregates.
void deleteDeadInstructions(SmallPtrSetImpl<AllocaInst *> &DeletedAllocas);
bool promoteAllocas(Function &F);
};
-} // namespace
+}
char SROA::ID = 0;
return true;
}
};
-} // namespace
+}
namespace {
/// \brief Visitor to rewrite aggregate loads and stores as scalar.
return false;
}
};
-} // namespace
+}
/// \brief Strip aggregate type wrapping.
///
/// \brief Flag indicating whether the profile input loaded successfully.
bool ProfileIsValid;
};
-} // namespace
+}
/// \brief Print the weight of edge \p E on stream \p OS.
///
}
};
-} // namespace
+}
char SROA_DT::ID = 0;
char SROA_SSAUp::ID = 0;
}
}
};
-} // namespace
+} // end anon namespace
/// isSafeSelectToSpeculate - Select instructions that use an alloca and are
/// subsequently loaded can be rewritten to load both input pointers and then
AU.addRequired<TargetTransformInfoWrapperPass>();
}
};
-} // namespace
+}
char CFGSimplifyPass::ID = 0;
INITIALIZE_PASS_BEGIN(CFGSimplifyPass, "simplifycfg", "Simplify the CFG", false,
bool CanMoveAboveCall(Instruction *I, CallInst *CI);
Value *CanTransformAccumulatorRecursion(Instruction *I, CallInst *CI);
};
-} // namespace
+}
char TailCallElim::ID = 0;
INITIALIZE_PASS_BEGIN(TailCallElim, "tailcallelim",
SmallPtrSet<Instruction *, 32> AllocaUsers;
SmallPtrSet<Instruction *, 32> EscapePoints;
};
-} // namespace
+}
bool TailCallElim::markTails(Function &F, bool &AllCallsAreTailCalls) {
if (F.callsFunctionThatReturnsTwice())
assert(Layout->FrameSize / Granularity == Layout->ShadowBytes.size());
}
-} // namespace llvm
+} // llvm namespace
AU.addPreservedID(LoopSimplifyID);
}
};
-} // namespace
+}
char BreakCriticalEdges::ID = 0;
INITIALIZE_PASS(BreakCriticalEdges, "break-crit-edges",
DivPhiNodes(PHINode *InQuotient, PHINode *InRemainder)
: Quotient(InQuotient), Remainder(InRemainder) {}
};
-} // namespace
+}
namespace llvm {
template<>
};
typedef DenseMap<DivOpInfo, DivPhiNodes> DivCacheTy;
-} // namespace llvm
+}
// insertFastDiv - Substitutes the div/rem instruction with code that checks the
// value of the operands and uses a shorter-faster div/rem instruction when
BasicBlock::const_iterator StartingInst,
std::vector<const BasicBlock*> &ToClone);
};
-} // namespace
+}
/// The specified block is found to be reachable, clone it and
/// anything that it can reach.
return true;
}
-} // namespace llvm
+} // End llvm namespace
FlattenCFGOpt(AliasAnalysis *AA) : AA(AA) {}
bool run(BasicBlock *BB);
};
-} // namespace
+}
/// If \param [in] BB has more than one predecessor that is a conditional
/// branch, attempt to use parallel and/or for the branch condition. \returns
}
}
};
-} // namespace
+}
/// Get or create a target for the branch from ResumeInsts.
BasicBlock *InvokeInliningInfo::getInnerResumeDest() {
};
char InstNamer::ID = 0;
-} // namespace
+}
INITIALIZE_PASS(InstNamer, "instnamer",
"Assign names to anonymous instructions", false, false)
AU.addPreserved<ScalarEvolution>();
}
};
-} // namespace
+}
char LCSSA::ID = 0;
INITIALIZE_PASS_BEGIN(LCSSA, "lcssa", "Loop-Closed SSA Form Pass", false, false)
/// verifyAnalysis() - Verify LoopSimplifyForm's guarantees.
void verifyAnalysis() const override;
};
-} // namespace
+}
char LoopSimplify::ID = 0;
INITIALIZE_PASS_BEGIN(LoopSimplify, "loop-simplify",
return CI1->getValue().slt(CI2->getValue());
}
};
-} // namespace
+}
char LowerSwitch::ID = 0;
INITIALIZE_PASS(LowerSwitch, "lowerswitch",
return true;
}
};
-} // namespace
+}
char MetaRenamer::ID = 0;
INITIALIZE_PASS(MetaRenamer, "metarenamer",
}
};
-} // namespace llvm
+} // End llvm namespace
/// Check to see if AvailableVals has an entry for the specified BB and if so,
/// return it. If not, construct SSA form by first calculating the required
: TTI(TTI), DL(DL), BonusInstThreshold(BonusInstThreshold), AC(AC) {}
bool run(BasicBlock *BB);
};
-} // namespace
+}
/// SafeToMergeTerminators - Return true if it is safe to merge these two
/// terminator instructions together.
}
};
-} // namespace
+}
static void EraseTerminatorInstAndDCECond(TerminatorInst *TI) {
Instruction *Cond = nullptr;
// For ArrayKind, this is the array.
GlobalVariable *Array;
};
-} // namespace
+}
SwitchLookupTable::SwitchLookupTable(
Module &M, uint64_t TableSize, ConstantInt *Offset,
Instruction *splitOverflowIntrinsic(Instruction *IVUser,
const DominatorTree *DT);
};
-} // namespace
+}
/// Fold an IV operand into its use. This removes increments of an
/// aligned IV when used by a instruction that ignores the low bits.
return Changed;
}
};
-} // namespace
+}
char InstSimplifier::ID = 0;
INITIALIZE_PASS_BEGIN(InstSimplifier, "instsimplify",
for (const auto &MapFile : MapFiles)
parser.parse(MapFile, &Descriptors);
}
-} // namespace
+}
INITIALIZE_PASS(RewriteSymbols, "rewrite-symbols", "Rewrite Symbols", false,
false)
DEBUG(dbgs() << "BBV: final: \n" << BB << "\n");
}
-} // namespace
+}
char BBVectorize::ID = 0;
static const char bb_vectorize_name[] = "Basic-Block Vectorization";
return LHS->isIdenticalTo(RHS);
}
};
-} // namespace
+}
/// \brief Check whether this block is a predicated block.
/// Due to if predication of stores we might create a sequence of "if(pred) a[i]
projects / oota-llvm.git / commitdiff