Merge branches 'pci/host-designware', 'pci/host-xgene' and 'pci/host-xilinx' into...

* pci/host-designware:
  PCI: designware: Don't complain missing *config* reg space if va_cfg0 is set

* pci/host-xgene:
  PCI: xgene: Add support for a 64-bit prefetchable memory window
  arm64: dts: Add APM X-Gene PCIe 64-bit prefetchable window
  PCI: xgene: Drop owner assignment from platform_driver

* pci/host-xilinx:
  PCI: xilinx: Check for MSI interrupt flag before handling as INTx

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 69486be7181e18287a8a8bd421055b902233e3c4..b48b8a2c50b9df0933c17361b93d84ef1fc565aa 100644 (file)
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -388,7 +388,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
                addrp = of_get_address(np, index, NULL, NULL);
                pp->cfg0_mod_base = of_read_number(addrp, ns);
                pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size;
-       } else {
+       } else if (!pp->va_cfg0_base) {
                dev_err(pp->dev, "missing *config* reg space\n");
        }
 

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index f1a06a091ccb578359656b1d9c4b32c0e99b2d99..dcb9b57ed7eac144467fce85089c8a6bafa2a144 100644 (file)
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -449,14 +449,17 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
                        return IRQ_HANDLED;
                }
 
-               /* Clear interrupt FIFO register 1 */
-               pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
-                          XILINX_PCIE_REG_RPIFR1);
-
-               /* Handle INTx Interrupt */
-               val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
-                       XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
-               generic_handle_irq(irq_find_mapping(port->irq_domain, val));
+               if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) {
+                       /* Clear interrupt FIFO register 1 */
+                       pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
+                                  XILINX_PCIE_REG_RPIFR1);
+
+                       /* Handle INTx Interrupt */
+                       val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
+                               XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
+                       generic_handle_irq(irq_find_mapping(port->irq_domain,
+                                                           val));
+               }
        }
 
        if (status & XILINX_PCIE_INTR_MSI) {