* Force all "don't care" bits to 0 so that there are absolutely no unset bits in

  the TableGen descriptions; all unset bits are thus errors.
* As a result, found and fixed instructions where some operands were not
  actually assigned into the right portion of the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7074 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SparcV9/SparcV9_F3.td b/lib/Target/SparcV9/SparcV9_F3.td
index 83809187ef32e56828c3c475f6a410939a27fee2..c23741838bbe3b28a9de5e0c3a5d1316437ec20e 100644 (file)
--- a/lib/Target/SparcV9/SparcV9_F3.td
+++ b/lib/Target/SparcV9/SparcV9_F3.td
@@ -95,7 +95,7 @@ class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2rd {
   set op3 = op3val;
   set Name = name;
   set Inst{13} = 0;   // i field = 0
-  //set Inst{12-5} = dontcare;
+  set Inst{12-5} = 0; // don't care
 }
 
 // The store instructions seem to like to see rd first, then rs1 and rs2
@@ -104,7 +104,7 @@ class F3_1rd<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
   set op3 = op3val;
   set Name = name;
   set Inst{13} = 0;   // i field = 0
-  //set Inst{12-5} = dontcare;
+  set Inst{12-5} = 0; // don't care
 }
 
 class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rs1simm13rd {
@@ -126,7 +126,9 @@ class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2 {
   set op   = opVal;
   set op3  = op3val;
   set Name = name;
+  set Inst{29-25} = 0; // don't care
   set Inst{13}  = 0;
+  set Inst{12-5} = 0; // don't care
 }
 
 class F3_4<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1simm13 {
@@ -134,7 +136,7 @@ class F3_4<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1simm13 {
   set op   = opVal;
   set op3  = op3Val;
   set Name = name;
-  //set Inst{29-25} = dontcare;
+  set Inst{29-25} = 0; // don't care
   set Inst{13}  = 1;
   set Inst{12-0} = simm;
 }
@@ -146,6 +148,7 @@ class F3_5<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
   set Name = name;
   set Inst{13} = 0;           // i field = 0
   set Inst{12-10} = rcondVal; // rcond field
+  set Inst{9-5} = 0; // don't care
 }
 
 class F3_6<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
@@ -156,8 +159,10 @@ class F3_6<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
   set op  = opVal;
   set op3 = op3Val;
   set Name = name;
+  set Inst{29-25} = rd;
   set Inst{13} = 1;           // i field = 1
   set Inst{12-10} = rcondVal; // rcond field
+  set Inst{9-0} = simm10;
 }
 
 //FIXME: classes 7-10 not defined!!
@@ -169,7 +174,7 @@ class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1rs2rd {
   set Name = name;
   set Inst{13} = 0; // i field = 0
   set Inst{12} = x;
-  //set Inst{11-5} = dontcare;
+  set Inst{11-5} = 0; // don't care
 }
 
 class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1 {
@@ -182,7 +187,7 @@ class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1 {
   set Inst{29-25} = rd;
   set Inst{13} = 1; // i field = 1
   set Inst{12} = 0; // x field = 0
-  //set Inst{11-5} = dontcare;
+  set Inst{11-5} = 0; // don't care
   set Inst{4-0} = shcnt;
 }
 
@@ -196,7 +201,7 @@ class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1 {
   set Inst{29-25} = rd;
   set Inst{13} = 1; // i field = 1
   set Inst{12} = 1; // x field = 1
-  //set Inst{11-6} = dontcare;
+  set Inst{11-6} = 0; // don't care
   set Inst{5-0} = shcnt;
 }
 
@@ -205,7 +210,7 @@ class F3_14<bits<2> opVal, bits<6> op3Val,
   set op  = opVal;
   set op3 = op3Val;
   set Name = name;
-  //set Inst{18-14} = dontcare;
+  set Inst{18-14} = 0; // don't care
   set Inst{13-5} = opfVal;
 }
 
@@ -218,6 +223,7 @@ class F3_15<bits<2> opVal, bits<6> op3Val,
   set op  = opVal;
   set op3 = op3Val;
   set Name = name;
+  set Inst{29-27} = 0; // defined to be zero
   set Inst{26-25} = cc;
   set Inst{18-14} = rs1;
   set Inst{13-5}  = opfVal;
@@ -236,7 +242,7 @@ class F3_17<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1rd {
   set op = opVal;
   set op3 = op3Val;
   set Name = name;
-  //Inst{13-0} = dontcare;
+  set Inst{13-0} = 0; // don't care
 }
 
 class F3_18<bits<5> fcn, string name> : F3 {
@@ -244,14 +250,14 @@ class F3_18<bits<5> fcn, string name> : F3 {
   set op3 = 0b111110;
   set Name = name;
   set Inst{29-25} = fcn;
-  //set Inst{18-0 } = dontcare;
+  set Inst{18-0 } = 0; // don't care;
 }
 
 class F3_19<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
   set op = opVal;
   set op3 = op3Val;
   set Name = name;
-  //Inst{18-0} = dontcare;
+  set Inst{18-0} = 0; // don't care
 }
 
 // FIXME: class F3_20

diff --git a/lib/Target/SparcV9/SparcV9_F4.td b/lib/Target/SparcV9/SparcV9_F4.td
index 981c9f0f764d67d37bfddff3ed3af133b8378369..39b5d9ef49466201cfc530883659ec030461bd53 100644 (file)
--- a/lib/Target/SparcV9/SparcV9_F4.td
+++ b/lib/Target/SparcV9/SparcV9_F4.td
@@ -14,14 +14,12 @@ class F4 : InstV9 {
 // F4_rs1 - Common class of instructions that use an rs1 field
 class F4_rs1 : F4 {
   bits<5> rs1;
-  //set Inst{29-25} = dontcare;
   set Inst{18-14} = rs1;
 }
 
 // F4_rs1rs2 - Common class of instructions that have rs1 and rs2 fields
 class F4_rs1rs2 : F4_rs1 {
   bits<5> rs2;
-  //set Inst{12-5} = dontcare;
   set Inst{4-0} = rs2;
 }
 
@@ -64,7 +62,7 @@ class F4_1<bits<2> opVal, bits<6> op3Val, string name> : F4_rs1rs2rd {
   set Name = name;
   set Inst{13} = 0; // i bit
   set Inst{12-11} = cc;
-  //set Inst{10-5} = dontcare;
+  set Inst{10-5} = 0; // don't care
 }
 
 class F4_2<bits<2> opVal, bits<6> op3Val, string name> : F4_rs1simm11rd {
@@ -88,7 +86,7 @@ class F4_3<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
   set Name = name;
   set Inst{29-25} = rd;
   set Inst{13} = 0; // i bit
-  //set Inst{10-5} = dontcare;
+  set Inst{10-5} = 0; // don't care
   set Inst{4-0} = rs2;
 }