construct on ARM, which was breaking by coincidence, and add a similar
testcase for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79719
91177308-0d34-0410-b5e6-
96231b3b80d8
N->getOperand(0), NegatedCount);
}
- assert(VT == MVT::i64 &&
- (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
+ // We can get here for a node like i32 = ISD::SHL i32, i64
+ if (VT != MVT::i64)
+ return SDValue();
+
+ assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
"Unknown shift to lower!");
// We only lower SRA, SRL of 1 here, all others use generic lowering.
--- /dev/null
+; RUN: llvm-as < %s | llc -march=arm -mattr=-neon
+
+; Example that requires splitting and expanding a vector shift.
+define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
+entry:
+ %shr = lshr <2 x i64> %val, < i64 2, i64 2 > ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %shr
+}
-; RUN: llvm-as < %s | llc
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
; Example that requires splitting and expanding a vector shift.
define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
entry:
- %shr = lshr <2 x i64> %val, < i64 2, i64 2 > ; <<2 x i64>> [#uses=1]
+ %shr = lshr <2 x i64> %val, < i64 2, i64 3 >
ret <2 x i64> %shr
}