[Hexagon] Adding combine reg, reg with predicated forms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223667 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td
index 3158adcfa5e5d55e0f814d00b9819a2f023d8be9..99a02a9a2331e5a7d085ae3fb85e6c69e7e1f1e6 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -208,6 +208,13 @@ def: BinOp32_pat<xor, A2_xor, i32>;
 let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0,
     isCodeGenOnly = 0 in {
   def S2_packhl    : T_ALU32_3op  <"packhl",  0b101, 0b100, 0, 0>;
+
+  let isPredicable = 1 in
+    def A2_combinew  : T_ALU32_3op  <"combine", 0b101, 0b000, 0, 0>;
+
+  // Conditional combinew uses "newt/f" instead of "t/fnew".
+  def C2_ccombinewt    : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
+  def C2_ccombinewf    : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
 }
 
 let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg"  in

diff --git a/test/MC/Disassembler/Hexagon/alu32_perm.txt b/test/MC/Disassembler/Hexagon/alu32_perm.txt
index 2f1d1b65067aae0a6512ce2f7706871c22ad0efa..d8952102ec71bdc121d732517890b79034d693b1 100644 (file)
--- a/test/MC/Disassembler/Hexagon/alu32_perm.txt
+++ b/test/MC/Disassembler/Hexagon/alu32_perm.txt
@@ -10,6 +10,8 @@
 # CHECK: r17 = combine(r31.l, r21.l)
 0xb0 0xe2 0x0f 0x7c
 # CHECK: r17:16 = combine(#21, #31)
+0x10 0xdf 0x15 0xf5
+# CHECK: r17:16 = combine(r21, r31)
 0xf1 0xc3 0x75 0x73
 # CHECK: r17 = mux(p3, r21, #31)
 0xb1 0xc2 0xff 0x73

diff --git a/test/MC/Disassembler/Hexagon/alu32_pred.txt b/test/MC/Disassembler/Hexagon/alu32_pred.txt
index c85b86b5135d5d1ace189f7c4b417670a1ceb8cb..c17bd0fdeb9c9767602cc0e453738c2c514624e7 100644 (file)
--- a/test/MC/Disassembler/Hexagon/alu32_pred.txt
+++ b/test/MC/Disassembler/Hexagon/alu32_pred.txt
@@ -6,6 +6,10 @@
 # CHECK: if (p3) r17 = aslh(r21)
 0x11 0xe3 0x35 0x70
 # CHECK: if (p3) r17 = asrh(r21)
+0x70 0xdf 0x15 0xfd
+# CHECK: if (p3) r17:16 = combine(r21, r31)
+0xf0 0xdf 0x15 0xfd
+# CHECK: if (!p3) r17:16 = combine(r21, r31)
 0x71 0xdf 0x15 0xf9
 # CHECK: if (p3) r17 = and(r21, r31)
 0x71 0xdf 0x35 0xf9