{
pll_value_t pll;
unsigned int ulActualMxClk;
-#if 1
+
/* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */
if (getChipType() == SM750LE)
return;
-#endif
if (frequency) {
/*
static void setMemoryClock(unsigned int frequency)
{
unsigned int ulReg, divisor;
- #if 1
+
/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */
if (getChipType() == SM750LE)
return;
-#endif
+
if (frequency) {
/* Set the frequency to the maximum frequency that the DDR Memory can take
which is 336MHz. */
static void setMasterClock(unsigned int frequency)
{
unsigned int ulReg, divisor;
-#if 1
+
/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */
if (getChipType() == SM750LE)
return;
-#endif
+
if (frequency) {
/* Set the frequency to the maximum frequency that the SM750 engine can
run, which is about 190 MHz. */
unsigned int tmpClock, ret;
pllcalparam *xparm;
-#if 1
if (getChipType() == SM750LE) {
/* SM750LE don't have prgrammable PLL and M/N values to work on.
Just return the requested clock. */
return request_orig;
}
-#endif
ret = 0;
mini_diff = ~0;
*/
POKE32(PANEL_DISPLAY_CTRL, ulTmpValue|ulReg);
-#if 1
+
while ((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) != (ulTmpValue|ulReg)) {
cnt++;
if (cnt > 1000)
break;
POKE32(PANEL_DISPLAY_CTRL, ulTmpValue|ulReg);
}
-#endif
} else {
ret = -1;
}
ret = 0;
par = container_of(crtc, struct lynxfb_par, crtc);
share = par->share;
-#if 1
+
if (!share->accel_off) {
/* set 2d engine pixel format according to mode bpp */
switch (var->bits_per_pixel) {
}
hw_set2dformat(&share->accel, fmt);
}
-#endif
/* set timing */
modparm.pixel_clock = ps_to_hz(var->pixclock);