misched: allow the default scheduler to be one chosen by the target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152360 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/MachineScheduler.h b/include/llvm/CodeGen/MachineScheduler.h
index aded11fb65879f631d158957fef896463b1b3bc4..e852009f7e8baed3a0bab48ae18d00e5dcddc703 100644 (file)
--- a/include/llvm/CodeGen/MachineScheduler.h
+++ b/include/llvm/CodeGen/MachineScheduler.h
@@ -15,8 +15,12 @@
 //  return new CustomMachineScheduler(C);
 // }
 // static MachineSchedRegistry
-// SchedDefaultRegistry("custom", "Run my target's custom scheduler",
-//                      createCustomMachineSched);
+// SchedCustomRegistry("custom", "Run my target's custom scheduler",
+//                     createCustomMachineSched);
+//
+// Inside <Target>PassConfig:
+//   enablePass(MachineSchedulerID);
+//   MachineSchedRegistry::setDefault(createCustomMachineSched);
 //
 //===----------------------------------------------------------------------===//
 
@@ -39,10 +43,11 @@ struct MachineSchedContext {
   MachineFunction *MF;
   const MachineLoopInfo *MLI;
   const MachineDominatorTree *MDT;
+  const TargetPassConfig *PassConfig;
   AliasAnalysis *AA;
   LiveIntervals *LIS;
 
-  MachineSchedContext(): MF(0), MLI(0), MDT(0), AA(0), LIS(0) {}
+  MachineSchedContext(): MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {}
 };
 
 /// MachineSchedRegistry provides a selection of available machine instruction

diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp
index 80862157cc4813f1b2f2b373c20ac74a35568b5e..f8921922ed7527a101acc66f0d4c564c803b45ac 100644 (file)
--- a/lib/CodeGen/MachineScheduler.cpp
+++ b/lib/CodeGen/MachineScheduler.cpp
@@ -82,7 +82,7 @@ void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.addRequiredID(MachineDominatorsID);
   AU.addRequired<MachineLoopInfo>();
   AU.addRequired<AliasAnalysis>();
-  AU.addPreserved<AliasAnalysis>();
+  AU.addRequired<TargetPassConfig>();
   AU.addRequired<SlotIndexes>();
   AU.addPreserved<SlotIndexes>();
   AU.addRequired<LiveIntervals>();
@@ -92,31 +92,47 @@ void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
 
 MachinePassRegistry MachineSchedRegistry::Registry;
 
-static ScheduleDAGInstrs *createDefaultMachineSched(MachineSchedContext *C);
+/// A dummy default scheduler factory indicates whether the scheduler
+/// is overridden on the command line.
+static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) {
+  return 0;
+}
 
 /// MachineSchedOpt allows command line selection of the scheduler.
 static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
                RegisterPassParser<MachineSchedRegistry> >
 MachineSchedOpt("misched",
-                cl::init(&createDefaultMachineSched), cl::Hidden,
+                cl::init(&useDefaultMachineSched), cl::Hidden,
                 cl::desc("Machine instruction scheduler to use"));
 
+static MachineSchedRegistry
+SchedDefaultRegistry("default", "Use the target's default scheduler choice.",
+                     useDefaultMachineSched);
+
+/// Forward declare the common machine scheduler. This will be used as the
+/// default scheduler if the target does not set a default.
+static ScheduleDAGInstrs *createCommonMachineSched(MachineSchedContext *C);
+
 bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
   // Initialize the context of the pass.
   MF = &mf;
   MLI = &getAnalysis<MachineLoopInfo>();
   MDT = &getAnalysis<MachineDominatorTree>();
+  PassConfig = &getAnalysis<TargetPassConfig>();
   AA = &getAnalysis<AliasAnalysis>();
 
   LIS = &getAnalysis<LiveIntervals>();
   const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
 
   // Select the scheduler, or set the default.
-  MachineSchedRegistry::ScheduleDAGCtor Ctor =
-    MachineSchedRegistry::getDefault();
-  if (!Ctor) {
-    Ctor = MachineSchedOpt;
-    MachineSchedRegistry::setDefault(Ctor);
+  MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
+  if (Ctor == useDefaultMachineSched) {
+    // Get the default scheduler set by the target.
+    Ctor = MachineSchedRegistry::getDefault();
+    if (!Ctor) {
+      Ctor = createCommonMachineSched;
+      MachineSchedRegistry::setDefault(Ctor);
+    }
   }
   // Instantiate the selected scheduler.
   OwningPtr<ScheduleDAGInstrs> Scheduler(Ctor(this));
@@ -283,10 +299,10 @@ void ScheduleTopDownLive::schedule() {
 //===----------------------------------------------------------------------===//
 
 namespace {
-class DefaultMachineScheduler : public ScheduleDAGInstrs {
+class CommonMachineScheduler : public ScheduleDAGInstrs {
   AliasAnalysis *AA;
 public:
-  DefaultMachineScheduler(MachineSchedContext *C):
+  CommonMachineScheduler(MachineSchedContext *C):
     ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
     AA(C->AA) {}
 
@@ -296,17 +312,18 @@ public:
 };
 } // namespace
 
-static ScheduleDAGInstrs *createDefaultMachineSched(MachineSchedContext *C) {
-  return new DefaultMachineScheduler(C);
+/// The common machine scheduler will be used as the default scheduler if the
+/// target does not set a default.
+static ScheduleDAGInstrs *createCommonMachineSched(MachineSchedContext *C) {
+  return new CommonMachineScheduler(C);
 }
 static MachineSchedRegistry
-SchedDefaultRegistry("default", "Activate the scheduler pass, "
-                     "but don't reorder instructions",
-                     createDefaultMachineSched);
+SchedCommonRegistry("common", "Use the target's default scheduler choice.",
+                     createCommonMachineSched);
 
 /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
 /// time to do some work.
-void DefaultMachineScheduler::schedule() {
+void CommonMachineScheduler::schedule() {
   buildSchedGraph(AA);
 
   DEBUG(dbgs() << "********** MI Scheduling **********\n");