Intel mode no longer uses %'s on registers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28028 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/2005-08-30-RegAllocAliasProblem.ll b/test/CodeGen/X86/2005-08-30-RegAllocAliasProblem.ll
index 509c07b74ae67c88df801fc091c0e17f0384c5a0..8aa5f4da5ded4ce9cdceb12b36170a28b3123e2e 100644 (file)
--- a/test/CodeGen/X86/2005-08-30-RegAllocAliasProblem.ll
+++ b/test/CodeGen/X86/2005-08-30-RegAllocAliasProblem.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'test.*%AL' || \
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'cmove.*%EAX'
+; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'test.*AL' || \
+; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'cmove.*EAX'
 
 ; This testcase was compiling to:
 ;

diff --git a/test/CodeGen/X86/2005-12-03-IndirectTailCall.ll b/test/CodeGen/X86/2005-12-03-IndirectTailCall.ll
index e5a08e9a0642d7d9aee4c11a7a21bffbb1705246..4efc4b7ce8a862ce6ae6bbac0619a6510cab29e9 100644 (file)
--- a/test/CodeGen/X86/2005-12-03-IndirectTailCall.ll
+++ b/test/CodeGen/X86/2005-12-03-IndirectTailCall.ll
@@ -1,5 +1,5 @@
 ; XFAIL: *
-; RUN: llvm-as < %s | llc -march=x86 -enable-x86-fastcc | grep 'jmp \*%ecx'
+; RUN: llvm-as < %s | llc -march=x86 -enable-x86-fastcc | grep 'jmp \*ecx'
 declare int %putchar(int)
 
 int %main(){ 

diff --git a/test/CodeGen/X86/fast-cc-merge-stack-adj.ll b/test/CodeGen/X86/fast-cc-merge-stack-adj.ll
index de8372cbc4968257e259065823b098e03a43131e..f31b180b2718899c56a552512a86420acd2cf17d 100644 (file)
--- a/test/CodeGen/X86/fast-cc-merge-stack-adj.ll
+++ b/test/CodeGen/X86/fast-cc-merge-stack-adj.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc  | grep 'add %ESP, 8'
+; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc  | grep 'add ESP, 8'
 
 target triple = "i686-pc-linux-gnu"
 

diff --git a/test/CodeGen/X86/fast-cc-pass-in-regs.ll b/test/CodeGen/X86/fast-cc-pass-in-regs.ll
index c9f9cee703a138a6b85e448aefa6ac505f288073..6899683c4c474a64e88e3c87388d2b35ca912a4c 100644 (file)
--- a/test/CodeGen/X86/fast-cc-pass-in-regs.ll
+++ b/test/CodeGen/X86/fast-cc-pass-in-regs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc  | grep 'mov %EDX, 1'
+; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc  | grep 'mov EDX, 1'
 ; check that fastcc is passing stuff in regs.
 
 ; Argument reg passing is disabled due to regalloc issues.  FIXME!

diff --git a/test/CodeGen/X86/overlap-add.ll b/test/CodeGen/X86/overlap-add.ll
index 70878a102f44704bbad013ddae38bd73231f8780..c5fc0bd89af2f92df05b22b783c92a7255ad4367 100644 (file)
--- a/test/CodeGen/X86/overlap-add.ll
+++ b/test/CodeGen/X86/overlap-add.ll
@@ -6,7 +6,7 @@
 
 ; Check that the shift gets turned into an LEA.
 
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'mov %E.X, %E.X'
+; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'mov E.X, E.X'
 
 ; FIXME: We need live variable information about flags to do this xform safely. :(
 ; XFAIL: *

diff --git a/test/CodeGen/X86/overlap-shift.ll b/test/CodeGen/X86/overlap-shift.ll
index 4d8c68811894a0141f6e21563145f2e357f8594a..48f91e0cba9cacaac9b2390dec81b75c67a922da 100644 (file)
--- a/test/CodeGen/X86/overlap-shift.ll
+++ b/test/CodeGen/X86/overlap-shift.ll
@@ -6,7 +6,7 @@
 
 ; Check that the shift gets turned into an LEA.
 
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'mov %E.X, %E.X'
+; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'mov E.X, E.X'
 
 %G = external global int